US20210091046A1 - Integrated semiconductor assemblies and methods of manufacturing the same - Google Patents
Integrated semiconductor assemblies and methods of manufacturing the same Download PDFInfo
- Publication number
- US20210091046A1 US20210091046A1 US16/995,092 US202016995092A US2021091046A1 US 20210091046 A1 US20210091046 A1 US 20210091046A1 US 202016995092 A US202016995092 A US 202016995092A US 2021091046 A1 US2021091046 A1 US 2021091046A1
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- cavity
- assembly
- die
- substrate
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Images
Classifications
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
- This application is a continuation of U.S. patent application Ser. No. 15/683,609, filed Aug. 22, 2017, which is incorporated herein by reference in its entirety.
- The present technology is directed to packaging semiconductor devices, such as memory and processors, and several embodiments are directed to integrated semiconductor assemblies including substrates having cavities.
- Packaged semiconductor dies, including memory dies, microprocessor dies, and interface dies, typically include a semiconductor die mounted on a substrate and encased in a plastic protective covering. The die includes functional features, such as memory cells, processor circuits, and interconnecting circuitry, as well as bond pads electrically connected to the functional features. The bond pads are often electrically connected to external terminals that extend outside of the protective covering to allow the die to be connected to busses, circuits or other higher level circuitry.
- Semiconductor die manufacturers are under increasing pressure to continually reduce the size of die packages to fit within the space constraints of electronic devices, while also increasing the functional capacity of each package to meet operating parameters. One approach for increasing the processing power of a semiconductor package without substantially increasing the surface area covered by the package (i.e., the package's “footprint”) is to vertically stack multiple semiconductor dies on top of one another in a single package. Stacking multiple dies, however, increases the vertical profile of the device, requiring the individual dies to be thinned substantially to achieve a vertically compact size. Additionally, the stacking of multiple dies can increase the probability of device failure, and lead to higher costs associated with longer manufacturing and testing times.
-
FIG. 1A is a schematic cross-sectional view of a semiconductor device assembly configured in accordance with an embodiment of the present technology. -
FIG. 1B is a schematic top view of the semiconductor device assembly shown inFIG. 1A taken alongline 1B-1B. -
FIGS. 2A-2C are schematic cross-sectional views illustrating a method of forming a semiconductor device assembly in accordance with an embodiment of the present technology. -
FIG. 3 is a schematic top view of a semiconductor device assembly configured in accordance with another embodiment of the present technology. -
FIGS. 4-7 are schematic cross-sectional views of semiconductor device assemblies configured in accordance with other embodiments of the present technology. -
FIG. 8 is a schematic view of a system that includes a semiconductor die assembly configured in accordance with embodiments of the present technology. - Specific details of several embodiments of stacked semiconductor die packages and methods of manufacturing such die packages are described below. The term “semiconductor device” generally refers to a solid-state device that includes semiconductor material. A semiconductor device can include, for example, a semiconductor substrate, wafer, or die that is singulated from a wafer or substrate. Throughout the disclosure, semiconductor devices are generally described in the context of semiconductor dies; however, semiconductor devices are not limited to semiconductor dies.
- The term “semiconductor device package” can refer to an arrangement with one or more semiconductor devices incorporated into a common package. A semiconductor package can include a housing or casing that partially or completely encapsulates at least one semiconductor device. A semiconductor device package can also include an interposer substrate that carries one or more semiconductor devices and is attached to or otherwise incorporated into the casing. The term “stacked package assembly” can refer to an assembly of one or more individual semiconductor device packages stacked on each other or a package-on-package assembly.
- As used herein, the terms “vertical,” “lateral,” “top,” “bottom,” “upper,” and “lower” can refer to relative directions or positions of features in the semiconductor device or package in view of the orientation shown in the Figures. For example, “upper” or “outermost” can refer to a feature positioned closer to the top of a page than another feature. These terms, however, should be construed broadly to include semiconductor devices having other orientations, such as inverted or inclined orientations where top/bottom, over/under, above/below, up/down, vertical/horizontal and left/right can be interchanged depending on the orientation.
-
FIG. 1A is a schematic cross-sectional view of a semiconductor device assembly 100 (“assembly 100”) configured in accordance with an embodiment of the present technology, andFIG. 1B is a schematic top view of theassembly 100 shown inFIG. 1A taken alongline 1B-1B. Theassembly 100 shown inFIG. 1A is taken alongline 1A-1A ofFIG. 1B . Referring toFIGS. 1A and 1B together, theassembly 100 includes abase substrate 110, afirst die 120 mounted to thesubstrate 110, and asecond die 130 mounted to thesubstrate 110. Thesubstrate 110 includes afirst side 111 a, asecond side 111 b opposite thefirst side 111 a, acavity 115 at thefirst side 111 a, and one or more power and/orsignal layers 117 having circuitry (e.g., copper traces and vias) for electrically coupling the first and second semiconductor dies 120, 130 to each other, other electrical devices, and/or electrical connectors 116 (e.g., solder balls, gold fingers, or other interconnections). Thesubstrate 110, for example, can be a printed circuit board (PCB) or other type of substrate commonly used in semiconductor device packages. In some embodiments, thesubstrate 110 can be formed at least in part from silicon. Thesubstrate 110 includes a cavity region (C) and a perimeter region (P) at least partially surrounding the cavity region (C). As such, thesubstrate 110 includes a continuous outermost surface including at least anupper surface 112 a of the perimeter region (P), alower surface 112 b of the cavity region (C), andsidewalls 128. In the illustrated embodiment, the perimeter region (P) completely surrounds the cavity region (C). - The
cavity 115 is positioned in the cavity region (C) of the substrate, and is defined by thesidewalls 128 and thelower surface 112 b. Thesidewalls 128 extend at least partially through thesubstrate 110 to an intermediate depth, or a second distance (D2). In some embodiments, thesidewalls 128 can extend through thesubstrate 110 from thefirst side 111 a to thesecond side 111 b. In the illustrated embodiment ofFIG. 1B , thecavity 115 is positioned entirely within thesubstrate 110 and thus includes foursidewalls 128. In other embodiments, thecavity 115 can extend to or beyond a length or width of thesubstrate 110 and therefore may only include two sidewalls 128 (e.g.,FIG. 3 ). Although thecavity 115 illustrated inFIGS. 1A and 1B has a rectilinear plan with four sidewalls, in other embodiments a cavity can have any one of a number of other shapes, including regular polygons with any number of sides, irregular polygons, ellipses or curvilinear shapes, etc. - The
first die 120 is positioned within thecavity 115 and includes atop surface 121 a and abottom surface 121 b opposite thetop surface 121 a. Thefirst die 120 is attached to thebase substrate 110 via a plurality of electrical connectors 122 (e.g., solder balls, bond pads, etc.) at thebottom side 121 b. Thetop surface 121 a is separated from thelower surface 112 b of thecavity 115 by a first distance (D1). In the illustrated embodiment, the first distance (D1) is less than the second distance (D2) previously described. Accordingly, thefirst die 120 is positioned entirely within thecavity 115 such that thetop surface 121 a of thefirst die 120 is below theupper surface 112 a of the perimeter region (P) of thesubstrate 110. In other embodiments, the first distance (D1) can be equal to (e.g.,FIGS. 2A-2C ) or slightly greater than the second distance (D2). Thefirst die 120 can include a memory device or memory module (e.g., DRAM, LPDRAM, SRAM, DIMM, NVDIMM, RDIMM, LRDIMM, Flash, etc.). In some embodiments, thefirst die 120 can include a logic device and/or processor. - The illustrated embodiment of
FIG. 1A includes only a single die. In some embodiments, additional dies may be included in thecavity 115. For example, a stack of dies in thecavity 115 can be configured as a hybrid memory cube (HMC) in which the lowermost die is a logic die that provides memory control (e.g., DRAM control), and the stacked dies over the lowermost die are DRAM or other memory dies that provide data storage. In such an embodiment, a top surface of the outermost die of the stack is below a bottom surface of thesecond die 130. - The
second die 130 is positioned over a portion of thefirst die 120 and includes atop surface 137 a and abottom surface 137 b. As such, thesecond die 130 traverses thefirst die 120 and thecavity region 115. Thesecond die 130 is attached to thesubstrate 110 at the perimeter region (P) via electrical connectors 132 (e.g., solder balls, bond pads, etc.). Theelectrical connectors 132 can electrically couple thesecond die 130 to (i) thesubstrate 110 and/or (ii) thefirst die 120 via thesubstrate 110. In the illustrated embodiment, thesecond die 130 includes a larger lateral dimension than that of thecavity 115 and thefirst die 120. Thebottom surface 137 b of thesecond die 130 is spaced apart from thelower surface 112 b of the cavity region (C) by a third distance (D3). The third distance (D3) is larger than each of the first distance (D1) and the second distance (D2). Thesecond die 130 can be a logic device, processor, or another memory device. Optionally, theassembly 100 can also include electrical connectors 140 (e.g., solder balls, bond pads, etc.) between the first and second dies 120, 130. In such an embodiment, theelectrical connectors 140 electrically couple thefirst die 120 directly to thesecond die 130. - One benefit of the present technology is the decreased thickness of the
assembly 100 achieved by mounting thefirst die 120 within thecavity 115 and/or below thesecond die 130. Because thefirst die 120 is mounted within thecavity 115, thesecond die 130 can be mounted over thefirst die 120 and proximate theupper surface 112 a of the substrate, thereby decreasing the thickness of the overall assembly. As mentioned previously, stacked devices have higher probabilities of device failure and higher costs associated with longer manufacturing and testing times. Accordingly, assemblies including the present technology can result in higher yields, more efficient manufacturing, and decreased costs. - Another benefit of the present technology is the ability to more efficiently dissipate heat from the
first die 120 and/or thesecond die 130. Unlike conventional stacked devices wherein multiple dies are stacked directly over one another, the present technology includes air gaps between the first and second dies 120, 130 thereby allowing both dies to cool via convection to the surrounding environment. Accordingly, theassembly 100 can maintain a lower average operating temperature compared to a stacked device, resulting in more efficient operation and longer run times. - Yet another benefit of the present technology is the positioning of the
second die 130 relative to thefirst die 120. In conventional stacked assemblies, the processor is often the main heat-generating source and is usually positioned proximate the substrate at the bottom of the stack. This is in part because the processor usually includes the largest lateral dimension relative to the other dies of the stack. This type of arrangement causes heat to become trapped at the bottom of the stack, and results in an overall increased operating temperature for the assembly. Unlike conventional stacked assemblies, thesecond die 130 of the present technology can include a processor and be positioned over thefirst die 120. As such, any heat generated from the processor is released upwards toward the surrounding environment and has less thermal effect on thefirst die 120 within thecavity 115. Therefore, the present technology can result in a lower operating temperature and more efficient device. -
FIGS. 2A-2C are schematic cross-sectional views illustrating a method of forming a semiconductor device assembly (such as or similar to the assembly 100) in accordance with an embodiment of the present technology.FIG. 2A illustrates the method after thecavity 115 has been formed in thesubstrate 110 and thefirst die 120 has been disposed within thecavity 115 between thesidewalls 128. Thecavity 115 can be formed by grinding, dry etching, chemical etching, chemical polishing, chemical-mechanical polishing, or other suitable processes known in the art. The lateral dimension or width of the cavity may be predetermined to ensure thefirst die 120 can fit withincavity 115. Similarly, the depth of thecavity 115 may be predetermined based on the combined height of thefirst die 120 and theelectrical connectors 122 before and/or after reflow. In the illustrated embodiment, thetop surface 121 a of thefirst die 120 is generally co-planar with theupper surface 112 a of the perimeter region (P) of thesubstrate 110. -
FIG. 2B illustrates an embodiment of the method after a mold material 220 (e.g., an underfill material, encapsulant, etc.) has been deposited in thecavity 115 to encapsulate thefirst die 120. In the illustrated embodiment, an outer surface of themold material 220 is flush with theupper surface 112 a of the perimeter region (P) of thesubstrate 110. Thus, in the illustrated embodiment, themold material 220 only partially encapsulates thefirst die 120 because thetop surface 121 a of thefirst die 120 is generally co-planar with theupper surface 112 a of the perimeter region (P) and is thus exposed through themold material 220. In other embodiments, thetop surface 121 a of thefirst die 120 is below theupper surface 112 a (e.g.,FIGS. 1A and 1B ). In such an embodiment, thetop surface 121 a is not exposed through themold material 220, and thus themold material 220 completely encapsulates thefirst die 120. In other embodiments, themold material 220 can be omitted. -
FIG. 2C illustrates an embodiment of the method after thesecond die 130 is disposed over at least a portion of thefirst die 120 and/or thecavity 115 and mounted to thesubstrate 110 at the perimeter region (P). Thesecond die 130 can be electrically coupled to the first die via circuitry of thesubstrate 110. As previously described with reference toFIG. 1A , in some embodiments, the method can further include depositing electrical connectors (not shown) between the first and second dies 120, 130 prior to disposing thesecond die 130 on thesubstrate 110. In such an embodiment, the electrical connectors couple thefirst die 120 directly to thesecond die 130. As described in further detail below with reference toFIGS. 3 and 4 , the method can further include disposing a third die on thesubstrate 110 that is stacked on or spaced apart from thesecond die 130. -
FIG. 3 is a schematic top view of a semiconductor device assembly (“assembly 300”) configured in accordance with another embodiment of the present technology. Theassembly 300 is generally similar to theassembly 100 previously described. For example, theassembly 300 includes thesubstrate 110 having acavity 315 with thefirst die 120 positioned therein. Theassembly 300 includes a cavity region (C) and a perimeter region (P) that only partially surrounds the cavity region (C). Theassembly 300 further includes a second die 330 and a third die 335 each attached to thesubstrate 110 at the perimeter region (P). The second die 330 includes atop surface 331 a and abottom surface 331 b opposite thetop surface 331 a. Thebottom surface 331 b is attached to thesubstrate 110 viaelectrical connectors 132. The third die 335 includes atop surface 336 a and abottom surface 336 b opposite thetop surface 336 a. Thebottom surface 336 b is attached to thesubstrate 110 viaelectrical connectors 132. The second and third dies 330, 335 each traverse a different portion of thefirst die 120. -
FIG. 4 is a schematic cross-sectional view of a semiconductor device assembly 400 (“assembly 400”) configured in accordance with another embodiment of the present technology. Theassembly 400 is generally similar to theassembly 100 previously described. For example, theassembly 400 includes thesubstrate 110 having thecavity 115, thefirst die 120 positioned in thecavity 115, and thesecond die 130 over thefirst die 120 and attached to thesubstrate 110 at the perimeter region (P). Theassembly 400 includes a third die 430 stacked on and attached to thesecond die 130. The third die 430 can be electrically coupled to thesecond die 130 via a plurality of electrical connectors (e.g., solder balls, wirebonds, etc.). In other embodiments, the third die 430 can be attached and electrically coupled to thesecond die 130 via other means including interconnects, die attach films, TSVs, and/or other known methods in the art. A person of ordinary skill in the art will understand that additional dies can be stacked over the third die 430 and/or on thesubstrate 110. -
FIG. 5 is a schematic cross-sectional view of a semiconductor device assembly 500 (“assembly 500”) configured in accordance with another embodiment of the present technology. Theassembly 500 is generally similar to theassembly 100 previously described. For example, theassembly 500 includes thesubstrate 110 having thecavity 115, thefirst die 120 positioned in thecavity 115, and thesecond die 130 over thefirst die 120 and attached to thesubstrate 110 at the perimeter region (P). Theassembly 500 includes asecond cavity 515 at thesecond side 111 b of thesubstrate 110, athird die 520 positioned in thecavity 515 and attached to thesubstrate 110, and afourth die 530 traversing thethird die 520 and attached to thesubstrate 110 at the perimeter region (P) viabond pads 532. Thebond pads 532 can further decrease the thickness of theassembly 500 compared to a die attached to the substrate with solder balls or the like. Thethird die 520 and/or thefourth die 530 can be electrically coupled to thefirst die 120 and/or thesecond die 130 via circuitry of thesubstrate 110. The arrangement of thesecond cavity 515,third die 520, and fourth die 530 at thesecond side 111 b can be similar or identical to the arrangement of thefirst cavity 115,first die 120, and second die 130 at thefirst side 111 a. As such, the features and benefits previously described with reference toassembly 100 andFIGS. 1A-1B , also apply to theassembly 500. In some embodiments, thefourth die 530 can be omitted from theassembly 500. In such an embodiment, theassembly 500 may include electrical connectors (e.g.,electrical connectors 116 fromFIG. 1A ) over the perimeter region (P) at thesecond side 111 b of thesubstrate 110. Theassembly 500 may also include electrical connections, such as edge fingers, interconnection sockets, and other similar structures commonly found on PCBs. -
FIG. 6 is a schematic cross-sectional view of a semiconductor device assembly 600 (“assembly 600”) configured in accordance with another embodiment of the present technology. The assembly 600 includes features generally similar to theassembly 100 previously described. For example, the assembly 600 includes thesubstrate 110 having thecavity 115, and thesecond die 130 attached to thesubstrate 110 at the perimeter region (P). The assembly 600 includes a first die 620 including afirst surface 627 a facing thesecond die 130, and asecond surface 627 b opposite thefirst surface 627 a and facing thesubstrate 110. The first die 620 can be attached to thesecond die 130 via an adhesive tape, die attach film, bond pads, or other methods known in the art. The first die 620 is at least partially within thecavity 115 such that a portion of the first die 620 is between thesidewalls 128 and/or below theupper surface 112 a. In the illustrated embodiment, for example, thesecond surface 627 b is lower than theupper surface 112 a. The first die 620 can be electrically coupled to thesecond die 130, and to thesubstrate 110 via thesecond die 130 andelectrical connectors 132. The first die 620 can include features similar or identical to thefirst die 120 previously described. The assembly 600 can optionally include athird die 650 attached to thesecond die 130 at thetop side 137 a. Thethird die 650 can include features similar or identical to the first or second dies 120, 130 previously described. The assembly 600 can be formed via a similar method as described with reference toFIGS. 2A and 2C , except that the first die 620 is attached to thesecond die 130 before the second die is attached to thesubstrate 110. Thethird die 650 can be attached to thesecond die 130 before or after the first die 620 is attached to thesecond die 130. -
FIG. 7 is a schematic cross-sectional view of a semiconductor device assembly 700 (“assembly 700”) configured in accordance with another embodiment of the present technology. The assembly 700 includes a first die 720 a and a second die 720 b that are between thesidewalls 128 and attached to thesubstrate 110 at thecavity 115 viaelectrical connectors 122. The first and second dies 720 a-b can each include features generally similar to those of thefirst die 120 previously described. The assembly 700 further includes a third die 730 a, a fourth die 730 b, and a fifth die 730 c over at least a portion of either the first and/or second dies 720 a-b. The third, fourth, and fifth dies 730 a-c can each include features general similar to those of thesecond die 130 previously described. The third die 730 a and the fifth die 730 c are each attached to the base substrate viaelectrical connectors 132 with a first portion of theelectrical connectors 132 attached directly to the perimeter region (P) at theupper surface 112 a of thesubstrate 110, and a second portion of theelectrical connectors 132 attached directly to a top surface 721 a of the first die 720 a. As such, the third die 730 a and the fifth die 730 c extend over only a portion of (a) thecavity 115 and (b) the first die 720 a or second die 720 b respectively. The fourth die 730 b is attached directly to the first and second dies 720 a-b viaelectrical connectors 132, with a first portion of theelectrical connectors 132 attached to the top surface 721 a of the first die 720 a and a second portion of theelectrical connectors 132 attached to the top surface 721 b of the second die 720 b. As such, the fourth die 730 b is positioned over thecavity 115 and between thesidewalls 128. In some embodiments, the third, fourth and/or fifth dies 730 a-c may be omitted. For example, the assembly 700 can include only the fourth die 730 b or only the third and fifth dies 730 a,c. - Any one of the semiconductor devices and/or assemblies described above with reference to
FIGS. 1A-7 can be incorporated into any of a myriad of larger and/or more complex systems, a representative example of which issystem 890 shown schematically inFIG. 8 . Thesystem 890 can include a semiconductor assembly 800 (“assembly 800”), apower source 892, adriver 897, aprocessor 896, and/or other subsystems orcomponents 898. Theassembly 800 can include features generally similar to those assemblies described above. The resultingsystem 890 can perform any of a wide variety of functions, such as memory storage, data processing, and/or other suitable functions. Accordingly,representative systems 890 can include, without limitation, hand-held devices (e.g., mobile phones, tablets, digital readers, and digital audio players), computers, and appliances. Components of thesystem 890 may be housed in a single unit or distributed over multiple, interconnected units (e.g., through a communications network). The components of thesystem 890 can also include remote devices and any of a wide variety of computer readable media. - This disclosure is not intended to be exhaustive or to limit the present technology to the precise forms disclosed herein. Although specific embodiments are disclosed herein for illustrative purposes, various equivalent modifications are possible without deviating from the present technology, as those of ordinary skill in the relevant art will recognize. For example, the illustrated embodiments of
FIG. 4 , which includes stacked devices, andFIG. 5 , which includes multiple cavities and dies positioned therein, can be combined or incorporated into other embodiments, such as the illustrated embodiment ofFIG. 6 . In some cases, well-known structures and functions have not been shown or described in detail to avoid unnecessarily obscuring the description of the embodiments of the present technology. For example, a person of ordinary skill in the art will understand that the dies previously described can include a plurality of passive components, such as resistors, capacitors, and/or other types of electrical devices incorporated therein. Although steps of methods may be presented herein in a particular order, alternative embodiments may perform the steps in a different order. Similarly, certain aspects of the present technology disclosed in the context of particular embodiments can be combined or eliminated in other embodiments. Furthermore, while advantages associated with certain embodiments of the present technology may have been disclosed in the context of those embodiments, other embodiments can also exhibit such advantages, and not all embodiments need necessarily exhibit such advantages or other advantages disclosed herein to fall within the scope of the technology. Accordingly, the disclosure and associated technology can encompass other embodiments not expressly shown or described herein, and the invention is not limited except as by the appended claims. - Throughout this disclosure, the singular terms “a,” “an,” and “the” include plural referents unless the context clearly indicates otherwise. Similarly, unless the word “or” is expressly limited to mean only a single item exclusive from the other items in reference to a list of two or more items, then the use of “or” in such a list is to be interpreted as including (a) any single item in the list, (b) all of the items in the list, or (c) any combination of the items in the list. Additionally, the term “comprising,” “including,” and “having” are used throughout to mean including at least the recited feature(s) such that any greater number of the same feature and/or additional types of other features are not precluded. Reference herein to “one embodiment,” “an embodiment,” or similar formulations means that a particular feature, structure, operation, or characteristic described in connection with the embodiment can be included in at least one embodiment of the present technology. Thus, the appearances of such phrases or formulations herein are not necessarily all referring to the same embodiment. Furthermore, various particular features, structures, operations, or characteristics may be combined in any suitable manner in one or more embodiments.
Claims (23)
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CN111033733B (en) | 2023-11-28 |
WO2019040330A1 (en) | 2019-02-28 |
TW201921609A (en) | 2019-06-01 |
CN111033733A (en) | 2020-04-17 |
US20190067245A1 (en) | 2019-02-28 |
KR20200033986A (en) | 2020-03-30 |
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