KR102629195B1 - 패키지 구조, 장치, 보드 카드 및 집적회로를 레이아웃하는 방법 - Google Patents

패키지 구조, 장치, 보드 카드 및 집적회로를 레이아웃하는 방법 Download PDF

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Publication number
KR102629195B1
KR102629195B1 KR1020217042291A KR20217042291A KR102629195B1 KR 102629195 B1 KR102629195 B1 KR 102629195B1 KR 1020217042291 A KR1020217042291 A KR 1020217042291A KR 20217042291 A KR20217042291 A KR 20217042291A KR 102629195 B1 KR102629195 B1 KR 102629195B1
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KR
South Korea
Prior art keywords
area
die
memory
chip
capacitors
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Application number
KR1020217042291A
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English (en)
Korean (ko)
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KR20220044903A (ko
Inventor
솨이 천
즈웨이 추
쥔웨이 장
Original Assignee
캠브리콘 테크놀로지스 코퍼레이션 리미티드
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Publication of KR20220044903A publication Critical patent/KR20220044903A/ko
Application granted granted Critical
Publication of KR102629195B1 publication Critical patent/KR102629195B1/ko

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/392—Floor-planning or layout, e.g. partitioning or placement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2113/00—Details relating to the application field
    • G06F2113/18—Chip packaging
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02372—Disposition of the redistribution layers connecting to a via connection in the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
    • H01L2224/10152—Auxiliary members for bump connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Theoretical Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Architecture (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • Semiconductor Integrated Circuits (AREA)
KR1020217042291A 2020-09-29 2021-08-23 패키지 구조, 장치, 보드 카드 및 집적회로를 레이아웃하는 방법 KR102629195B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
CN202011053319.2A CN114330201A (zh) 2020-09-29 2020-09-29 封装结构、装置、板卡及布局集成电路的方法
CN202011053319.2 2020-09-29
PCT/CN2021/114097 WO2022068467A1 (zh) 2020-09-29 2021-08-23 封装结构、装置、板卡及布局集成电路的方法

Publications (2)

Publication Number Publication Date
KR20220044903A KR20220044903A (ko) 2022-04-12
KR102629195B1 true KR102629195B1 (ko) 2024-01-24

Family

ID=80949583

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020217042291A KR102629195B1 (ko) 2020-09-29 2021-08-23 패키지 구조, 장치, 보드 카드 및 집적회로를 레이아웃하는 방법

Country Status (4)

Country Link
KR (1) KR102629195B1 (zh)
CN (1) CN114330201A (zh)
TW (1) TW202213709A (zh)
WO (1) WO2022068467A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115794434B (zh) * 2022-11-18 2024-05-24 电子科技大学 一种基于共享存储的多裸芯集成微系统及多裸芯交互方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6700794B2 (en) * 2001-07-26 2004-03-02 Harris Corporation Decoupling capacitor closely coupled with integrated circuit
WO2014078134A2 (en) * 2012-11-15 2014-05-22 Amkor Technology, Inc. Method and system for a semiconductor device package with a die-to-die first bond
US9806058B2 (en) * 2015-07-02 2017-10-31 Taiwan Semiconductor Manufacturing Company, Ltd. Chip package having die structures of different heights and method of forming same
US10141253B2 (en) * 2016-11-14 2018-11-27 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
US10153222B2 (en) * 2016-11-14 2018-12-11 Taiwan Semiconductor Manufacturing Company, Ltd. Package structures and methods of forming the same
US20190013283A1 (en) * 2017-07-10 2019-01-10 Powertech Technology Inc. Semiconductor package and manufacturing method thereof
US10978406B2 (en) * 2017-07-13 2021-04-13 Mediatek Inc. Semiconductor package including EMI shielding structure and method for forming the same
CN110473839A (zh) * 2018-05-11 2019-11-19 三星电子株式会社 半导体封装系统

Also Published As

Publication number Publication date
CN114330201A (zh) 2022-04-12
KR20220044903A (ko) 2022-04-12
WO2022068467A1 (zh) 2022-04-07
TW202213709A (zh) 2022-04-01

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