KR102629195B1 - How to layout package structures, devices, board cards, and integrated circuits - Google Patents

Abstract

The present invention provides package structures, integrated circuit devices, board cards, and methods for laying out integrated circuits on dies in package structures. mounting the system-on-chip into a system area chip on a die; mounting memory on a memory area chip on the die; and mounting a plurality of capacitors on a capacitor area chip on the die. Here, the capacitor area is a remaining area other than the system area and the memory area.

Description

How to layout package structures, devices, board cards, and integrated circuits

Related applications

This application claims the priority of a Chinese patent application with application number 2020110533192 filed on September 29, 2020 and titled "Method for Layout Package Structure, Device, Board Card and Integrated Circuit."

The present invention relates to general semiconductors, and specifically to package structures, integrated circuit devices, board cards, and methods of laying out integrated circuits on die of package structures.

CoWoS (chip on wafer on substrate) is an integrated production technology. First, the chip is connected to a silicon wafer through the CoW (chip on wafer) packaging process, and then the CoW chip and substrate are connected to integrate into CoWoS. Through this technology, multiple chips can be packaged into one. Since bare chips on a plane are connected to each other through a silicon interposer, the technical effect of small package volume, low consumption, and few leads can be achieved. . The power of CoWoS is supplied by storage of capacitors.

A commonly known application is to package chips with multiple different functions using CoWoS. When multiple packers are placed, the chip area increases and thus the cost also increases. Therefore, a solution to place capacitors while reducing the area is urgently needed.

In order to solve at least some of the problems existing in the related art, the present invention provides a package structure, an integrated circuit device, a board card, and a method of laying out an integrated circuit on a die of the package structure.

In one aspect, the present invention provides a method of laying out an integrated circuit on a die in a package structure. The method includes mounting a system-on-chip on a system area chip on a die; mounting memory on a memory area chip on the die; and mounting a plurality of capacitors on a capacitor area chip on the die, where the capacitor area is a remaining area other than the system area and the memory area.

In another aspect, the present invention provides a package structure. The package structure includes a system-on-chip installed in a system area on a die; a memory installed in a memory area on the die; and a plurality of capacitors installed in a capacitor area on the die, where the capacitor area is a remaining area other than the system area and the memory area.

In another aspect, the present invention discloses an integrated circuit device including the package structure, and further discloses a board card including the integrated circuit device.

The technical solution of the present invention can increase the capacitance value and save manufacturing costs by reducing the area by appropriately planning the layout of the capacitor in order to sufficiently utilize the area of the die.

The above and other objects, features and advantages of implementations of the present invention will become easier to understand from the detailed description that follows with reference to the drawings. In the drawings, some implementation methods of the present invention are shown as examples and not restrictive, and identical or corresponding symbols indicate identical or corresponding parts.
1 is a configuration diagram of a board card according to an embodiment of the present invention.
Figure 2 is a configuration diagram of an integrated circuit device according to an embodiment of the present invention.
Figure 3 is a schematic diagram showing the internal structure of a computing device according to an embodiment of the present invention.
Figure 4 is a schematic diagram showing the internal structure of a processor core according to an embodiment of the present invention.
Figure 5 is a schematic diagram showing the layout of a package structure according to an embodiment of the present invention.
Figure 6 is a schematic diagram showing the layout of another package structure according to an embodiment of the present invention.
Figure 7 is a schematic diagram showing the layout of another package structure according to an embodiment of the present invention.
Figure 8 is a schematic diagram showing the layout of another package structure according to an embodiment of the present invention.
Figure 9 illustrates the limits for each spacing associated with a capacitor in an embodiment of the present invention.
Figure 10 is a flowchart of laying out an integrated circuit on a die according to another embodiment of the present invention.
Figure 11 is a cross-sectional view showing the packaging process structure of CoW according to an embodiment of the present invention.
Figure 12 is a cross-sectional view showing the packaging process structure of CoWoS according to an embodiment of the present invention.
Figure 13 is a flowchart of manufacturing a CoWoS structure on a die according to another embodiment of the present invention.
Figure 14A is a cross-sectional view of the package structure corresponding to each step in another embodiment of the present invention.
Figure 14B is a cross-sectional view of the package structure corresponding to each step in another embodiment of the present invention.
Figure 15A is a cross-sectional view of the package structure corresponding to each step in another embodiment of the present invention.
Figure 15B is a cross-sectional view of the package structure corresponding to each step in another embodiment of the present invention.
Figure 15C is a cross-sectional view of the package structure corresponding to each step in another embodiment of the present invention.

Hereinafter, the technical solutions according to the embodiments of the present invention will be clearly and completely described with reference to the drawings of the embodiments of the present invention. It is clear that the embodiments described below are only some embodiments of the present invention and are not all embodiments. All other embodiments obtained by a person skilled in the art based on the embodiments of the present invention without creative efforts fall within the protection scope of the present invention.

Terms such as “first,” “second,” “third,” and “fourth” in the claims, specification, and accompanying drawings of the present invention are used to distinguish different objects and to describe a specific order. You must understand that it is not intended to be used. Additionally, the terms "comprise" and "have" used in the specification, claims, and accompanying drawings of the present invention are used to indicate the presence of the described feature, whole, step, operation, element, and/or component. However, it does not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and/or sets thereof.

Additionally, it should be understood that the terminology used in the specification of the present invention is for the purpose of describing specific embodiments and is not intended to limit the present invention. As used in the specification and claims of the present invention, the singular forms “a”, “an” and “the” are understood to include the plural forms, unless the context clearly dictates otherwise. It is further to be understood that the term “and/or” as used in the specification and claims of the present invention refers to and includes one or more of the listed lists and all possible combinations.

As used in the specification and claims, the term “if” shall be construed as “when…” or “if…” or “in response to determination” or “in response to detection,” depending on the context. It can be.

Hereinafter, a specific implementation method of the present invention will be described in detail with reference to the attached drawings.

Currently, semiconductor processing begins with a complete wafer, which is a circular thin sheet made of pure silicon and is generally divided into various sizes such as 6 inches, 8 inches, and 12 inches. The wafer is divided into individual small blocks, and these small blocks are called dies. Chips are mounted on each die and wires are arranged well to implement specific electrical functions. The die is packaged as a single particle, and the purpose of packaging is to mount, fix, seal, and protect the chip and improve heat transfer performance. At the same time, the contacts of the chip are connected to the leads of the package housing using conductors to complete one chip package structure.

One embodiment of the present invention is a CoWoS package structure formed on a die, in this embodiment the chip includes memory and a system-on-chip, but the present invention is not limited to packaging only the devices described above.

Memory is used to temporarily store computational data required for the system-on-chip and data for exchange with external storage devices. In this embodiment, the memory may be high bandwidth memory (HBM), which is a high-performance DRAM manufactured by a 3D stack process and is used for application scenarios requiring high memory bandwidth, such as graphics processors and networks. It can be applied to switching and forwarding devices (e.g. routers, exchangers), etc.

System-on-a-Chip (SoC) is a technology that integrates a complete system on a single chip and packages all or part of the necessary electronic circuitry. In this embodiment, the system-on-chip is mounted on a board card. 1 is a schematic diagram showing the structure of a board card 10 according to an embodiment of the present invention. As shown in Figure 1, the board card 10 includes an integrated processing unit 101, which is an artificial intelligence operation unit and supports each type of deep learning and machine learning algorithms, such as computer vision, voice, natural language processing, It is configured to meet the needs of smart processing in complex scenarios in fields such as data discovery. In particular, deep learning technology is widely applied in the cloud smart field, and cloud smart applications have distinct characteristics that require a large amount of data input and high platform storage and calculation capabilities. The board card 10 of this embodiment is applied to cloud smart applications and has massive off-chip storage, on-chip storage, and large computational capabilities.

The integrated processing device 101 is connected to the peripheral device 103 through an external interface device 102. The peripheral device 103 is, for example, a server, computer, camera, display device, mouse, keyboard, LAN card, or WiFi interface. Data to be processed is transmitted from the peripheral device 103 to the integrated processing device 101 through the external interface device 102. The calculation result of the integrated processing unit 101 is transmitted back to the peripheral device 103 via the external interface device 102. According to different application scenarios, the external interface device 102 may include other interface types, for example, PCIe interface, etc.

The board card 10 further includes an external storage device 104 that stores data. The external storage device 104 includes one or more storage units 105. The external storage device 104 is connected to the control device 106 and the integrated processing device 101 through a bus to transmit data. The control device 106 in the board card 10 is configured to control the state of the integrated processing unit 101. Accordingly, in one application scenario, the control device 106 may include a microcontroller unit (Micro Controller Unit, MCU).

Figure 2 is a schematic diagram of the integrated processing device 101 of this embodiment. As shown in FIG. 2, the integrated processing unit 101 includes a computing device 201, an interface device 202, a processing device 203, and a DRAM 204. In one application scenario, computing device 201, interface device 202, and processing device 203 are integrated into the system-on-a-chip described above. In another application scenario, the computing device 201 itself corresponds to the system-on-chip described above.

The computing device 201 is configured to perform user-specified operations and is mainly implemented as a single-core smart processor or multi-core smart processor to perform deep learning or machine learning calculations. The computing device 201 interacts with the processing device 203 through the interface device 202 to jointly perform user-specified operations.

Interface device 202 is configured to transfer data and control instructions between computing device 201 and processing device 203. For example, computing device 201 obtains input data from processing device 203 through interface device 202 and writes it to a storage device on-chip of computing device 201. Furthermore, the computing device 201 obtains control commands from the processing unit 203 through the interface device 202 and records them in the control cache of the computing device 201 on-chip. Alternatively or alternatively, interface device 202 may also read data in storage of computing device 201 and transmit it to processing device 203.

Processing device 203 is a general-purpose processing device that performs, but is not limited to, data transport and basic control of starting and/or stopping computing device 201. Depending on the implementation, processing unit 203 may be one or more types of processors: a central processing unit, a graphics processor, or other general-purpose and/or dedicated processors. These processors may be digital signal processors (DSPs), application specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs) or other programmable logic devices, individual gates or transistors. It can be a logical device, and individual hardware components, the number of which can be determined according to actual needs. As described above, the computing device 201 of the present invention can be considered to have a single core structure or a homogeneous multi-core structure. However, when considering the computing device 201 and the processing device 203 as integrated, both are considered to form a heterogeneous multi-core structure.

DRAM 204 is the high-bandwidth memory, configured to store data to be processed, typically 16G or larger in size, and used to store data for computing device 201 and/or processing device 203. do.

Figure 3 is a schematic diagram showing the internal structure of the computing device 201. Computing device 201 is configured to process input data, such as computer vision, speech, natural language, and data mining. The computing device 201 in the figure has a multi-core layered structure and includes an external memory controller 301, a peripheral communication module 302, an on-chip interconnect module 303, a synchronization module 304, and a plurality of clusters 305. Includes.

There may be a plurality of external memory controllers 301, but two are shown as examples in the drawing. It accesses an external storage device, such as DRAM 204 of FIG. 2, in response to an access request sent by the processor core to read data from or write data from off-chip. The peripheral communication module 302 receives a control signal transmitted from the processing device 203 through the interface device 202 and then operates the computing device 201 to perform the task. The on-chip interconnect module 303 is configured to connect the external memory controller 301, the peripheral communication module 302, and the plurality of clusters 305 to transmit data and control signals between the respective modules. The synchronization module 304 is a global barrier controller (GBC) that adjusts the work progress of each cluster to ensure information synchronization. The plurality of clusters 305 are the core components of the computing device 201, and 4 clusters are shown as examples in the drawing. However, with the development of hardware, the computing device 201 of the present invention can be configured with 8, 16, or 64 clusters. It may even contain more clusters 305. Cluster 305 is configured to efficiently perform deep learning algorithms.

Each cluster 305 includes a plurality of processor cores (IPU cores) 306 and one memory core (MEM core) 307.

Although four processor cores 306 are illustrated in the drawing, the present invention is not limited to the quantity of processor cores 306. Its internal configuration is as shown in Figure 4, and each processor core 306 includes three modules: a control module 41, a calculation module 42, and a storage module 43.

The control module 41 is configured to perform the task of deep learning by coordinating and controlling the operations of the operation module 42 and the storage module 43, and the instruction fetch unit (IFU) 411 and instruction decode Includes an instruction decode unit (IDU) 412. The instruction fetch unit 411 is configured to receive an instruction sent from the processing unit 203, and the instruction decode unit 412 decodes the obtained instruction and then sends the decoding result to the operation module 42 and the storage module as control information. Send to (43).

The calculation module 42 includes a vector calculation unit 421 and a matrix calculation unit 422. The vector operation unit 421 is configured to perform vector operations to support complex operations such as vector multiplication, addition, and non-linear transformation, and the matrix operation unit 422 performs core calculations of deep learning operations, matrix multiplication, and convolution ( convolutional).

The storage module 43 is used to store or transport related data, including a neuron RAM (NRAM) 431, a weight RAM (WRAM) 432, and input/output direct memory access (IODMA). ) module 433, and a move direct memory access (MVDMA) module 434. NRAM 431 is configured to store input and output data and intermediate results required for calculations of the processor core 306, WRAM 432 is configured to store weights of the deep learning network, and IODMA 433 is configured to store the broadcast bus ( 309) is configured to control the fetch of NRAM (431)/WRAM (432) and DRAM (204), and MVDMA (434) controls fetch of NRAM (431)/WRAM (432) and SRAM (308) It is configured to control.

Returning to Figure 3, memory core 307 is primarily used for storage and communication, storing shared data or intermediate results between processor cores 306, communication between cluster 305 and DRAM 204, Communication between clusters 305, communication between processor cores 306, etc. are performed. In another embodiment, the memory core 307 has scalar operation capability and performs scalar operations.

The memory core 307 includes a static random access memory (SRAM) 308, a broadcast bus 309, a cluster direct memory access (CDMA) module 310, and a global direct memory access (GDMA) module 311. . The SRAM 308 plays the role of a high-performance data relay station, and data multiplexed between different processor cores 306 within the same cluster 305 is obtained from the DRAM 204 through the processor core 306 itself. It is relayed between the processor cores 306 via the SRAM 308 without any need. The memory core 307 only needs to distribute the multiplexed data from the SRAM 308 to a plurality of processor cores 306. This improves communication efficiency between cores and significantly reduces the number of on-chip and off-chip input/output accessors. You can.

The broadcast bus 309, CDMA 310, and GDMA 311 perform communication between processor cores 306, communication between clusters 305, and data transmission between clusters 305 and DRAM 204, respectively. It is composed. This will be described in detail below.

The broadcast bus 309 is configured to perform high-speed communication between each processor core 306 of the cluster 305, and the communication methods between cores supported by the broadcast bus 309 in this embodiment are unicast and multicast. and broadcast. Unicast refers to data transmission point-to-point (i.e., from a single processor core to a single processor core), while multicast refers to communication that transmits a batch of data from SRAM 308 to a specific number of processor cores 306. Broadcast refers to a communication method that transmits a set of data from the SRAM 308 to all processor cores 306, and is a special case of multicast.

CDMA 310 is configured to control fetching of SRAM 308 between different clusters 305 of one computing device 201 . GDMA 311 is configured to cooperate with external memory controller 301 to control fetches from SRAM 308 to DRAM 204 in cluster 305 or to read data from DRAM 204 to SRAM 308. .

Figure 5 is a layout schematic diagram of the package structure according to this embodiment. The layout of this package structure is located in a molding compound area 50 of the die, which includes a system area 51 and two memory areas 52. Here, the system area 51 is located in the center of the molding compound area 50, and the memory area 52 is located on both sides of the system area 51. The chip of the package structure includes a system-on-chip 501 and a plurality of memories 502, where the system-on-chip 501 is the above-described system-on-chip and includes only the computing device 201, or the computing device 201, It may also include only the interface device 202 and the processing device 203. The system-on-chip 501 is installed in the system area 51, and the memory 502 is DRAM 204. There are a total of six in this embodiment and are uniformly installed in the memory area 52, and the memory 502 is DRAM 204. Three memories 502 are installed on each side.

Due to the size of the system-on-chip 501 and the memory 502, a residual area is created when laying out these chips, and the residual area is located outside the system area 51 and the memory area 52 in the molding compound area 50. It refers to empty areas, and in this embodiment, the capacitors required for the CoWoS structure are placed in these remaining areas. As shown in FIG. 5, residual areas are formed at the top and bottom of the system area 51 due to this chip layout, so a capacitor can be placed in the remaining areas. Specifically, the chip of the package structure further includes a plurality of capacitors 503, and the molding compound region 50 includes two capacitor regions 53, wherein the capacitor region 53 is a molding compound region 50. They are located at the top and bottom of the system area 51, which is the remaining area of . The capacitors 503 are uniformly distributed within the capacitor area 53 to sufficiently utilize the area of the molding compound area 50.

If the capacitor area 53 cannot accommodate all of the capacitors required for the CoWoS structure, the remaining capacitors may be laid out outside the molding compound area 50 in this embodiment. As shown in Figure 5, the die further includes non-moulding compound regions 54 located atop and below the molding compound region 50 to accommodate more capacitors. This embodiment is not limited to the location of the non-molding compound area 54, but almost all of the surrounding area of the molding compound area 50 can be used as the non-molding compound area 54, and its size depends on the quantity and size of the capacitor. It is decided. In this embodiment, the capacitor is first installed in the remaining area within the molding compound area 50, and if space is insufficient, the capacitor is installed in the non-molding compound area 54.

This embodiment is not limited to the specifications of the capacitor, and according to the specific requirements of the chip, any suitable capacitor available on the market, for example, the capacitor of GRM2165C1H333GA01 produced by Murata Company, can be used, but is not limited to this.

In addition to the chip layout method of FIG. 5, FIG. 6 is a schematic diagram of the layout of another package structure according to this embodiment. The difference from the layout method described above is that the remaining areas are located at the four corners of the molding compound area 50, and the capacitors are placed within these remaining areas. Specifically, the molding compound region 50 includes four capacitor regions 53 located at the four corners of the molding compound region 50, and the capacitors 503 sufficiently utilize the area of the molding compound region 50. are uniformly distributed within the capacitor area 53 so as to do so.

Figure 7 is a layout schematic diagram of another package structure in this embodiment. The difference from the layout method described above is that four memories 502 are installed at the four corners of the molding compound area 50, and the remaining area is between the two memory areas 52 on both sides of the system area 51. It is located. Accordingly, the molding compound area 50 includes two capacitor areas 53 each located between the two memory areas 52 on both sides of the system area 51, and these capacitors 503 are located in the molding compound area 50. It is uniformly distributed within the capacitor area 53 to sufficiently utilize the area.

Figure 8 is a layout schematic diagram of another package structure according to this embodiment. What is different from the layout method described above is that two system-on-chips 501 are installed in the system area 51, and what is common with the layout method of FIG. 5 is that residual areas are formed at the top and bottom of the system area 51. Thus, the capacitor 503 is placed within these remaining areas.

Various chip layout methods shown in FIGS. 5 to 8 illustrate locations where residual areas are generated, that is, locations of capacitor areas. In summary, the capacitor area is located in the remaining area of the molding compound area 50, between the system area 51 and the die edge, between the system area 51 and the memory area 52, and between the memory area 52 and It may be between the die borders, between the memory area 52 and the memory area 52 .

Since the semiconductor manufacturing process has physical limitations, the gap between the chip and the capacitor is limited to ensure that each element operates normally, thereby preventing electrical interference. Figure 9 shows the limits for each spacing associated with the capacitor in this embodiment. The distance d1 between the capacitor 503 and the system area 51 must be greater than 0.5 mm, and the distance d2 between the capacitor 503 and the memory area 52 must be greater than 1 mm, and the distance between the capacitor 503 and the die The distance d3 between the edges (the border 901 of the molding compound area 50) must be greater than 0.5 mm, and the distance d4 between the capacitors 503 must be greater than 0.5 mm.

Although the non-molding compound area 54 is not shown in the chip layout schemes of FIGS. 6 to 8, this does not mean that the non-molding compound area 54 is not needed to accommodate more capacitors. Those skilled in the art can easily understand from the description of FIG. 5 that a non-molding compound area 54 can be installed around the molding compound area 50 to accommodate a capacitor regardless of the chip layout method. and will not be explained repeatedly here.

In addition to the system-on-chip 501 and the memory 502, the chip of the present invention can be used in various integrated circuits, such as resistors, other capacitor types (e.g. MIMCAP), inductors, diodes, metal-oxide- Metal-oxide-semiconductor field effect transistors (MOSFET), complementary MOS (CMOS) transistors, bipolar junction transistors (BJT), and laterally diffused metal-oxide semiconductors (LDMOS). ) may further include a variety of passive microelectronic devices and active microelectronic devices, such as transistors, high-power MOS transistors, or other types of transistors.

In this embodiment, the die area can be reduced by using the remaining area other than the system area and memory area as a capacitor area to place the necessary capacitors on the chip. The reduction in die volume under the condition that the wafer size does not change means that more dies can be accommodated on a single wafer, which has the technological effect of lowering manufacturing costs.

Another embodiment of the present invention is a method of laying out an integrated circuit on a die, the flowchart of which is shown in FIG. 10.

Step 1001: Mount the system-on-chip on the system area chip on the die. As described above, the chip layout is located in the molding compound area of the die including the system area and the memory area, and the chip in the package structure includes the system-on-chip and memory, and the present embodiment uses chip mounting technology to form a system-on-chip. Install in the system area.

One exemplary chip mounting technique is controlled collapse chip connection (C4). Collapse-controlled chip connection involves applying high-temperature solder, flux, or solder paste to tin-plated electrodes on a board or transferring it to solder balls on a chip, then mounting the chip on the board, and reflow-connecting it through heating during mounting. Alternatively, batch reflow in a standard reflow oven.

Step 1002: Mount the memory on the memory area chip on the die. There can be multiple memories, the number of which is determined by actual demand. The memory of this embodiment may be a high-bandwidth memory, and the high-bandwidth memory is a structure in which several layers of DRAM are stacked as one and mounted in the memory area. High-bandwidth memory implements high-bit width and low-frequency video memory, so on the basis of providing a large video memory bit width, excessively high frequency is not required, and under the same 4GB capacity, high-bandwidth memory can provide video memory bits. The width is 4096 bits, which is several times higher than GDDR5. The advent of high-bandwidth memory has expanded the layout of chips from 2D to 3D, reducing die area.

Step 1003: A plurality of capacitors are mounted on a chip in the capacitor area on the die. As previously described, the capacitor area in this embodiment is a remaining area other than the system area and memory area. In this embodiment, the die area is reduced by sufficiently utilizing the area of the molding compound area 50 by disposing the capacitor required for the CoWoS structure in the remaining area. The capacitor area of this embodiment may be located between the system area and the die border, between the system area and the memory area, between the memory area and the die border, and between the memory area and the memory area. Limitations on the spacing related to the capacitor are as shown in FIG. 9 and will not be described again.

Figure 11 is a cross-sectional view showing the packaging process structure of CoW according to the above embodiment. The structure first forms a plurality of silicon through holes (through silicon via, TSV) 1102 on the die 1101. Here, silicon through-hole technology is a high-density package technology that replaces wire bonding technology, and realizes vertical electrical connection of silicon through-holes by filling them with conductive materials such as copper, tungsten, and polysilicon. This technology reduces the connection length through vertical connection and reduces signal delay and unnecessary capacitance/inductance, enabling low-power, high-speed communication and increased bandwidth between chips, while also enabling miniaturization of device integration. Next, a micro bump 1103 is formed using a micro bump manufacturing technology (microbump) to bond the chip 1104, capacitor 1105, and die 1101 into one. The chip 1104 in the drawing exemplarily includes the system-on-chip and a plurality of memories.

CoWoS is manufactured by reconnecting the substrate to the CoW process in Figure 11. Figure 12 shows the packaging process structure of CoWoS. First, fill the chip 1104 with underfill, then form a solder ball 1201 and bond it to the substrate (e.g. printed circuit board) 1202, and finally add the package 1203. Complete it.

An embodiment of the present invention supplies power to the chip by forming a plurality of capacitors on the die 1101, and the larger the generated capacitance value, the more stable the power supply. Deep learning chips that consume a lot of electricity urgently need high capacitance values. The present invention proposes to provide a high capacitance value by installing a capacitor in the remaining area in the CoWoS process.

Another embodiment of the present invention is a method of manufacturing a CoWoS structure on a die, in which the CoW structure shown in FIG. 11 is first manufactured, and then the CoWoS structure shown in FIG. 12 is manufactured. This embodiment This method is as shown in Figure 13, and Figures 14 and 15 are cross-sectional views of the package structure corresponding to each step of this embodiment.

First, in this embodiment, a plurality of redistribution layers are formed on the first side of the die using silicon through-holes. Specifically, in step 1301, a plurality of silicon through-hole layers are formed by mask etching the first side of the die 1401 (i.e., die 1101), and Figure 14A shows the first silicon through-hole layer 1402 and the first silicon through-hole layer. 2The silicon through-hole layer 1403 is shown as an example. In this embodiment, if the thickness of die 1401 is 775 μm, the depth of the silicon through-hole layer is 107 μm. In step 1302, water vapor is generated on the first surface through a thermal wet oxidation process, and then the water vapor reacts with the silicon material of the die to generate a first dielectric layer 1404 whose component is silicon heteronitride on the first surface. After performing these steps, structure 141 is formed on the first side of die 1401.

In step 1303, the conductive layer 1409 is electroplated. The material of the conductive layer 1409 is copper. After performing these steps, structure 142 is formed on the first side of die 1401.

In step 1304, a plurality of redistribution layers 1405 are deposited. First, the surface of the first side is polished flat using CMP (chemical mechanical polishing) to remove the conductive layer 1409 on the first side surface, leaving only the silicon through-hole layer in the conductive layer 1409. The function of the redistribution layer 1405 is to electrically connect the silicon through-hole layer and the chip contact. According to the actual demand of the chip contact connection, this redistribution layer 1405 is specially divided to ensure that the contact is accurately electrically connected to the appropriate silicon through-hole layer. Make sure it is connected. FIG. 14A exemplarily shows a rewiring layer 1405 that is rewired into two layers with a dielectric deposited between them. After performing these steps, structure 143 is formed on the first side of die 1401.

At step 1305, a second dielectric layer 1406 is deposited. The upper part of the outlet of each silicon through-hole layer is blocked through the mask layout so that the redistribution layer 1405 on the upper part of the outlet of each silicon through-hole layer is exposed, but is not blocked by the second dielectric layer 1406. After performing these steps, structure 144 is formed on the first side of die 1401.

In step 1306, a plurality of first wafer bumps are formed on the plurality of redistribution layers 1405. Specifically, a first wafer bump is formed on the top of each silicon through-hole layer using the C4 process so that the first wafer bump is electrically connected to the silicon through-hole layer through the redistribution layer 1405. After performing these steps, structure 145 is formed on the first side of die 1401. The drawing illustrates two first wafer bumps, namely the first wafer bump 1407 and the first wafer bump 1408. Here, the first wafer bump 1407 is electrically connected to the first silicon through-hole layer 1402 through the redistribution layer 1405, and the first wafer bump 1408 penetrates the second silicon through the redistribution layer 1405. It is electrically connected to the hole layer 1403. The distance (D1) between the two first wafer bumps is 60 μm, and the center distance (D2) is 130 μm, 150 μm, or 180 μm.

Next, step 1307 is performed to bond the plurality of first wafer bumps, system-on-chip, and memory. After performing these steps, the structure 151 shown in Figure 15A is formed on the first side of die 1401. Here, chip 1501 includes the system-on-chip and memory.

In step 1308, underfill is filled in the system area and memory area. The material of the underfill can reduce the effects of moisture protection, thermal shock and various mechanical shocks, and its role is to provide higher reliability and a longer life cycle. After performing these steps, the structure 152 shown in Figure 15A is formed on the first side of die 1401, where underfill 1502 protects the contacts of chip 1501 and the first wafer bumps.

In step 1309, a plurality of first wafer bumps and a capacitor are bonded. After performing these steps, the structure 153 shown in Figure 15A is formed on the first side of die 1401. The structure 153 exemplarily represents a state in which two capacitors 1503 are bonded to a plurality of first wafer bumps, and these capacitors 1503 are installed in the capacitor area, that is, in the remaining area other than the system area and memory area.

In step 1310, a CoW structure is formed by molding the system-on-chip, memory, and a plurality of capacitors. In other words, the chip 1501 and the capacitor 1503 are packaged, forming the structure 154 shown in FIG. 15B on the first side of the die 1401. Here, the package plastic 1504 covers the chip 1501 and the capacitor 1503 to mount, fix, seal, and protect the chip and improve heat transfer performance. Through this, the CoW structure of Figure 11 is implemented.

In step 1311, the CoW structure is glass bonded. First, the entire CoW structure is flipped so that the first side faces downward, and the package plastic 1504 and the glass 1505 are bonded by mechanical or chemical methods to form a laminate material. A commonly available bonding method is anodic bonding. There are anodic bonding, adhesive intermediate sandwich method, and silicon (or glass) surface coating bonding method. After performing these steps, structure 155 shown in Figure 15B is formed on the first side of die 1401.

In step 1312, the die is polished so that the other surface of the silicon through hole is aligned with the second surface of the die. As shown in structure 156 in FIG. 15B, this embodiment polishes the second side surface of die 1401 flat through chemical mechanical polishing so that all silicon through-hole 1506 surfaces are flush with the second side surface. It is positioned neatly and the surface of the silicon through hole 1506 is exposed to the second side.

In step 1313, a plurality of second wafer bumps are formed on the second side and connected to the other side of the silicon through hole. As shown in the structure 157 of FIG. 15C, a second wafer bump 1507 is formed in the opening portion of each silicon through hole 1506 on the second side through the C4 process.

In step 1314, a second wafer bump is welded to the substrate. As shown in the structure 158 of FIG. 15C, the glass 1505 is first removed, the die 1401 is flipped so that the package plastic 1504 is facing upward, and the package plastic 1504 is first polished to form the chip 1501. ) The surface is exposed to the air, which is advantageous for heat dissipation. Then, the second wafer bump 1507 is welded to the substrate 1508 again. Here, the spacing between the two second wafer bumps 1507 is 60 μm, and the center distance is 130 μm, 150 μm, or 180 μm. This completes the CoWoS package structure of Figure 12.

If the capacitor area 53 cannot accommodate all of the capacitors required for the CoWoS structure, the remaining capacitors may be placed outside the molding compound area 50 in this embodiment. In this case, this embodiment then welds the capacitor to the substrate through step 1315. As shown in structure 159 of FIG. 15, a separate capacitor 1509 is welded to substrate 1508. The capacitor 1503 is combined with the capacitor 1509 to improve the overall capacitance value and significantly increase power supply stability.

The present invention reduces the area of the die by using the remaining area of the molding compound area as a capacitor area to place the necessary capacitors on the chip. The reduction in die volume under the condition that the wafer size does not change means that more dies can be accommodated on a single wafer, which has the technological effect of lowering manufacturing costs.

The foregoing will be better understood through the provisions below.

Clause A1: A method of laying out an integrated circuit on a die in a package structure, comprising: mounting a system-on-chip on a system area chip on the die; mounting memory on a memory area chip on the die; and mounting a plurality of capacitors on a capacitor area chip on the die, where the capacitor area is a remaining area other than the system area and the memory area.

Clause A2: The method according to Clause A1, wherein the capacitor region is located between the system region and the die edge.

Clause A3: The method according to clause A1, wherein the capacitor area is located between the system area and the memory area.

Clause A4: The method according to Clause A1, wherein the capacitor area is located between the memory area and the die border.

Clause A5: The method according to clause A1, wherein the capacitor area is located between the plurality of memory areas.

Clause A6: The method according to clause A1, wherein the distance between the plurality of capacitors and the system area is greater than 0.5 mm.

Clause A7: The method according to Clause A1, wherein the distance between the plurality of capacitors and the memory area is greater than 1 mm.

Clause A8: The method according to clause A1, wherein the distance between the plurality of capacitors and the die edge is greater than 0.5 mm.

Clause A9: The method according to clause A1, wherein the distance between the plurality of capacitors is greater than 0.5 mm.

Clause A10: The method according to any one of clauses A1 to clause A9, comprising: forming a plurality of redistribution layers on a first side of the die using silicon through-holes; forming a plurality of first wafer bumps on the plurality of redistribution layers; and bonding the plurality of first wafer bumps, the system-on-chip, the memory, and the plurality of capacitors.

Clause A11: The method according to clause A10, further comprising filling the system area and the memory area with underfill.

Clause A12: The method according to clause A11, further comprising molding the system-on-chip, the memory and the plurality of capacitors to form a CoW structure.

Clause A13: The method according to Clause A12, comprising the steps of glass bonding the CoW structure; and polishing the die so that the other surface of the silicon through hole and the second surface of the die are aligned.

Clause A14: The method according to clause A13, comprising forming a plurality of second wafer bumps on the second side and connecting them to the other side of the silicon through hole; and welding the plurality of second wafer bumps to the substrate.

Clause A15: The method according to clause A14, wherein forming the plurality of first wafer bumps and forming the plurality of second wafer bumps use a C4 process.

Clause A16: The method according to Clause A14, wherein the spacing between the plurality of first wafer bumps and the plurality of second wafer bumps is 60 μm.

Clause A17: The method according to Clause A10, wherein the distance between the centers of the plurality of first wafer bumps and the plurality of second wafer bumps is 150 μm.

Clause A18: The method according to Clause A1, wherein the memory is High Bandwidth Memory (HBM).

Clause A19: The method according to clause A1, wherein the package structure is a CoWoS package structure.

Clause A20: A package structure, the package structure comprising: a system-on-chip installed in a system area on a die; a memory installed in a memory area on the die; and a plurality of capacitors installed in a capacitor area on the die, where the capacitor area is a remaining area other than the system area and the memory area.

Clause A21: The package structure according to Clause A20, wherein the capacitor region is located between the system region and the die edge.

Clause A22: The package structure according to clause A20, wherein the capacitor area is located between the system area and the memory area.

Clause A23: The package structure according to Clause A20, wherein the capacitor area is located between the memory area and the die edge.

Clause A24: The package structure according to clause A20, wherein the capacitor area is located between the plurality of memory areas.

Clause A25: The package structure according to any one of clauses A20 to A24, wherein the distance between the plurality of capacitors and the system area is greater than 0.5 mm.

Clause A26: The package structure according to any one of clauses A20 to A24, wherein the distance between the plurality of capacitors and the memory area is greater than 1 mm.

Clause A27: The package structure according to any one of clauses A20 to clause A24, wherein the distance between the plurality of capacitors and the die edge is greater than 0.5 mm.

Clause A28: The package structure according to any one of clauses A20 to A24, wherein the distance between the plurality of capacitors is greater than 0.5 mm.

Clause A29: The package structure according to Clause A1, wherein the memory is a high-bandwidth memory.

Clause A30: The package structure according to clause A1, wherein the package structure is a CoWoS package structure.

Clause A31: An integrated circuit device comprising a package structure according to any one of clauses A20 to A30.

Clause A32: In a board card, it includes an integrated circuit device according to clause A31.

The embodiments of the present invention have been described in detail above, and the principles and implementation methods of the present invention have been described in detail by applying specific embodiments. However, the description of the embodiments will be used to understand the method and core idea of the present invention. Those skilled in the art may change the specific implementation method and scope of application according to the spirit of the present invention, and as described above, the contents of this specification should not be construed as limiting the present invention. .

Claims (32)

As a method of laying out a package structure,
mounting the system-on-chip into a system area chip on a die;
mounting memory on a memory area chip on the die; and
Comprising: mounting a plurality of capacitors, which are separate elements from the system-on-chip and the memory, on the capacitor area chip on the die and for supplying power to the package structure,
Here, the capacitor area is a remaining area other than the system area and the memory area,
A method of laying out an integrated circuit on a die of a package structure, wherein the plurality of capacitors are electrically connected to a redistribution layer formed on a first side of the die. In claim 1,
the capacitor area is located between the system area and the die edge; or
the capacitor area is located between the system area and the memory area; or
the capacitor area is located between the memory area and the die edge; or
Wherein the capacitor area is located between the plurality of memory areas. In claim 1,
The distance between the plurality of capacitors and the system area is greater than 0.5 mm; or
The distance between a plurality of capacitors and the memory area is greater than 1 mm; or
The distance between the plurality of capacitors and the die edge is greater than 0.5 mm; or
A method wherein the distance between the plurality of capacitors is greater than 0.5 mm. The method according to any one of claims 1 to 3,
forming a plurality of redistribution layers on the first side of the die using silicon through-holes;
forming a plurality of first wafer bumps on the plurality of redistribution layers; and
The method further comprising bonding the plurality of first wafer bumps to the system-on-chip, the memory, and the plurality of capacitors. In claim 4,
The method further comprising filling the system area and the memory area with underfill. In claim 5,
The method further comprising forming a CoW (Chip on Wafer) structure by molding the system-on-chip, the memory, and the plurality of capacitors. In claim 6,
glass bonding the CoW structure; and
The method further comprising polishing the die so that the other surface of the silicon through hole and the second surface of the die are aligned. In claim 7,
forming a plurality of second wafer bumps on the second side and connecting them to the other side of the silicon through hole; and
The method further comprising welding the plurality of second wafer bumps to a substrate. In claim 8,
The method of forming the plurality of first wafer bumps and forming the plurality of second wafer bumps using a C4 process. In claim 8,
A method wherein the distance between the plurality of first wafer bumps and the plurality of second wafer bumps is 60 μm. In claim 4,
The method wherein the distance between the centers of the plurality of first wafer bumps and the plurality of second wafer bumps is 150 μm. Regarding package structure,
System-on-chip installed in the system area above the die;
a memory installed in a memory area on the die; and
It is installed in the capacitor area on the die, is a separate element from the system on chip and the memory, and includes a plurality of capacitors for supplying power to the package structure,
Here, the capacitor area is a remaining area other than the system area and the memory area,
A package structure wherein the plurality of capacitors are electrically connected to a redistribution layer formed on a first side of the die. In claim 12,
the capacitor area is located between the system area and the die edge; or
the capacitor area is located between the system area and the memory area; or
the capacitor area is located between the memory area and the die edge; or
A package structure wherein the capacitor area is located between the plurality of memory areas. The method of either claim 12 or claim 13,
The distance between the plurality of capacitors and the system area is greater than 0.5 mm; or
The distance between the plurality of capacitors and the memory area is greater than 1 mm; or
The distance between the plurality of capacitors and the die edge is greater than 0.5 mm; or
A package structure wherein the distance between the plurality of capacitors is greater than 0.5mm. An integrated circuit device comprising a package structure according to claim 12.


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