JP2009111345A - 高κキャップ阻止誘電体‐バンドギャップ操作SONOS及びMONOS - Google Patents
高κキャップ阻止誘電体‐バンドギャップ操作SONOS及びMONOS Download PDFInfo
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- 230000000903 blocking effect Effects 0.000 title claims abstract description 108
- LPQOADBMXVRBNX-UHFFFAOYSA-N ac1ldcw0 Chemical compound Cl.C1CN(C)CCN1C1=C(F)C=C2C(=O)C(C(O)=O)=CN3CCSC1=C32 LPQOADBMXVRBNX-UHFFFAOYSA-N 0.000 title description 32
- 239000010410 layer Substances 0.000 claims abstract description 454
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 132
- 230000015654 memory Effects 0.000 claims abstract description 116
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 54
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 54
- 239000000463 material Substances 0.000 claims abstract description 50
- 230000005641 tunneling Effects 0.000 claims abstract description 36
- 239000002356 single layer Substances 0.000 claims abstract description 5
- 230000005684 electric field Effects 0.000 claims description 49
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 48
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 25
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 25
- 238000000034 method Methods 0.000 claims description 24
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 24
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 18
- 229910052710 silicon Inorganic materials 0.000 claims description 18
- 239000010703 silicon Substances 0.000 claims description 18
- 229910052751 metal Inorganic materials 0.000 claims description 17
- 239000002184 metal Substances 0.000 claims description 17
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 17
- 229920005591 polysilicon Polymers 0.000 claims description 15
- 239000004065 semiconductor Substances 0.000 claims description 15
- 238000004519 manufacturing process Methods 0.000 claims description 7
- 150000002736 metal compounds Chemical class 0.000 claims description 4
- 230000007423 decrease Effects 0.000 claims description 3
- 230000014759 maintenance of location Effects 0.000 description 41
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 29
- 229910004298 SiO 2 Inorganic materials 0.000 description 25
- 238000002347 injection Methods 0.000 description 22
- 239000007924 injection Substances 0.000 description 22
- 230000004888 barrier function Effects 0.000 description 21
- 230000006870 function Effects 0.000 description 17
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 15
- 238000010586 diagram Methods 0.000 description 14
- 238000005516 engineering process Methods 0.000 description 13
- 229910052782 aluminium Inorganic materials 0.000 description 11
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 10
- 150000004767 nitrides Chemical class 0.000 description 10
- 230000008569 process Effects 0.000 description 10
- 238000007667 floating Methods 0.000 description 9
- 238000012360 testing method Methods 0.000 description 9
- 239000003989 dielectric material Substances 0.000 description 8
- 238000002513 implantation Methods 0.000 description 7
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 6
- 239000002131 composite material Substances 0.000 description 6
- 230000005284 excitation Effects 0.000 description 6
- 229910052718 tin Inorganic materials 0.000 description 6
- 230000008901 benefit Effects 0.000 description 5
- 230000008859 change Effects 0.000 description 5
- 238000002955 isolation Methods 0.000 description 5
- 230000007246 mechanism Effects 0.000 description 5
- 229910052697 platinum Inorganic materials 0.000 description 5
- 238000003860 storage Methods 0.000 description 5
- 230000007547 defect Effects 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 4
- 230000009467 reduction Effects 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 238000000926 separation method Methods 0.000 description 3
- 229910017121 AlSiO Inorganic materials 0.000 description 2
- 229910004129 HfSiO Inorganic materials 0.000 description 2
- 229910021193 La 2 O 3 Inorganic materials 0.000 description 2
- 229910006501 ZrSiO Inorganic materials 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000003780 insertion Methods 0.000 description 2
- 230000037431 insertion Effects 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 239000002243 precursor Substances 0.000 description 2
- 230000004044 response Effects 0.000 description 2
- 230000001629 suppression Effects 0.000 description 2
- 230000001052 transient effect Effects 0.000 description 2
- 229910019899 RuO Inorganic materials 0.000 description 1
- 238000003917 TEM image Methods 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 230000006399 behavior Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 238000004590 computer program Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910052593 corundum Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000005516 deep trap Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- MROCJMGDEKINLD-UHFFFAOYSA-N dichlorosilane Chemical compound Cl[SiH2]Cl MROCJMGDEKINLD-UHFFFAOYSA-N 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000002784 hot electron Substances 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 229910052741 iridium Inorganic materials 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000002105 nanoparticle Substances 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000004151 rapid thermal annealing Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- 238000003949 trap density measurement Methods 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 238000009279 wet oxidation reaction Methods 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
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- G—PHYSICS
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Abstract
【解決手段】この阻止誘電体操作電荷トラップメモリーセルは、阻止誘電体によってゲートから分離された電荷トラップ要素を備える。該阻止誘電体は該電荷トラップ要素に接し高品質に作ることができる二酸化シリコン等のバッファ層(第1層)と、該ゲートに接するキャップ層(第2層)とを含む。該キャップ層は第1層より高い誘電率を有し、高κ材料でできているのが好ましい。第2層は相対的に高い伝導帯オフセットも有している。チャネルと該電荷トラップ要素の間にバンドギャップ操作トンネル層が設けられ、該多層阻止誘電体と組合わされて正孔トンネル現象による高速消去動作を可能にする。或いは、単一層からなるトンネル層が使用されてもよい。
【選択図】図1
Description
バッファ層717Aは窒化物から湿式転化されたSiO2、高温酸化物(HTO)、LPCVD‐SiO2等であってもよい。しかし、湿式転化SiO2が好適である。バッファ層717Aの好適な厚みは、0.5〜8nmである。この厚みはキャップ層717Bの厚みのκ1/κ2倍を超えるという関係を満たす。
Claims (22)
- メモリーセルアレイを備える電荷トラップメモリーであって、該アレイ内の各メモリーセルは、
チャネル表面を有するチャネルと、該チャネルに隣接したソース端子及びドレイン端子とを含む半導体と、
ゲートと該チャネル表面の間の誘電体スタックであって、
該ゲートと該チャネル表面のうち一方に接するトンネル誘電体層と、
該トンネル誘電体層上の電荷トラップ誘電体層と、
該電荷トラップ誘電体層上の阻止誘電体層と
を含む誘電体スタックと
を備え、
該阻止誘電体層は、該電荷トラップ誘電体層に接する誘電率κ1の第1層と、該ゲートと該チャネル表面のうち他方に接する第2層とを含み、該第2層は該第1層の誘電率κ1より高い誘電率κ2を有し、該第2層の厚みは、該第1層の厚みのκ2/κ1倍より小さい、
電荷トラップメモリー。 - 前記誘電体スタックは160Å未満の実効酸化膜厚EOTを有し、前記トンネル誘電体層は約40Åと55Åの間の実効酸化膜厚EOTを有し、前記阻止誘電体層は95Å未満の実効酸化膜厚EOTを有する請求項1に記載のメモリー。
- 前記電荷トラップ誘電体層は窒化シリコンからなり、前記阻止誘電体層の前記第1層は酸化シリコンからなる請求項1に記載のメモリー。
- 前記阻止誘電体層の前記第2層は酸化アルミニウムからなる請求項1に記載のメモリー。
- 前記阻止誘電体層は前記電荷トラップ誘電体層と前記ゲートとの間に位置する請求項1に記載のメモリー。
- 前記阻止誘電体層の前記第2層の誘電率κ2は7より大きい請求項1に記載のメモリー。
- 前記阻止誘電体層の前記第1層は酸化シリコン又は酸窒化シリコンからなり、前記電荷トラップ誘電体層は窒化シリコンと酸窒化シリコンのうち少なくとも1つからなる請求項1に記載のメモリー。
- 前記阻止誘電体層の前記第1層は酸化シリコン又は酸窒化シリコンからなり、該阻止誘電体層の前記第2層は酸化アルミニウムからなり、前記電荷トラップ誘電体層は窒化シリコンと酸窒化シリコンのうち少なくとも1つからなる請求項1に記載のメモリー。
- 前記トンネル誘電体層は、複数の材料の組合せからなり、前記チャネル表面の近くにおいてその価電子帯エネルギーレベルが相対的に低く、該チャネル表面から第1距離において価電子帯エネルギーレベルは増加し、該チャネル表面から2nm超の第2距離において価電子帯エネルギーレベルは減少するよう構成された請求項1に記載のメモリー。
- 前記メモリーセルアレイに結合され、リード、プログラム、及び消去動作のために選択されたメモリーセルにバイアス電圧を印加する回路であって、該バイアス電圧は、前記ゲートと前記半導体との間に印加され、14MV/cm未満の大きさの電界を発生させ、前記トンネル誘電体層を通る正孔トンネル現象を引き起こすバイアス電圧を含む回路を備える請求項1に記載のメモリー。
- 前記トンネル誘電体層は前記チャネル表面上に位置し、前記ゲートは金属、金属化合物、n+ドープポリシリコン、又はp+ドープポリシリコンからなる請求項1に記載のメモリー。
- 前記トンネル誘電体層は、前記チャネルに隣接し18Å以下の厚みの第1酸化シリコン層と、該第1酸化シリコン層上の30Å以下の厚みの窒化シリコン層と、該窒化シリコン層上の30Å以下の厚みの酸化シリコン層とを含む請求項1に記載のメモリー。
- 前記トンネル誘電体層は、約3〜5nmの厚みの二酸化シリコン又は酸窒化シリコンの単独層からなる請求項1に記載のメモリー。
- メモリーセルアレイを備える電荷トラップメモリーであって、該アレイ内の各メモリーセルは、
チャネル表面を有するチャネルと、該チャネルに隣接したソース端子及びドレイン端子とを含む半導体と、
該チャネルに隣接し18Å以下の厚みの第1酸化シリコン層と、該第1酸化シリコン層上の30Å以下の厚みの窒化シリコン層と、該窒化シリコン層上の30Å以下の厚みの酸化シリコン層とを含み該チャネル表面上に位置するトンネル誘電体層と、
50Å以上の厚みの窒化シリコンからなり該トンネル誘電体層上に位置する電荷トラップ誘電体層と、
該電荷トラップ誘電体層に接する誘電率κ1の酸化シリコンの第1層と、ゲートに接し該κ1より高い誘電率κ2を有し、該第1層の厚みのκ2/κ1倍より小さい厚みを持つ第2層とを含み該電荷トラップ誘電体層上に位置する阻止誘電体層と、
該阻止誘電体層上の該ゲートと
を備える電荷トラップメモリー。 - 前記阻止誘電体層は95Å未満の実効酸化膜厚EOTを有する請求項14に記載のメモリー。
- チャネル表面を有するチャネル領域と、該チャネル領域に隣接したソース端子及びドレイン端子とを含む半導体を画成することと、
ゲートを画成することと、
該チャネル表面と該ゲートとの間に誘電体スタックを形成することと
を含み、
該誘電体スタックを形成することは、
該チャネル表面と該ゲートのうち一方に接するトンネル誘電体層を形成することと、
該トンネル誘電体層上に電荷トラップ誘電体層を形成することと、
該電荷トラップ誘電体層上に阻止誘電体層を形成することと
を含み、該阻止誘電体層を形成することは、
該電荷トラップ誘電体層に接する第1材料層を形成することと、
該チャネル表面と該ゲートのうち他方に接する第2材料層を形成することと
を含み、該第2材料層は該第1材料層より高い誘電率を有する電荷トラップメモリー製造方法。 - 前記誘電体スタックは160Å未満の実効酸化膜厚EOTを有し、前記トンネル誘電体層は約40Åと55Åの間の実効酸化膜厚EOTを有し、前記阻止誘電体層は95Å未満の実効酸化膜厚EOTを有する請求項16に記載の製造方法。
- 前記トンネル誘電体層は、無視できるほどの電荷トラップ効率を持った複数の材料の組合せからなり、前記チャネル表面の近くにおいてその価電子帯エネルギーレベルが相対的に低く、該チャネル表面から第1オフセットにおいて価電子帯エネルギーレベルは増加し、該チャネル表面から2nm超の第2オフセットにおいて価電子帯エネルギーレベルは減少するよう構成された請求項16に記載の製造方法。
- 前記第2材料層の誘電率は7より大きい請求項16に記載の製造方法。
- 前記ゲートは金属、金属化合物、n+ドープポリシリコン、又はp+ドープポリシリコンからなる請求項16に記載の製造方法。
- 前記トンネル誘電体層は、前記チャネルに隣接し18Å以下の厚みの第1酸化シリコン層と、該第1酸化シリコン層上の30Å以下の厚みの窒化シリコン層と、該窒化シリコン層上の30Å以下の厚みの酸化シリコン層とを含む請求項16に記載の製造方法。
- 前記トンネル誘電体層は、約3〜5nmの厚みの二酸化シリコン又は酸窒化シリコンの単独層からなる請求項16に記載の製造方法。
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US61/019,178 | 2008-01-04 | ||
US12/182,318 | 2008-07-30 | ||
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US7816727B2 (en) | 2010-10-19 |
US20090059676A1 (en) | 2009-03-05 |
KR20090023197A (ko) | 2009-03-04 |
EP2031643A2 (en) | 2009-03-04 |
TW200910607A (en) | 2009-03-01 |
KR101370741B1 (ko) | 2014-03-06 |
CN101383353A (zh) | 2009-03-11 |
EP2031643A3 (en) | 2010-02-17 |
US20110003452A1 (en) | 2011-01-06 |
US8330210B2 (en) | 2012-12-11 |
US8119481B2 (en) | 2012-02-21 |
US20120146126A1 (en) | 2012-06-14 |
KR20120003833A (ko) | 2012-01-11 |
TWI415269B (zh) | 2013-11-11 |
CN101383353B (zh) | 2011-05-25 |
JP5281849B2 (ja) | 2013-09-04 |
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