JP2007504594A - ダイナミック・メモリー、センス増幅器回路、ワード線駆動回路、制御信号ｐｘ駆動回路、信号センス又はリストア方法、及び漏れ電流低減方法 - Google Patents

ダイナミック・メモリー、センス増幅器回路、ワード線駆動回路、制御信号ｐｘ駆動回路、信号センス又はリストア方法、及び漏れ電流低減方法 Download PDF

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JP2007504594A
JP2007504594A JP2006525512A JP2006525512A JP2007504594A JP 2007504594 A JP2007504594 A JP 2007504594A JP 2006525512 A JP2006525512 A JP 2006525512A JP 2006525512 A JP2006525512 A JP 2006525512A JP 2007504594 A JP2007504594 A JP 2007504594A
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Prior art keywords
transistor
coupled
drain
potential
latch
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JP2006525512A
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English (en)
Japanese (ja)
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JP2007504594A5 (enExample
Inventor
チェー，ミョン，チャン
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ズィーモス テクノロジー，インコーポレイテッド
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Publication of JP2007504594A publication Critical patent/JP2007504594A/ja
Publication of JP2007504594A5 publication Critical patent/JP2007504594A5/ja
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4085—Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4094—Bit-line management or control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/02—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding parasitic signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/065—Differential amplifiers of latching type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/08—Control thereof
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/005—Transfer gates, i.e. gates coupling the sense amplifier output to data lines, I/O lines or global bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2227—Standby or low power modes

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Vehicle Body Suspensions (AREA)
  • Logic Circuits (AREA)
JP2006525512A 2003-09-05 2004-09-03 ダイナミック・メモリー、センス増幅器回路、ワード線駆動回路、制御信号ｐｘ駆動回路、信号センス又はリストア方法、及び漏れ電流低減方法 Pending JP2007504594A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US50066203P 2003-09-05 2003-09-05
PCT/US2004/029038 WO2005024834A2 (en) 2003-09-05 2004-09-03 Low voltage operation dram control circuits

Publications (2)

Publication Number Publication Date
JP2007504594A true JP2007504594A (ja) 2007-03-01
JP2007504594A5 JP2007504594A5 (enExample) 2009-12-24

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006525512A Pending JP2007504594A (ja) 2003-09-05 2004-09-03 ダイナミック・メモリー、センス増幅器回路、ワード線駆動回路、制御信号ｐｘ駆動回路、信号センス又はリストア方法、及び漏れ電流低減方法

Country Status (9)

Country Link
US (3) US7082048B2 (enExample)
EP (1) EP1661137B1 (enExample)
JP (1) JP2007504594A (enExample)
KR (1) KR20060119934A (enExample)
CN (1) CN1898744A (enExample)
AT (1) ATE439672T1 (enExample)
CA (1) CA2537632A1 (enExample)
DE (1) DE602004022561D1 (enExample)
WO (1) WO2005024834A2 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9214218B2 (en) 2011-03-14 2015-12-15 Ps4 Luxco S.A.R.L. Semiconductor DRAM with non-linear word line discharge

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US7287171B1 (en) 2004-03-08 2007-10-23 Altera Corporation Systems and methods for reducing static and total power consumption in programmable logic device architectures
TW200721163A (en) * 2005-09-23 2007-06-01 Zmos Technology Inc Low power memory control circuits and methods
US7755964B2 (en) * 2006-10-25 2010-07-13 Qualcomm Incorporated Memory device with configurable delay tracking
KR100897282B1 (ko) * 2007-11-07 2009-05-14 주식회사 하이닉스반도체 리시버 회로
KR101096225B1 (ko) * 2008-08-21 2011-12-22 주식회사 하이닉스반도체 반도체 메모리 장치 및 그 구동방법
TWI457575B (zh) * 2012-04-06 2014-10-21 Ind Tech Res Inst 具有自我測試的像素陣列模組及其自我測試方法
CN103077739B (zh) * 2012-12-31 2015-07-29 清华大学 一种冗余结构动态随机访问存储单元
US8896344B1 (en) 2013-01-04 2014-11-25 Altera Corporation Heterogeneous programmable device and configuration software adapted therefor
CN103531229A (zh) * 2013-10-18 2014-01-22 上海工程技术大学 一种静态随机存储器
KR20170013488A (ko) * 2015-07-27 2017-02-07 에스케이하이닉스 주식회사 반도체장치 및 반도체시스템
US10656995B2 (en) 2018-10-03 2020-05-19 Micron Technology, Inc. Copy-back operations in a memory device
KR102615012B1 (ko) 2018-11-12 2023-12-19 삼성전자주식회사 메모리 장치 및 그것의 동작 방법
CN114400999A (zh) 2020-12-21 2022-04-26 台湾积体电路制造股份有限公司 电路及其操作方法
CN115620767B (zh) * 2021-07-12 2025-06-06 长鑫存储技术有限公司 存储器的检测方法和存储器的检测装置

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JPH02246089A (ja) * 1989-03-20 1990-10-01 Hitachi Ltd 半導体集積回路
JPH11328955A (ja) * 1998-05-14 1999-11-30 Mitsubishi Electric Corp 半導体回路装置
JPH11345488A (ja) * 1998-06-01 1999-12-14 Hitachi Ltd 半導体記憶装置
JP2001014846A (ja) * 1999-06-30 2001-01-19 Toshiba Corp 半導体集積回路および半導体記憶装置
JP2001101866A (ja) * 1999-09-02 2001-04-13 Samsung Electronics Co Ltd 半導体メモリ装置の感知増幅器

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JP3306682B2 (ja) * 1993-08-18 2002-07-24 日本テキサス・インスツルメンツ株式会社 駆動回路
JP3667787B2 (ja) * 1994-05-11 2005-07-06 株式会社ルネサステクノロジ 半導体記憶装置
US5434822A (en) * 1994-07-07 1995-07-18 Intel Corporation Apparatus and method for adjusting and maintaining a bitline precharge level
JP3482020B2 (ja) * 1994-12-22 2003-12-22 松下電器産業株式会社 センスアンプ回路
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KR100568544B1 (ko) * 2004-09-20 2006-04-07 삼성전자주식회사 계층적 비트 라인 구조를 가지는 반도체 메모리 장치 및반도체 메모리 장치의 동작 방법

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JPH02246089A (ja) * 1989-03-20 1990-10-01 Hitachi Ltd 半導体集積回路
JPH11328955A (ja) * 1998-05-14 1999-11-30 Mitsubishi Electric Corp 半導体回路装置
JPH11345488A (ja) * 1998-06-01 1999-12-14 Hitachi Ltd 半導体記憶装置
JP2001014846A (ja) * 1999-06-30 2001-01-19 Toshiba Corp 半導体集積回路および半導体記憶装置
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9214218B2 (en) 2011-03-14 2015-12-15 Ps4 Luxco S.A.R.L. Semiconductor DRAM with non-linear word line discharge

Also Published As

Publication number Publication date
EP1661137A4 (en) 2007-05-30
US20060227593A1 (en) 2006-10-12
US7082048B2 (en) 2006-07-25
WO2005024834A2 (en) 2005-03-17
US7839701B2 (en) 2010-11-23
DE602004022561D1 (de) 2009-09-24
US7324390B2 (en) 2008-01-29
CN1898744A (zh) 2007-01-17
US20050083769A1 (en) 2005-04-21
US20080008018A1 (en) 2008-01-10
EP1661137A2 (en) 2006-05-31
EP1661137B1 (en) 2009-08-12
CA2537632A1 (en) 2005-03-17
WO2005024834A3 (en) 2005-12-15
KR20060119934A (ko) 2006-11-24
ATE439672T1 (de) 2009-08-15

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