TW201145275A - Memory cell and an associated memory device - Google Patents

Abstract

A memory cell includes a pair of sub-cells, each including an access transistor, a storage transistor, and an isolation transistor that are serially coupled in sequence with their source/drain connected. The isolation transistor is shared with a sub-cell of an adjacent memory cell and always turned off, wherein the storage transistor is always turned on. A wordline is coupled to a gate of the access transistor of each sub-cell, and complementary bit lines are respectively coupled to sources/drains of the access transistors of the pair of sub-cells, such that data bit may be accessed between the bit line and the corresponding storage transistor through the corresponding access transistor.

Description

201145275 VI. Description of the Invention: [Technical Field] [0001] The present invention relates to a semiconductor memory, and more particularly to a 3T2C (3-1; ransistor-2-capacitor) dynamic random access memory (dynamic random Access memory) unit. [Prior Art] [0002] Semiconductor memory is one of the most commonly used data storage media, such as dynamic random access memory (DRAM) and static random access memory (static random access memory). SRAM). The semiconductor memory can be fabricated into a single integrated circuit or integrated with other components to form a system on chip (S0C). [0003] In current system wafer applications, memory occupies a substantial portion of the entire wafer area, such as 60% to 70%. Therefore, the choice of memory type and technology will have an important impact on the performance and cost of the entire wafer. [0004] Some system chips use dynamic random access memory technology as a data storage medium. The first A diagram shows a schematic diagram of a conventional dynamic random access memory cell including a storage capacitor Cs and an access transistor Ta. Due to the simple architecture, the density of dynamic random access memory is usually higher than that of static random access memory. However, conventional dynamic random access memory devices require specific process technology to form a large capacitance storage capacitor Cs on a small germanium wafer. Moreover, this particular process technology is not compatible with the system wafer process, thus increasing the overall manufacturing cost. [0005] Other system chips use static random access memory technology as a data storage medium. The first B-picture shows a conventional SRAM unit 099118016, Form No. A0101, No. 4/20, 0992031922-0, 201145275, which includes two cross-coupled inverters 10Q and Two access transistors Tb, Tc. Unlike dynamic random access, the SRAM process is compatible with system wafer processes, but its density is lower than that of dynamic random access memory. Furthermore, as shown in the first B diagram, since the cross-coupled inverter 10 is directly connected between the power supply Vdd and the ground, the static random access memory is easy to interfere with the noise of the power supply. [0006] Therefore, there is a need to propose a novel memory architecture that can use standard complementary metal-oxide-semiconductor (MPP)S) processes to reduce manufacturing costs and have higher The nature of density. SUMMARY OF THE INVENTION [0007] One of the objects of the present invention is to provide a memory cell architecture and a related high-density dynamic random access memory device, which can be applied to a system wafer process, and Not disturbed by power noise. [0008] According to an embodiment of the present invention, a memory unit includes a pair of subunits,

Each morning _ A 099118016 兀 early 兀 includes an access transistor, a storage transistor, and an isolation transistor, which are connected in series by the connection source/depolarization in a separate isolation system. In a subunit adjacent to the memory unit and is always closed. The storage transistor is always on. The word line is consumed by the access transistor of each + unit and the complementary bit line (the complementary bit is connected to the source of the access transistor of the meta-pair) / No pole, so by using the transistor, the form number can be accessed between the corresponding bit line and the storage transistor. Page 5 / Total 2Q stomach 〇 〇 192 192 192 192 192 192 192 192 192 192 192 192 192 192 192 192 192 192 192 192 192 192 192 192 192 192 192 192 192 192 192 192 In another embodiment of the present invention, a memory device includes a plurality of memory cells as described above. Each memory cell further includes a precharge path and a sense amplifier. When the precharge path is activated, the complementary bit can be The power line is pre-charged to a voltage level. When the sense amplifier is activated, the complementary bit line can be driven to the level of the power source and the ground end respectively. [Embodiment] [0010] The second figure shows the embodiment of the present invention. A circuit diagram of the memory unit 20 of the dynamic random access memory (DRA Μ ). In this embodiment, each memory unit 20 uses a differential architecture to store complementary data bits. Say, memory list The second sub-unit 200A includes a pair of sub-units 200A, 20 0B. The first sub-unit 200A includes an access transistor Ma, a storage transistor Me, and an isolation transistor Me. Similarly, the second sub-unit 200B also includes an access. The transistor Mb, a storage transistor Md, and an isolation transistor Mf. Although the present embodiment uses a P-type metal-ox-ide-semiconductor (PMOS) transistor, an N-type can also be used. A metal-oxide-semiconductor (N-type MOS) transistor, or a combination of the two, is not limited to the disclosure. It is worth noting that the isolation transistors Me and Mf are respectively shared to sub-units of adjacent memory cells. In other words, the first sub-unit 200A actually includes only half of the isolated transistor Me, and the second sub-unit 200B includes only half of the isolated transistor Mf. Therefore, each memory unit 20 includes two accesses in total. The transistor, two storage transistors as capacitors, and an isolation transistor. Therefore, the memory unit 20 of the present embodiment can be referred to as a 3T2C memory unit or a 5T memory unit. 099118016 Table Early Number A0101 Page 6 of 20 Page 09920 31922-0 201145275 The subunits just mentioned above, such as the first subunit 2〇〇A, the access transistor, the storage transistor Me and the isolated transistor are connected (directly or indirectly) to the source/汲 sequentially. Extremely coupled in series. It is worth noting that the source and drain of a symmetrical MOS transistor are interchangeable, so the source of the transistor is not specifically described or labeled in this specification and the drawings. Pole and bungee, but use, source / bungee, to represent the source or bungee. In addition, "coupled," or "connected" as used in the present specification means that the two elements are directly connected by wire or indirectly through at least one intermediate element. [0012] In this embodiment, The gates of the access transistors Ma and Mb are coupled to a word line (WL). The source/drain electrodes of the access transistors Ma and Mb that are not connected to the storage transistors 1, Md are respectively coupled. Connected to the complementary bit lines BL, BL_b. Therefore, by accessing the transistor Ma/Mb, charge access can be performed between the bit line BL/BL_b and the corresponding storage transistor rib/Md. The storage transistor Mc/m_ is connected to the ground GND, the gate of the isolation transistor Me/Mf is coupled to the power source, and (4) the isolation transistor not connected to the storage transistor k, Md. Me,

The source/drain electrodes of the Mf are respectively coupled to the storage transistors of the subunits adjacent to the cell. [0013] Very 髁 迅 朱 朱 称 称 称 称 称 称 称 称 称 称 称 称 称 称 称 称 称 称 称 称 称 称Bud xide in_ Μ — ) will form a Version layer, thus producing electrons... Generally speaking, the generation is opposite to the majority (major-...). The reverse layer of this embodiment can be used for storage. Data bit. The capacitance of the storage transistor Me, Md is based on its parasitic 099118016 Form No. A0101 0992031922-0 Main Road (4) 诵 1 Page 7 / Total 20 pages 201145275 Capacitance: Determined. According to the embodiment In the differential architecture, if the block material level tlG is stored in a storage transistor, such as a transistor &, the data bit 1 is stored in another storage transistor, such as a transistor. Further, due to the isolation transistor Me, The Mf system is directly closed, so that the stored data is isolated from the adjacent memory unit. [0015] FIG. 3A shows a memory device according to an embodiment of the present invention, which includes the memory unit 20 of the second figure. And pre-charging the channel, the sense amplifier 32. In the present embodiment, the pre-charging circuit 30 includes three pre-charged crystals ρι, p2, P3, wherein the pre-charged crystals PhP2 are wired in series with the complementary bit line BL, Between BL-b. Precharge crystal P 1. The source/drain connection between P2 is coupled to the power supply Vdd (or a voltage level). The source and the drain of the precharged crystal P3 are respectively coupled to the complementary bit line, BL_b. The gates of the pre-charged crystals PI, P2, and P3 are coupled to a precharge signal pre. Although the present embodiment uses a p-type metal oxide semiconductor transistor, an N-type metal oxide semiconductor (N_type MOS) may be used. The transistor: . . . , or a combination of the two. The design of the pre-charging circuit 30 disclosed in the present invention may also be replaced by a conventional pre-charging circuit, and may also be modified according to the prior art. Therefore, the sensing amplifier 32 includes two cross-coupling inverters 320 and a first sensing transistor si (for example, N-type metal oxide). And a second sensing transistor S2 (eg, a P-type metal oxide semiconductor transistor), wherein 'the second sensing transistor S2, the two cross-coupled inverters 320, and the first sensing transistor S1 are The series is coupled in series between the power supply Vdd and the ground GND. The first sensing The gate of the crystal S1 will be driven by the first sensing signal sa' and the second sensing transistor 099118016 Form No. A0101 Page 8 / Total 20 pages 0992031922-0 201145275 The gate of the body S2 will be the second sensing signal _ The input terminals of the driving inverter 320 are coupled respectively: a buffer of c is further divided into the complementary bit lines BL, BL b. The design of the inverter 32 is also - dare, h is determined by 1 The use of a sense amplifier is also limited to the disclosure of the art according to the skill of the art. / Again, it is not [0016] The third B picture shows the memory device of the third A picture _ heart tribute to the relevant waveform not to be 1 1 pre-charge fine e when the time (four) is pulled to the main pure level, the charging path 30 conduction. Therefore, the 'parallel bit line is precharged to the voltage level of the power supply. Then, at time, by pulling the precharge signal Pre back to the passive high level, the precharge path 3 is turned off, and the selected word is pulled to the active low level. The stored charge will be shared between the selected subunit (e.g., the first subunit 2A) and its corresponding bit line (e.g., bit line BL). Thus, the voltage level on the bit line 6 will change slightly, and after a phenomenon of voltage swing (v〇jtage squeaking) between the complementary bit lines ~b occurs, at time t3, the first A sense* signal sa is pulled to the active high level to turn on the sense amplifier Μ, thus discharging the bit line (eg, BL) whose voltage is swinging down (down~Swing) to be closer to the low level. As shown in Figure 3. Next, at time and time, the second sense signal sab is pulled to the active low level, thus the up-swing bit line (eg BL_b) Charging, so that it is closer to the same level. During the sense amplification, in order to make the complementary bit lines BL, BL_b form a full swing, it is intended to be close to the grounding GND and the power supply Vdd, respectively. The two coupled and coupled inverters 32 加强 will strengthen each other's signals to form a latch. 099118016 Form No. A0101 Page 9 / Total 20 Page 0992031922-0 201145275 [0017] When the memory of the third A picture When the body device performs a write operation, the complementary bit is driven separately by writing data Lines BL, BL_b to power supply Vdd and ground GND. In one embodiment, the precharge path 30 and the sense amplifier 32 need not be activated when writing is performed. In another embodiment, when writing is performed The precharge path 30 and the sense amplifier 32 can be activated as described above and in the third B. For the latter embodiment, the same bit line selected (which has the same word line WL) can be at the same time The same program is used for writing and reading operations, whereby the memory cells outside the write memory unit can be re-read (er er ead) during the write operation, so that the attenuated stored charge can be According to the above, the present embodiment adopts a differential architecture and avoids the capacitance used by the conventional dynamic random access memory, thereby facilitating the integration of the memory and the system, for example, integration with the system chip. In addition, the architecture of the memory unit of the present embodiment (second diagram) is simpler than that of the conventional static random access memory unit (the first B diagram). Moreover, the storage transistors Me and Md of the embodiment are not directly connected to the power supply. Vdd The grounding terminal GND is coupled, so that the influence of the power supply noise is more avoided than the conventional static random access memory unit (Fig. B). [0019] The above description is only a preferred embodiment of the present invention, and is not used. The scope of the invention is defined by the scope of the invention, and the equivalents and modifications of the invention may be included in the scope of the following claims. [0020] Figure A shows a schematic diagram of a conventional dynamic random access memory cell. The first B diagram shows a schematic diagram of a conventional static random access memory cell. 099118016 Form No. A0101 Page 10 of 20 0992031922-0 201145275 The second figure shows a circuit diagram of a memory cell of a dynamic random access memory according to an embodiment of the present invention. FIG. 3A shows a memory device according to an embodiment of the present invention, which includes a memory unit of the second figure, and a precharge path and a sense amplifier. The third B diagram illustrates the correlation waveform of the memory device of the third A diagram.

[Main component symbol description] [0021] 10 Inverter 20 Memory unit 200A First subunit 200B Second subunit 30 Precharge path 32 Sensing amplification 1 § 320 Inverter Vdd Power supply GND Ground terminal Cs Storage capacitor Ta Access transistor Tb, Tc access transistor Ma, Mb access transistor Me, Md storage transistor Me, Mf isolation transistor WL word line BL, BL_b (complementary) bit line PI, P2, P3 precharge Crystal pre precharge signal S1 first sense transistor 099118016 0992031922-0 Form No. A0101 Page 11 / Total 20 pages 201145275 S2 sa sab 11, second sensing transistor first sensing signal second sensing signal t2 T3, t4 time 099118016 Form number A0101 Page 12 / Total 20 pages 0992031922-0

Claims (1)

201145275 VII. Patent application scope: 1. A memory unit, comprising: a pair of sub-units, each of the sub-units comprising an access transistor, a storage transistor and an isolation transistor, which are sequentially connected by a connection source The pole/drain is coupled in series, wherein the isolated cell system shares the subunit used in a neighboring memory cell, and the isolated cell system is always turned off, and the storage cell system is always turned on. a word line coupled to one of the gates of each of the sub-cells; and a complementary bit 1 ines coupled to the pair of sub-units The source/drain of the transistor is taken, so that the data transistor can be accessed between the corresponding bit line and the storage transistor by the access transistor. 2. The memory unit of claim 1, wherein the source/> and the poles of the access transistors not connected to the storage transistors are respectively connected to the complementary bits. line. 3. The memory unit of claim 1, wherein the access transistor, the storage transistor, and the isolated transistor system are N-type metal oxide semiconductor (NMOS) transistors. 4. The memory unit of claim 1, wherein the access transistor, the storage transistor, and the isolated electro-crystal system are P-type metal oxide semiconductor (PMOS) transistors. 5. The memory unit of claim 4, wherein the gate of the storage transistor is coupled to a ground. 6. The memory unit according to claim 4, wherein the isolated electric 099118016 form number A0101 page 13 / total 20 pages 0992031922-0 201145275 The gate of the crystal is coupled to a power source. 7. The memory unit of claim 1, wherein the complementary data bits are stored in the storage transistors of the pair of subunits, respectively. 8. The memory unit of claim 1, wherein the source/drain electrodes of the isolated transistors not connected to the storage transistors are respectively coupled to the adjacent memory cells. The storage cells of the subunits. 9. A memory device, comprising: a plurality of memory cells, each of the memory cells comprising: a pair of sub-units, each of the sub-units comprising an access transistor, a storage transistor, and an isolation transistor, The series is coupled in series by connecting the source/drain, wherein the isolated cell system shares the sub-cell used in a neighboring memory cell, and the isolated cell system is always turned off, and the a memory cell system is always turned on; a word line coupled to the gate of the access transistor of each of the subunits; and a complementary bit line coupled to the pair The sub-cell accesses the source/drain of the transistor, so that the access transistor can access the data bit between the corresponding bit line and the storage transistor; a pre-charge path, coupled Connected between the complementary bit lines, when the precharge path is activated, to precharge the complementary bit lines to a voltage level: and a sense amplifier coupled to the complementary bits Between the lines, when the sense amplifier is When starting, it is used to respectively drive the complementary bit lines to a power source and a ground terminal. 10. The memory device of claim 9, wherein the access transistor, the storage transistor, and the isolated transistor system are N-type metal oxides 099118016 Form No. A0101 Page 14 of 20 pages 0992031922 -0 201145275 Semiconductor (NM0S) transistor. 11. The memory device of claim 9, wherein the access transistor, the storage transistor, and the isolated transistor system are P-type metal oxide semiconductor (PMOS) transistors. 12. The memory device of claim 11, wherein the gate of the storage transistor is coupled to the ground. 13. The memory device of claim 11, wherein the gate of the isolating transistor is coupled to a power source. 14. The memory device of claim 9, wherein the complementary data bits are stored in the storage transistors of the pair of subunits, respectively. The memory device of claim 9, wherein the source/drain electrodes of the access transistors not connected to the storage transistors are respectively coupled to the complementary bit lines. The memory device of claim 9, wherein the source/pole/poles of the isolated transistors not connected to the storage transistors are respectively connected to the adjacent memory unit. The storage cells of the subunits. 099118016 Form No. A0101 Page 15 of 20 0992031922-0