CA2537632A1 - Low voltage operation dram control circuits - Google Patents
Low voltage operation dram control circuits Download PDFInfo
- Publication number
- CA2537632A1 CA2537632A1 CA002537632A CA2537632A CA2537632A1 CA 2537632 A1 CA2537632 A1 CA 2537632A1 CA 002537632 A CA002537632 A CA 002537632A CA 2537632 A CA2537632 A CA 2537632A CA 2537632 A1 CA2537632 A1 CA 2537632A1
- Authority
- CA
- Canada
- Prior art keywords
- voltage
- coupled
- drain
- recited
- transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 230000000295 complement effect Effects 0.000 claims abstract description 48
- 238000000034 method Methods 0.000 claims abstract description 33
- 230000015654 memory Effects 0.000 claims description 39
- 210000004027 cell Anatomy 0.000 claims description 23
- 230000008878 coupling Effects 0.000 claims description 10
- 238000010168 coupling process Methods 0.000 claims description 10
- 238000005859 coupling reaction Methods 0.000 claims description 10
- 210000000352 storage cell Anatomy 0.000 claims description 8
- 230000002441 reversible effect Effects 0.000 claims description 6
- 238000006243 chemical reaction Methods 0.000 claims description 3
- 230000000717 retained effect Effects 0.000 claims description 3
- 230000003213 activating effect Effects 0.000 claims 2
- 238000012163 sequencing technique Methods 0.000 claims 2
- 238000007599 discharging Methods 0.000 abstract description 3
- 230000009286 beneficial effect Effects 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 11
- 230000002829 reductive effect Effects 0.000 description 6
- 101100137906 Nicotiana sylvestris PSAEB gene Proteins 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 4
- 238000006731 degradation reaction Methods 0.000 description 4
- 230000007246 mechanism Effects 0.000 description 4
- 101150032357 psaE gene Proteins 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 230000004044 response Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 208000032750 Device leakage Diseases 0.000 description 1
- 101150030705 MNS1 gene Proteins 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000000670 limiting effect Effects 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000036961 partial effect Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/408—Address circuits
- G11C11/4085—Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4094—Bit-line management or control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/02—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding parasitic signals
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
- G11C7/065—Differential amplifiers of latching type
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
- G11C7/08—Control thereof
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/005—Transfer gates, i.e. gates coupling the sense amplifier output to data lines, I/O lines or global bit lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/22—Control and timing of internal memory operations
- G11C2207/2227—Standby or low power modes
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Dram (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
- Vehicle Body Suspensions (AREA)
- Logic Circuits (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US50066203P | 2003-09-05 | 2003-09-05 | |
| US60/500,662 | 2003-09-05 | ||
| PCT/US2004/029038 WO2005024834A2 (en) | 2003-09-05 | 2004-09-03 | Low voltage operation dram control circuits |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA2537632A1 true CA2537632A1 (en) | 2005-03-17 |
Family
ID=34272981
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002537632A Abandoned CA2537632A1 (en) | 2003-09-05 | 2004-09-03 | Low voltage operation dram control circuits |
Country Status (9)
| Country | Link |
|---|---|
| US (3) | US7082048B2 (enExample) |
| EP (1) | EP1661137B1 (enExample) |
| JP (1) | JP2007504594A (enExample) |
| KR (1) | KR20060119934A (enExample) |
| CN (1) | CN1898744A (enExample) |
| AT (1) | ATE439672T1 (enExample) |
| CA (1) | CA2537632A1 (enExample) |
| DE (1) | DE602004022561D1 (enExample) |
| WO (1) | WO2005024834A2 (enExample) |
Families Citing this family (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7287171B1 (en) | 2004-03-08 | 2007-10-23 | Altera Corporation | Systems and methods for reducing static and total power consumption in programmable logic device architectures |
| TW200721163A (en) * | 2005-09-23 | 2007-06-01 | Zmos Technology Inc | Low power memory control circuits and methods |
| US7755964B2 (en) * | 2006-10-25 | 2010-07-13 | Qualcomm Incorporated | Memory device with configurable delay tracking |
| KR100897282B1 (ko) * | 2007-11-07 | 2009-05-14 | 주식회사 하이닉스반도체 | 리시버 회로 |
| KR101096225B1 (ko) * | 2008-08-21 | 2011-12-22 | 주식회사 하이닉스반도체 | 반도체 메모리 장치 및 그 구동방법 |
| JP2012190522A (ja) | 2011-03-14 | 2012-10-04 | Elpida Memory Inc | 半導体装置 |
| TWI457575B (zh) * | 2012-04-06 | 2014-10-21 | Ind Tech Res Inst | 具有自我測試的像素陣列模組及其自我測試方法 |
| CN103077739B (zh) * | 2012-12-31 | 2015-07-29 | 清华大学 | 一种冗余结构动态随机访问存储单元 |
| US8896344B1 (en) | 2013-01-04 | 2014-11-25 | Altera Corporation | Heterogeneous programmable device and configuration software adapted therefor |
| CN103531229A (zh) * | 2013-10-18 | 2014-01-22 | 上海工程技术大学 | 一种静态随机存储器 |
| KR20170013488A (ko) * | 2015-07-27 | 2017-02-07 | 에스케이하이닉스 주식회사 | 반도체장치 및 반도체시스템 |
| US10656995B2 (en) | 2018-10-03 | 2020-05-19 | Micron Technology, Inc. | Copy-back operations in a memory device |
| KR102615012B1 (ko) | 2018-11-12 | 2023-12-19 | 삼성전자주식회사 | 메모리 장치 및 그것의 동작 방법 |
| CN114400999A (zh) | 2020-12-21 | 2022-04-26 | 台湾积体电路制造股份有限公司 | 电路及其操作方法 |
| CN115620767B (zh) * | 2021-07-12 | 2025-06-06 | 长鑫存储技术有限公司 | 存储器的检测方法和存储器的检测装置 |
Family Cites Families (27)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62252597A (ja) * | 1986-04-24 | 1987-11-04 | Sony Corp | センスアンプ |
| JP2934448B2 (ja) * | 1989-03-20 | 1999-08-16 | 株式会社日立製作所 | 半導体集積回路 |
| US5187395A (en) * | 1991-01-04 | 1993-02-16 | Motorola, Inc. | BIMOS voltage bias with low temperature coefficient |
| JP3306682B2 (ja) * | 1993-08-18 | 2002-07-24 | 日本テキサス・インスツルメンツ株式会社 | 駆動回路 |
| JP3667787B2 (ja) * | 1994-05-11 | 2005-07-06 | 株式会社ルネサステクノロジ | 半導体記憶装置 |
| US5434822A (en) * | 1994-07-07 | 1995-07-18 | Intel Corporation | Apparatus and method for adjusting and maintaining a bitline precharge level |
| JP3482020B2 (ja) * | 1994-12-22 | 2003-12-22 | 松下電器産業株式会社 | センスアンプ回路 |
| TW306001B (enExample) * | 1995-02-08 | 1997-05-21 | Matsushita Electric Industrial Co Ltd | |
| JP3260583B2 (ja) * | 1995-04-04 | 2002-02-25 | 株式会社東芝 | ダイナミック型半導体メモリおよびそのテスト方法 |
| US5627487A (en) * | 1995-06-28 | 1997-05-06 | Micron Technology, Inc. | Charge conserving driver circuit for capacitive loads |
| US5640350A (en) * | 1996-05-01 | 1997-06-17 | Iga; Adam Sempa | Multi-bit dynamic random access memory cell storage |
| JPH10241361A (ja) * | 1997-02-25 | 1998-09-11 | Toshiba Corp | 半導体記憶装置 |
| JP3742191B2 (ja) * | 1997-06-06 | 2006-02-01 | 株式会社東芝 | 半導体集積回路装置 |
| US6043682A (en) * | 1997-12-23 | 2000-03-28 | Intel Corporation | Predriver logic circuit |
| JP3853513B2 (ja) * | 1998-04-09 | 2006-12-06 | エルピーダメモリ株式会社 | ダイナミック型ｒａｍ |
| JPH11328955A (ja) * | 1998-05-14 | 1999-11-30 | Mitsubishi Electric Corp | 半導体回路装置 |
| US6525896B2 (en) * | 1998-05-14 | 2003-02-25 | International Business Machines Corporation | Method and circuitry for high voltage application with MOSFET technology |
| JPH11345488A (ja) * | 1998-06-01 | 1999-12-14 | Hitachi Ltd | 半導体記憶装置 |
| US6573548B2 (en) * | 1998-08-14 | 2003-06-03 | Monolithic System Technology, Inc. | DRAM cell having a capacitor structure fabricated partially in a cavity and method for operating same |
| US6535415B2 (en) * | 1999-02-22 | 2003-03-18 | Hitachi, Ltd. | Semiconductor device |
| JP2001014846A (ja) * | 1999-06-30 | 2001-01-19 | Toshiba Corp | 半導体集積回路および半導体記憶装置 |
| KR100331550B1 (ko) * | 1999-09-02 | 2002-04-06 | 윤종용 | 반도체 메모리장치의 감지증폭기 |
| JP2002074950A (ja) * | 2000-08-29 | 2002-03-15 | Toshiba Corp | 半導体集積回路 |
| JP2002298579A (ja) * | 2001-03-29 | 2002-10-11 | Toshiba Corp | 半導体記憶装置 |
| US6545923B2 (en) * | 2001-05-04 | 2003-04-08 | Samsung Electronics Co., Ltd. | Negatively biased word line scheme for a semiconductor memory device |
| JP4439167B2 (ja) * | 2002-08-30 | 2010-03-24 | 株式会社ルネサステクノロジ | 半導体記憶装置 |
| KR100568544B1 (ko) * | 2004-09-20 | 2006-04-07 | 삼성전자주식회사 | 계층적 비트 라인 구조를 가지는 반도체 메모리 장치 및반도체 메모리 장치의 동작 방법 |
-
2004
- 2004-09-03 CN CNA2004800266531A patent/CN1898744A/zh active Pending
- 2004-09-03 DE DE602004022561T patent/DE602004022561D1/de not_active Expired - Lifetime
- 2004-09-03 CA CA002537632A patent/CA2537632A1/en not_active Abandoned
- 2004-09-03 US US10/934,312 patent/US7082048B2/en not_active Expired - Fee Related
- 2004-09-03 WO PCT/US2004/029038 patent/WO2005024834A2/en not_active Ceased
- 2004-09-03 KR KR1020067004455A patent/KR20060119934A/ko not_active Withdrawn
- 2004-09-03 JP JP2006525512A patent/JP2007504594A/ja active Pending
- 2004-09-03 EP EP04783327A patent/EP1661137B1/en not_active Expired - Lifetime
- 2004-09-03 AT AT04783327T patent/ATE439672T1/de not_active IP Right Cessation
-
2006
- 2006-06-07 US US11/449,170 patent/US7324390B2/en not_active Expired - Fee Related
-
2007
- 2007-06-27 US US11/769,538 patent/US7839701B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| EP1661137A4 (en) | 2007-05-30 |
| US20060227593A1 (en) | 2006-10-12 |
| US7082048B2 (en) | 2006-07-25 |
| WO2005024834A2 (en) | 2005-03-17 |
| US7839701B2 (en) | 2010-11-23 |
| DE602004022561D1 (de) | 2009-09-24 |
| US7324390B2 (en) | 2008-01-29 |
| CN1898744A (zh) | 2007-01-17 |
| US20050083769A1 (en) | 2005-04-21 |
| US20080008018A1 (en) | 2008-01-10 |
| EP1661137A2 (en) | 2006-05-31 |
| EP1661137B1 (en) | 2009-08-12 |
| WO2005024834A3 (en) | 2005-12-15 |
| JP2007504594A (ja) | 2007-03-01 |
| KR20060119934A (ko) | 2006-11-24 |
| ATE439672T1 (de) | 2009-08-15 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| FZDE | Discontinued |