ATE439672T1 - Dram-steuerschaltungen mit niederspannungsbetrieb - Google Patents

Dram-steuerschaltungen mit niederspannungsbetrieb

Info

Publication number
ATE439672T1
ATE439672T1 AT04783327T AT04783327T ATE439672T1 AT E439672 T1 ATE439672 T1 AT E439672T1 AT 04783327 T AT04783327 T AT 04783327T AT 04783327 T AT04783327 T AT 04783327T AT E439672 T1 ATE439672 T1 AT E439672T1
Authority
AT
Austria
Prior art keywords
sense
gate voltages
restore
complementary
low voltage
Prior art date
Application number
AT04783327T
Other languages
English (en)
Inventor
Myung Choi
Original Assignee
Zmos Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Zmos Technology Inc filed Critical Zmos Technology Inc
Application granted granted Critical
Publication of ATE439672T1 publication Critical patent/ATE439672T1/de

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4085—Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4094—Bit-line management or control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/02—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding parasitic signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/065—Differential amplifiers of latching type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/08—Control thereof
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/005—Transfer gates, i.e. gates coupling the sense amplifier output to data lines, I/O lines or global bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2227—Standby or low power modes

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Vehicle Body Suspensions (AREA)
  • Logic Circuits (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
AT04783327T 2003-09-05 2004-09-03 Dram-steuerschaltungen mit niederspannungsbetrieb ATE439672T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US50066203P 2003-09-05 2003-09-05
PCT/US2004/029038 WO2005024834A2 (en) 2003-09-05 2004-09-03 Low voltage operation dram control circuits

Publications (1)

Publication Number Publication Date
ATE439672T1 true ATE439672T1 (de) 2009-08-15

Family

ID=34272981

Family Applications (1)

Application Number Title Priority Date Filing Date
AT04783327T ATE439672T1 (de) 2003-09-05 2004-09-03 Dram-steuerschaltungen mit niederspannungsbetrieb

Country Status (9)

Country Link
US (3) US7082048B2 (de)
EP (1) EP1661137B1 (de)
JP (1) JP2007504594A (de)
KR (1) KR20060119934A (de)
CN (1) CN1898744A (de)
AT (1) ATE439672T1 (de)
CA (1) CA2537632A1 (de)
DE (1) DE602004022561D1 (de)
WO (1) WO2005024834A2 (de)

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US7287171B1 (en) 2004-03-08 2007-10-23 Altera Corporation Systems and methods for reducing static and total power consumption in programmable logic device architectures
TW200721163A (en) * 2005-09-23 2007-06-01 Zmos Technology Inc Low power memory control circuits and methods
US7755964B2 (en) * 2006-10-25 2010-07-13 Qualcomm Incorporated Memory device with configurable delay tracking
KR100897282B1 (ko) * 2007-11-07 2009-05-14 주식회사 하이닉스반도체 리시버 회로
KR101096225B1 (ko) * 2008-08-21 2011-12-22 주식회사 하이닉스반도체 반도체 메모리 장치 및 그 구동방법
JP2012190522A (ja) 2011-03-14 2012-10-04 Elpida Memory Inc 半導体装置
TWI457575B (zh) * 2012-04-06 2014-10-21 Ind Tech Res Inst 具有自我測試的像素陣列模組及其自我測試方法
CN103077739B (zh) * 2012-12-31 2015-07-29 清华大学 一种冗余结构动态随机访问存储单元
US8896344B1 (en) 2013-01-04 2014-11-25 Altera Corporation Heterogeneous programmable device and configuration software adapted therefor
CN103531229A (zh) * 2013-10-18 2014-01-22 上海工程技术大学 一种静态随机存储器
KR20170013488A (ko) * 2015-07-27 2017-02-07 에스케이하이닉스 주식회사 반도체장치 및 반도체시스템
US10656995B2 (en) 2018-10-03 2020-05-19 Micron Technology, Inc. Copy-back operations in a memory device
KR102615012B1 (ko) 2018-11-12 2023-12-19 삼성전자주식회사 메모리 장치 및 그것의 동작 방법
CN114400999A (zh) * 2020-12-21 2022-04-26 台湾积体电路制造股份有限公司 电路及其操作方法

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JP2934448B2 (ja) * 1989-03-20 1999-08-16 株式会社日立製作所 半導体集積回路
US5187395A (en) * 1991-01-04 1993-02-16 Motorola, Inc. BIMOS voltage bias with low temperature coefficient
JP3306682B2 (ja) * 1993-08-18 2002-07-24 日本テキサス・インスツルメンツ株式会社 駆動回路
JP3667787B2 (ja) * 1994-05-11 2005-07-06 株式会社ルネサステクノロジ 半導体記憶装置
US5434822A (en) * 1994-07-07 1995-07-18 Intel Corporation Apparatus and method for adjusting and maintaining a bitline precharge level
JP3482020B2 (ja) * 1994-12-22 2003-12-22 松下電器産業株式会社 センスアンプ回路
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JP3260583B2 (ja) * 1995-04-04 2002-02-25 株式会社東芝 ダイナミック型半導体メモリおよびそのテスト方法
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US6043682A (en) * 1997-12-23 2000-03-28 Intel Corporation Predriver logic circuit
JP3853513B2 (ja) * 1998-04-09 2006-12-06 エルピーダメモリ株式会社 ダイナミック型ｒａｍ
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JP2002074950A (ja) * 2000-08-29 2002-03-15 Toshiba Corp 半導体集積回路
JP2002298579A (ja) * 2001-03-29 2002-10-11 Toshiba Corp 半導体記憶装置
US6545923B2 (en) * 2001-05-04 2003-04-08 Samsung Electronics Co., Ltd. Negatively biased word line scheme for a semiconductor memory device
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Also Published As

Publication number Publication date
US20060227593A1 (en) 2006-10-12
US7839701B2 (en) 2010-11-23
KR20060119934A (ko) 2006-11-24
US20080008018A1 (en) 2008-01-10
CA2537632A1 (en) 2005-03-17
WO2005024834A2 (en) 2005-03-17
US7324390B2 (en) 2008-01-29
US20050083769A1 (en) 2005-04-21
EP1661137A4 (de) 2007-05-30
JP2007504594A (ja) 2007-03-01
EP1661137B1 (de) 2009-08-12
CN1898744A (zh) 2007-01-17
DE602004022561D1 (de) 2009-09-24
EP1661137A2 (de) 2006-05-31
US7082048B2 (en) 2006-07-25
WO2005024834A3 (en) 2005-12-15

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