JP2007504594A5 - - Google Patents

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Publication number
JP2007504594A5
JP2007504594A5 JP2006525512A JP2006525512A JP2007504594A5 JP 2007504594 A5 JP2007504594 A5 JP 2007504594A5 JP 2006525512 A JP2006525512 A JP 2006525512A JP 2006525512 A JP2006525512 A JP 2006525512A JP 2007504594 A5 JP2007504594 A5 JP 2007504594A5
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JP
Japan
Prior art keywords
transistor
coupled
drain
latch
potential
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2006525512A
Other languages
English (en)
Japanese (ja)
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JP2007504594A (ja
Filing date
Publication date
Application filed filed Critical
Priority claimed from PCT/US2004/029038 external-priority patent/WO2005024834A2/en
Publication of JP2007504594A publication Critical patent/JP2007504594A/ja
Publication of JP2007504594A5 publication Critical patent/JP2007504594A5/ja
Pending legal-status Critical Current

Links

JP2006525512A 2003-09-05 2004-09-03 ダイナミック・メモリー、センス増幅器回路、ワード線駆動回路、制御信号ｐｘ駆動回路、信号センス又はリストア方法、及び漏れ電流低減方法 Pending JP2007504594A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US50066203P 2003-09-05 2003-09-05
PCT/US2004/029038 WO2005024834A2 (en) 2003-09-05 2004-09-03 Low voltage operation dram control circuits

Publications (2)

Publication Number Publication Date
JP2007504594A JP2007504594A (ja) 2007-03-01
JP2007504594A5 true JP2007504594A5 (enExample) 2009-12-24

Family

ID=34272981

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006525512A Pending JP2007504594A (ja) 2003-09-05 2004-09-03 ダイナミック・メモリー、センス増幅器回路、ワード線駆動回路、制御信号ｐｘ駆動回路、信号センス又はリストア方法、及び漏れ電流低減方法

Country Status (9)

Country Link
US (3) US7082048B2 (enExample)
EP (1) EP1661137B1 (enExample)
JP (1) JP2007504594A (enExample)
KR (1) KR20060119934A (enExample)
CN (1) CN1898744A (enExample)
AT (1) ATE439672T1 (enExample)
CA (1) CA2537632A1 (enExample)
DE (1) DE602004022561D1 (enExample)
WO (1) WO2005024834A2 (enExample)

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US7287171B1 (en) 2004-03-08 2007-10-23 Altera Corporation Systems and methods for reducing static and total power consumption in programmable logic device architectures
TW200721163A (en) * 2005-09-23 2007-06-01 Zmos Technology Inc Low power memory control circuits and methods
US7755964B2 (en) * 2006-10-25 2010-07-13 Qualcomm Incorporated Memory device with configurable delay tracking
KR100897282B1 (ko) * 2007-11-07 2009-05-14 주식회사 하이닉스반도체 리시버 회로
KR101096225B1 (ko) * 2008-08-21 2011-12-22 주식회사 하이닉스반도체 반도체 메모리 장치 및 그 구동방법
JP2012190522A (ja) 2011-03-14 2012-10-04 Elpida Memory Inc 半導体装置
TWI457575B (zh) * 2012-04-06 2014-10-21 Ind Tech Res Inst 具有自我測試的像素陣列模組及其自我測試方法
CN103077739B (zh) * 2012-12-31 2015-07-29 清华大学 一种冗余结构动态随机访问存储单元
US8896344B1 (en) 2013-01-04 2014-11-25 Altera Corporation Heterogeneous programmable device and configuration software adapted therefor
CN103531229A (zh) * 2013-10-18 2014-01-22 上海工程技术大学 一种静态随机存储器
KR20170013488A (ko) * 2015-07-27 2017-02-07 에스케이하이닉스 주식회사 반도체장치 및 반도체시스템
US10656995B2 (en) 2018-10-03 2020-05-19 Micron Technology, Inc. Copy-back operations in a memory device
KR102615012B1 (ko) 2018-11-12 2023-12-19 삼성전자주식회사 메모리 장치 및 그것의 동작 방법
CN114400999A (zh) 2020-12-21 2022-04-26 台湾积体电路制造股份有限公司 电路及其操作方法
CN115620767B (zh) * 2021-07-12 2025-06-06 长鑫存储技术有限公司 存储器的检测方法和存储器的检测装置

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JPS62252597A (ja) * 1986-04-24 1987-11-04 Sony Corp センスアンプ
JP2934448B2 (ja) * 1989-03-20 1999-08-16 株式会社日立製作所 半導体集積回路
US5187395A (en) * 1991-01-04 1993-02-16 Motorola, Inc. BIMOS voltage bias with low temperature coefficient
JP3306682B2 (ja) * 1993-08-18 2002-07-24 日本テキサス・インスツルメンツ株式会社 駆動回路
JP3667787B2 (ja) * 1994-05-11 2005-07-06 株式会社ルネサステクノロジ 半導体記憶装置
US5434822A (en) * 1994-07-07 1995-07-18 Intel Corporation Apparatus and method for adjusting and maintaining a bitline precharge level
JP3482020B2 (ja) * 1994-12-22 2003-12-22 松下電器産業株式会社 センスアンプ回路
TW306001B (enExample) * 1995-02-08 1997-05-21 Matsushita Electric Industrial Co Ltd
JP3260583B2 (ja) * 1995-04-04 2002-02-25 株式会社東芝 ダイナミック型半導体メモリおよびそのテスト方法
US5627487A (en) * 1995-06-28 1997-05-06 Micron Technology, Inc. Charge conserving driver circuit for capacitive loads
US5640350A (en) * 1996-05-01 1997-06-17 Iga; Adam Sempa Multi-bit dynamic random access memory cell storage
JPH10241361A (ja) * 1997-02-25 1998-09-11 Toshiba Corp 半導体記憶装置
JP3742191B2 (ja) * 1997-06-06 2006-02-01 株式会社東芝 半導体集積回路装置
US6043682A (en) * 1997-12-23 2000-03-28 Intel Corporation Predriver logic circuit
JP3853513B2 (ja) * 1998-04-09 2006-12-06 エルピーダメモリ株式会社 ダイナミック型ｒａｍ
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KR100331550B1 (ko) * 1999-09-02 2002-04-06 윤종용 반도체 메모리장치의 감지증폭기
JP2002074950A (ja) * 2000-08-29 2002-03-15 Toshiba Corp 半導体集積回路
JP2002298579A (ja) * 2001-03-29 2002-10-11 Toshiba Corp 半導体記憶装置
US6545923B2 (en) * 2001-05-04 2003-04-08 Samsung Electronics Co., Ltd. Negatively biased word line scheme for a semiconductor memory device
JP4439167B2 (ja) * 2002-08-30 2010-03-24 株式会社ルネサステクノロジ 半導体記憶装置
KR100568544B1 (ko) * 2004-09-20 2006-04-07 삼성전자주식회사 계층적 비트 라인 구조를 가지는 반도체 메모리 장치 및반도체 메모리 장치의 동작 방법

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