JP2006501692A - リバースエンジニアリングを防ぐための導電性チャネル擬似ブロック方法及びその回路 - Google Patents

リバースエンジニアリングを防ぐための導電性チャネル擬似ブロック方法及びその回路 Download PDF

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Publication number
JP2006501692A
JP2006501692A JP2005501980A JP2005501980A JP2006501692A JP 2006501692 A JP2006501692 A JP 2006501692A JP 2005501980 A JP2005501980 A JP 2005501980A JP 2005501980 A JP2005501980 A JP 2005501980A JP 2006501692 A JP2006501692 A JP 2006501692A
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JP
Japan
Prior art keywords
channel
conductive layer
conductive
doped
block structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2005501980A
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English (en)
Japanese (ja)
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JP2006501692A5 (enExample
Inventor
チョウ，ラップ−ワイ
エム，ジュニア クラーク，ウィリアム
ジェイ ハービソン，ギャヴィン
ピー ボウクス，ジェイムズ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HRL Laboratories LLC
Raytheon Co
Original Assignee
HRL Laboratories LLC
Raytheon Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by HRL Laboratories LLC, Raytheon Co filed Critical HRL Laboratories LLC
Publication of JP2006501692A publication Critical patent/JP2006501692A/ja
Publication of JP2006501692A5 publication Critical patent/JP2006501692A5/ja
Pending legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/073—Special arrangements for circuits, e.g. for protecting identification code in memory
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/073—Special arrangements for circuits, e.g. for protecting identification code in memory
    • G06K19/07309—Means for preventing undesired reading or writing from or onto record carriers
    • G06K19/07363—Means for preventing undesired reading or writing from or onto record carriers by preventing analysis of the circuit, e.g. dynamic or static power analysis or current analysis
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/57—Protection from inspection, reverse engineering or tampering
    • H01L23/573—Protection from inspection, reverse engineering or tampering using passive means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/585—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries comprising conductive layers or plates or strips or rods or rings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Theoretical Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Semiconductor Memories (AREA)
JP2005501980A 2002-09-27 2003-09-23 リバースエンジニアリングを防ぐための導電性チャネル擬似ブロック方法及びその回路 Pending JP2006501692A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US41421602P 2002-09-27 2002-09-27
US10/635,790 US7049667B2 (en) 2002-09-27 2003-08-05 Conductive channel pseudo block process and circuit to inhibit reverse engineering
PCT/US2003/030212 WO2004030097A1 (en) 2002-09-27 2003-09-23 A conductive channel pseudo block process and circuit to inhibit reverse engineering

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2010029399A Division JP5185305B2 (ja) 2002-09-27 2010-02-12 リバースエンジニアリングを防ぐための導電性チャネル擬似ブロック処理方法及びその回路

Publications (2)

Publication Number Publication Date
JP2006501692A true JP2006501692A (ja) 2006-01-12
JP2006501692A5 JP2006501692A5 (enExample) 2006-11-16

Family

ID=32033688

Family Applications (2)

Application Number Title Priority Date Filing Date
JP2005501980A Pending JP2006501692A (ja) 2002-09-27 2003-09-23 リバースエンジニアリングを防ぐための導電性チャネル擬似ブロック方法及びその回路
JP2010029399A Expired - Fee Related JP5185305B2 (ja) 2002-09-27 2010-02-12 リバースエンジニアリングを防ぐための導電性チャネル擬似ブロック処理方法及びその回路

Family Applications After (1)

Application Number Title Priority Date Filing Date
JP2010029399A Expired - Fee Related JP5185305B2 (ja) 2002-09-27 2010-02-12 リバースエンジニアリングを防ぐための導電性チャネル擬似ブロック処理方法及びその回路

Country Status (6)

Country Link
US (3) US7049667B2 (enExample)
JP (2) JP2006501692A (enExample)
AU (1) AU2003278917A1 (enExample)
GB (2) GB2422487B (enExample)
TW (1) TWI251282B (enExample)
WO (1) WO2004030097A1 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010505279A (ja) * 2006-09-28 2010-02-18 エイチアールエル ラボラトリーズ，エルエルシー リバースエンジニアリングに対する改善された抵抗力を有する半導体チップ

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US6815816B1 (en) * 2000-10-25 2004-11-09 Hrl Laboratories, Llc Implanted hidden interconnections in a semiconductor device for preventing reverse engineering
US7049667B2 (en) * 2002-09-27 2006-05-23 Hrl Laboratories, Llc Conductive channel pseudo block process and circuit to inhibit reverse engineering
US6979606B2 (en) 2002-11-22 2005-12-27 Hrl Laboratories, Llc Use of silicon block process step to camouflage a false transistor
AU2003293540A1 (en) * 2002-12-13 2004-07-09 Raytheon Company Integrated circuit modification using well implants
US7242063B1 (en) 2004-06-29 2007-07-10 Hrl Laboratories, Llc Symmetric non-intrusive and covert technique to render a transistor permanently non-operable
US8654634B2 (en) * 2007-05-21 2014-02-18 International Business Machines Corporation Dynamically reassigning virtual lane resources
US7994042B2 (en) 2007-10-26 2011-08-09 International Business Machines Corporation Techniques for impeding reverse engineering
US7825465B2 (en) * 2007-12-13 2010-11-02 Fairchild Semiconductor Corporation Structure and method for forming field effect transistor with low resistance channel region
US8214657B2 (en) * 2008-07-29 2012-07-03 International Business Machines Corporation Resistance sensing for defeating microchip exploitation
US8172140B2 (en) * 2008-07-29 2012-05-08 International Business Machines Corporation Doped implant monitoring for microchip tamper detection
US9003559B2 (en) * 2008-07-29 2015-04-07 International Business Machines Corporation Continuity check monitoring for microchip exploitation detection
US8332659B2 (en) * 2008-07-29 2012-12-11 International Business Machines Corporation Signal quality monitoring to defeat microchip exploitation
US8418091B2 (en) * 2009-02-24 2013-04-09 Syphermedia International, Inc. Method and apparatus for camouflaging a standard cell based integrated circuit
US10691860B2 (en) 2009-02-24 2020-06-23 Rambus Inc. Secure logic locking and configuration with camouflaged programmable micro netlists
US8151235B2 (en) * 2009-02-24 2012-04-03 Syphermedia International, Inc. Camouflaging a standard cell based integrated circuit
US9735781B2 (en) 2009-02-24 2017-08-15 Syphermedia International, Inc. Physically unclonable camouflage structure and methods for fabricating same
US8510700B2 (en) 2009-02-24 2013-08-13 Syphermedia International, Inc. Method and apparatus for camouflaging a standard cell based integrated circuit with micro circuits and post processing
US8111089B2 (en) * 2009-05-28 2012-02-07 Syphermedia International, Inc. Building block for a secure CMOS logic cell library
US9218511B2 (en) 2011-06-07 2015-12-22 Verisiti, Inc. Semiconductor device having features to prevent reverse engineering
US9287879B2 (en) 2011-06-07 2016-03-15 Verisiti, Inc. Semiconductor device having features to prevent reverse engineering
US8975748B1 (en) 2011-06-07 2015-03-10 Secure Silicon Layer, Inc. Semiconductor device having features to prevent reverse engineering
US9437555B2 (en) 2011-06-07 2016-09-06 Verisiti, Inc. Semiconductor device having features to prevent reverse engineering
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US9479176B1 (en) 2013-12-09 2016-10-25 Rambus Inc. Methods and circuits for protecting integrated circuits from reverse engineering
US10262956B2 (en) 2017-02-27 2019-04-16 Cisco Technology, Inc. Timing based camouflage circuit
US11695011B2 (en) 2018-05-02 2023-07-04 Nanyang Technological University Integrated circuit layout cell, integrated circuit layout arrangement, and methods of forming the same
JP6832375B2 (ja) 2019-02-25 2021-02-24 ウィンボンド エレクトロニクス コーポレーション 半導体集積回路をリバースエンジニアリングから保護する方法
US10923596B2 (en) 2019-03-08 2021-02-16 Rambus Inc. Camouflaged FinFET and method for producing same
CN109980014B (zh) * 2019-03-26 2023-04-18 湘潭大学 一种后栅极铁电栅场效应晶体管及其制备方法
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