GB2430800A - Camouflaged circuit structure - Google Patents

Abstract

The spacing between the source/drain and gate electrodes of a non-operable MOSFET is set to a distance equal to a sidewall spacer to increase the similarity between non-operable and operable devices. The device structure inhibits attempts at reverse engineering.

Description

USE OF SILICON BLOCK PROCESS STEP TO C1NOUFLAGE A FALSE

TRANSISTOR

Cross reference to related applications

This application claims the benefit of US Provisional Patent Application 60/428,634 filed November 22, 2002, the contents of which are hereby incorporated herein by reference.

This application is divided from GB 2,422,956 A (GB 0608053.5) to which reference is directed.

Technical Field

The present invention relates to integrated circuits (ICs) and semiconductor devices in general and their methods of manufacture wherein the integrated circuits and semiconductor devices employ camouflaging techniques which make it difficult for the reverse engineer to discern how the semiconductor device functions.

Related art The present invention is related to the following US patents by some of the same inventors as the present inventors: (1) United States Patent Nos. 5,866,933; 5,783,375 and 6,294,816 teach connecting transistors in a CMOS circuit by implanted (and therefore hidden and buried) lines between the transistors. The implanted lines are formed by modifying the p+ and n+ source/drain masks. These implanted interconnections are used to make 3-input AND or OR circuits look substantially identical to the reverse engineer. Also, buried interconnects forcetheieverseengineerto nethelCingreaterdepthtotzytoflgureoutthe.

connectivity between transistors and hence their function.

* (2) United States Patent Nos. 5,783846; 5,930,663 and 6,064,110 teach rnodifing the * 5 source/drain implant masks to provide a gap in the implanted connecting lines between * transistors. The length of the gap being approximately the mininruni feature size ofhe CMOS technology being used. If this gap is "filled" with one kind of implant; thà line conducts; but.if it is "filled" with another kind of implant, the line does not conduct. The intentional gaps are called "channel blocks." The reverse engineer is foifccd to determine connectivity on the basis of resolving the implant type at the minimum feature size of the CMOS process being used.

(3) United States Patent No. 6,117,762 teaches a method and an apparatus for protecting semiconductor integrated circuits from reverse engineering. Semiconductor active areas arc formed on a substrate and a silicide layer is formed ovr at least one active area of the * Semiconductor active areas and over a selected substrate area. The silicide layer connecting the at least one active area with another active area.

Jackground of the Invention The creation of complex integrated circuits and semiconductor devices can be an expensive undertaking because of thà large number of hours of sophisticated engineering talent involved in designing such devices. AdditiQnally, integrated circuits can include read only memories and/or REPROMs into which software, in the form of firmware, is encoded. Further, integrated circuits are often used in applications involving the enciyption of information. Jorder to keep the enciypted information confidential, devices should be protected from being reverse engineered. Thus, there can bó a variety of reasons for protecting integrated circuits and other semiconductor devices from being re'ersed engineered. * In àrder to keep tIle reverse engineer at bay, diffcret techniques are known in the ait to make integrated circuits moredifflcu]t to reverse engineer. One technique is to make the connections between transistors dicult to detennine forcing the reverse engineer to.perforrn a careful analysis of each transistor (in particular, each CMOS transistor pair for CMOS dèvices) and thwarting.attempts to use automat c circuit and pattem recognition techniques in order to reverse engineer an integrated circuit Since integrated circuits can have hundreds of thousands or even millions of Iransistors, forcing the reverse engineer to analyze each transistor carefully in * a device can effectively frustrate the reverse aug near's ability to reverse engineer the device.

successfully.

A conductive layer, such as silicide, is often used during the manufacture of semiconductor devices. In modem CMOS processing, especially with a minhi,uni feature size * below 0.5 jim, a silicide layer is utilized to improve the conductivity of gate, source and drain contacts. In accordance with typical design rules, any active region resulting in a source/drain region iS siicided.

One reverse engineering techniqueinvolves de-layering the completed IC by means of chemical mechanical polishing (CM?) or other etching processes. The etching processes may, under some conditions, reveal the regions betWeen where the suicide was formed on the substrate, and where it was not i.e. the regions defined by the silicide block mask step and by * regions where structures, such as apolysilicon gate, prevent the silicide layer from being deposited onthe substrate. These regions may be revealed becausC, under soni kinds of etches, there is an observable difference in topology due to different etching rates for silicided vs. pure * silicon The revetc engineer, by noting the silicided areas vs. non- silicided areas1, may make reasonable assumptions as to the function of the device. This*inforniation can thenbe stored ito * * a database for automatic classification of other similar devices.

Some methods of protecting against reverse engineering may be susceptible to discovemy.

* under some reverse engineering techniques, such as chemical-mechanical polièbing. (CM?) or 3 **.

* other etching techniques. For example, Figure la depicts a possible topdown view ofa false transistor niadein accordance with US Patent Application No. 091758,792 alter etcbin& During the manufactining of the false transistor, and in accordance with normal design rules, the silicide block mask allows for a silicide layer 15, see Fignre lb. to be placed completely over the active regions 12, 16, and optionally over gate laycr14.Gate layer 14 maybe apolysilicon layer.

During the CM? process, the gate layer 14 would be removed, thereby resulting in the top-down view as shown in Figure la. As shéywn, the suicide layer edge 18 aligns with th gate edge 11, 13, thus the reverse engineer only sees one line along the gateedge 11, 13.

As will be described below, the top-down view of the false transistor is different from a top-down view of a true transistor and as such, the difference may be a signature that the transistor is not a true For functional or tne transistors, as shown iii Figures 2a and 2b, the silicide layer edge 18' is oflet from the polysilicon gate layer 14 due to the presônce of sidewall spacers 19 that are formed acljacenttó gate layer 14. A light doped density (LDD) implant lOIs typically formed alter the formation of the gate layer 14 and before the formation of the sidewall spaters. After sidewallspacers 19 ate fonned, active areas 12, 16 are typically formed ip the substrate. The formation of active areas 12, 16 saturate most of the LDD implant, so that only the portion of the LDD implant 10 that.is under the sidewall spacers 19 effectively remains. A coiductive layer, such as silicide, is typically placed over the active areas 12, 16 and the gate layer 14. The gate layer 14 and sidewall spaceri 19, prevent the silicidà from being deposited upon the bubstrate in those areas. Thus, the artifict edge 18' is spaced from and lies mostly parallel with the edges 11, 13 of the gate layer 14 for a true transistor. Thus, from the examination of the top-down view the reverse engineer may b able to determine that a structure originally placed in the area wasa fact a false transistormeant to confuse the reverse engineer due to the absence of artifact edges 18' lying spaced from and mostly parallel with edges 11, 13 of the polysilicon gate 14. A reverse * engineer could then program computei software to recognize the absence of artifact edges 18' of * the suicide layers lying separate from and being mostly parallel with the edges 11, 13 of the gate.

* layer 14 as indications Of false transistors. One skilled in the art will appreciate that although Figure lb depicts active regions 12, 16. aajacent to the gate region 14 and Figure 2b.depicts LDD implants 10 adjacent to the gate region 14, it is extremely difficult, if not impossible, for the reverse engineer to determine the different d ping levels of the LDL) implant 10 and.the active regions 12,16.

Therefore, a need exists to provide a semiconductor device and a.method of manufacturing semiconductor devices that uses artifact edges to confuse the reverse engineer.

Providing artifact edges that are not indicative of the actual device formed will further confuse the reverse engineer and result in incorrect conclusjong as to the actual composition, and thus function, of the device.

Summary of the Invention

One aspect of this invention is to make reverse, engineering even more difficult and, in particular, to confuse the reverse engincefs study of the artifacts revealed di ring the reverse.

engineezing process by pr viding artifacts that are not indicative of the underlying processing and circuit.features. The result is that the. reverse engineezis given large reason to doubt the validity of typical conclusions. it is beie%red that it will not only be time consuming to reverse.

*engineer a'chi employing the present invention but perhaps impractical, if not impossible.

Another aspect of the present invention is that it does not rely upon modifications ox acklitions to the function of the circuitry that is tà be protected from reverse engineering, nor does it require any additional processing steps or equipment. instead, a highly effective deterreflt to reverse engineering is accomplished.in*a streamlined manner that adds neither processing tinie nor complexity to the basic circuitry. * . - 5.

The Inventors named herein have previously filed Patent Applications and have received * Patents in this general area of.tcchnology, that is relating to the camouflage of integrated circuit devices in Ordi to make it more difficult to reverse engineer them. The present invention can be used hannoniously with the techniques disclosed above in the prior United States Patents to further confuse the reverse engineer.

The present invention might only be used oncein a thousand of instances on the chip in question. Thus, the reverse engineer will have to look very carefully at each transistor or * connection. The reverse engineer will be raced with having to find the proverbial needle in a haystack Another aspect of the present invention is a method of manufacturing a semiconductor device in which a conductive laye block mask is modified resulting in reverse engineering artifacts that are misleading and not indicative of the true structure of the device.

An aspect of thepresent invention is to provide a camouflaged cirenit structurà, comprising:, a gate layer having a first gate layer edge and a second gate layer edge; a first active area disposed adjacent said first gate layer edge; a second active area disposed adjacent sid second gate layer edge; and a conductive layer having a first artifact edge and a second artifact edge, said conductive layer partially formed over said first active area and said second active area; wherein said first artifact edge of said conductive layer is offset from said first gate layer edge, and said second artifact edge of said conductive layer is offsetfrom said second gate layer * edge.

Another aspect of the prcs.ent invention is a method of confusing a reverse engineer comprising the steps of: providing a false semiaonauctor device without sidewall spacers having at least cuie active region; and forming a conductive layer partially over the at least one active region such that an artifact edge of saidconductive layer of said false semiconductor device * * without sidewall spacers mimics an artifact edge of a conductive layer of a true semiconductor * * device having sidewall spacers.

Another aspect of the present invention is a method of camouflaging an integrated circuit structure comprising the steps of forming the integrated circuit structure having a plurality of active areas; and fonning a conductive block layer mask to thereby form artifact edges of a * conductive layer that are located in a same relative locations for nonoperational transistors without sidewall spacers as well as operational transistors with sidewall spacers.

Another aspect of the present invention is a method of protecting an integrated circuit design comprising the steps of modi1ing a silicide block mask used duringthe manufacture of a false transistor such that edges of a silicide layer for the false transistor are placed in substantially the same relative locations as edges of asilicide layer for a tme transistor, and manufacturing said integrated circuit.

Another aspect of the present invention is a circuit structure comprising: a gate layer having a first gate layer edge and a second gate layer edge; a first active area, said first active area being formed during a single processing step, said first active area having a width, said first active area formed adjacent said first gate layer edge; .a. second active area, said second active area being fonncd duriiig a single processing step, said second active area having a width, said second active area formed adjacent said second gate layer edge; a conductive layer having a first artifact edge and a second artifact edge, said conductive layer being formed over said first active area and over said second active area, a width of said conductive layer formed over said first active area being less than said width of said first active area, a width of said qonductive layer formed over said second active area being less than said width of said second active area.

25. . . Another aspect of the present invention is a method of hiding a circuit function comprising the steps of forming at least one active region of a device With a single processing step, said at least one active region having a width; and forming a conductive layer partially over * 7 the at least one active region wherein a width of said conductive.layer is less than the width of the at least one active region.. - * BriefDesciption of the Drawings 5.

Figure-la depicts artifact edges of a suicide layer thatthe reverse engineer could see after * all the metal and oxide layers have been removed from a false transistor, Figure lb depicts a cross-section of a false transistor; Figure 2a depicts prior art artifact edges of a silicide layer that the reverse engineer could see after all the metal andoxide layers have been removed from a true transistor Figure 2b depicts a cross-section of a prior art thie transistor, Figure 3a depicts artifact edges of a silicide layer that the reverse engineer could see after all the metal and oxide layers have been removed from a false transistor in accordance with one embodiment of the present invention; - Figure 3b depicts a cross-section of a false transistor in accordance with one embodiment of the present invention; and Figure 4 depicts an example of a suicide layer block mask to be used in accordance with one embodiment of the present invention. * . -

* * 8- Detailed lescription: . The present invention now will be described more fully hereinafter with reference to the.

accompanying drawings, in which an embodiment of the invention is showlL This invention may be embodied in many different foxms and shçuld not be consthied as limited to the embodiment set forth.herein Many methods of manufacturing semiconductor devices are well known in the art. The following discussion focuses on modiring a conductive layer block yna.qk used during the manufacture of semiconductor devices in order to confuse the reverse engineer. The discussion is not intended to provide all of the semiconductor manuicturing details, which are well known in the art.

rnorder to confuse the reverse engineer, the placement of an artifact edge of a silicide layer that would be seen when a reverse engineer examines devices manufctured with other reveise-engineering-deteclion-preyentjon techniques is changed. In reverse-engineering- detection-prevention techniques, false, or non-operational, transistors are used along with true, or operational, transistors. Some falso transistors arc manufactured without sidewall spacers, see Figure Ib, while cozresponding tru transistors may well have sidewall spacers 19, as shown in Figure 2b. From a top-down view, and through most reversecnginecring techniques, thescfalso transistors look the same as operational transistors. However, under some reverse engineering techniques, such as chemical mechanical polishing (CMP) or other etching processes, the artifact edges of the suicide layer may give away the reverse engineering-detection-prevention technique. As shown inFigure la, for some non-operational transistors, the artifact edges l8of,a sjlicjdclayr 15 coincidewith the edges 11, 13 ofthe gate layer 14. However, with operatipn.

transistors as shown in Figure 2a, the artifact edges) 8' of a silicide layer 15 are offset frOm the edges 11, 13 of the gate layer 14 by the width of sidewall spacers 19.

Figure 3a is a t'opdown view and Figure 3b s.a cross-sectional vinci of a false transistor in accordance with the present invention. Figure 3a depicts artifact edges 18" of a conductive layer 15 that do not coincide with the edges 11, 13 of gate layer 14. A con luctive layer block mask 21, see Figure 4, is preferably modified to prevent the suicide layer 15 from covering the * entireactiveareas 12, l6.Theconductivelayerl5ispa allyformedoverafirstaétivearea 12 and a second active area 16. The result is that the conductive layer 15 has a cross-sectional width 151 that is smaller than the cross-sectional width 121,161 ófthó active areas 12, 16. Thus, when a reverse engineering process, such as CMP or other etching process, is used,. the artifact edges 18" of the conductive layer 15 do not give away the fact, that the transistor is a false transistor.

Instead, the artifact edges 18" are offset by a distance 17, see Figure 3a, fronithe gate layer 14, with distanca 17 having a width that is preferably approximately equivalent to the width of one typical sidewall spacer, as if sidewall spacers were present Therefore, the reverse engineer can no longer rely on the placement of the artifact edges 18 ofco ductive layer 15 to detennine if a transistor is a true transistor or a false transistor.

One skilled in the art will appreciate that the conductive layer blockmask 21 will require * different modifications depending on the feature sIze of the device. The offset distance 17 between the artifact edge 18 of the conductive layer 15 and the edge 11,13 of the gate layer 14 is preferably approximately equal to the width of the sidewall spacers, which varies depending * *on. the feature size of the device. One skilled in the art will appreciate that the difference between the width of the sidewall spacer. 19 and the width of the offset 17 should' be within the manufacturing tolerances for the processused, and thus the offset 17 and the width of the sidewall spacer 19 are approximately equal. For 0.35 pm technology, for example, the sidewall spacer width Is approximately 0.09 pm. For typical CMOS processes, the conductive layer 15 will be silicide while the gate layer 14 will be po]ysilicon.' One skilled in the art will appreciate that regardless of the feature size of the device, the person laying out the masks should plao the artifact edges 18" of the conductive layer 15 for a false transistor in substantially the same relative locations as the artifaàt edges 18' of the conductive layer 15 for a lruelransistor. Thus, the reverse engineer will be unable to use the artifact edges.18 of the conductive layer l5to determine if the transistor is a true transistor or a false transistor.

Additionally, false transistors manufactqted in accordance with the invention are preferably used not to completely disable a multiple transistor circuit, but rather to cause the * circuit to function in an unexpected or non-intuitive manner. ror example, what appears to be an * 5 OR gate to the reverse engineer might really function as an A1l) gate. Alternatively, what appears as.a inverting input might rally be noninverting. The possibilities are endless and.are almost sure to cause the reverse engineer so much grief that he or she would give up as opposed to pressing forward to discover how to revise engineer the integrated circuit device on which thistechthque is utilized.

* Having described the invention in connection with certain preferred embodiments thereo modification will now certainly suggest itself to those skilled in the art. As such, the invention is not to be limited to the disclosed embodiments, except as is specifically required by * the appended claims. * * * * r * 11 )

Claims (18)

1. CLAIMS: 1. A circuit structure comprising: a gate layer having a first

   gate layer edge and a second gate layer edge; a first active area, said first active area being a single area, said first active area having a width, and said first active area being formed immediately adjacent said first gate layer edge; a second active area, said second active area being a single area, said second active area having a width, and said second active area being formed immediately adjacent said second gate layer edge; a conductive layer having a first artifact edge and a second artifact edge, said conductive layer being formed over said first active area and over said second active area, a width of said conductive layer formed over said first active area being less than said width of said first active area, a width of said conductive layer formed over said second active area being less than said width of said second active area to thereby define artifact edges adjacent, but spaced from, the first and second gate layer edges.
2. 2. The circuit structure of claim 1 wherein a difference between the width of said conductive layer and the width of said first active area is approximately equal to a width of a sidewall spacer.
3. 3. The circuit structure of claims 1 or 2 wherein said circuit is nonoperable.
4. 4. A method of hiding a circuit function of a circuit, the method comprising the steps of: forming at least one active region of a device with a single processing step, said at least one active region having a width; and forming a conductive layer partially over the at least one active region wherein a width of said conductive layer is less than the width of the at least one active region so that the conductive layer yields an artifact edge, when subjected to reverse engineering techniques, which is in a conventionally anticipated location for a conventionally operational version of the circuit, but wherein the circuit, due to the width of the at least one active region, functions in an unanticipated fashion. I0
5. 5. The method of claim 4 wherein said device is non- operable.
6. 6. The method of claims 4 or 5 wherein a difference between (5 the width of the at least one active region and the width of the conductive layer is approximately equal to a width of a sidewall spacer.
7. 7. A method of confusing a reverse engineer comprising the steps of: providing a false semiconductor device without sidewall spacers having at least one active region; and forming a conductive layer partially over the at least one active region such that an artifact edge of said conductive layer of said false semiconductor device without sidewall spacers mimics an artifact edge of a conductive layer of a semiconductor device having sidewall spacers.
8. 8. The method of claim 7 wherein the conductive layer is a suicide layer.
9. 9. The method of claims 7 or 8 wherein the false semiconductor device is a false transistor having a polysilicon gate and wherein the step of forming a conductive layer comprises the step of modifying a conductive layer block mask such that the artifact edge of said conductive layer is offset from an edge of said polysilicon gate.
10. 10. The method of claim 9 wherein the offset between the artifact edge of said conductive layer arid said edge of said polysilicon gate is approximately equal to a width of a sidewall spacer.
11. 11. A method of camouflaging a non-operational circuit structure comprising the steps of: forming the non-operational circuit structure having a plurality of active areas; and forming a conductive block layer mask to thereby form an artifact edge of a conductive layer that is located in a same relative location for the non-operational circuit structure without sidewall spacers as an operational circuit structure with sidewall spacers.
12. 12. The method according to claim 11 wherein the conductive layer is a silicide layer.
13. 13. A method of protecting an integrated circuit design comprising: modifying a suicide block mask used during the manufacture of a false transistor such that edges of a silicide layer for the false transistor are placed in substantially the same relative locations as edges of a suicide layer for a true transistor; and manufacturing said integrated circuit.
14. 14. A camouflaged circuit structure for an integrated circuit, the circuit structure comprising: a gate layer having a first gate layer edge and a second gate layer edge; a first active area disposed adjacent said first gate layer edge; a second active area disposed adjacent said second gate layer edge; and a conductive layer having a first artifact edge and a second artifact edge, said conductive layer partially formed over said first active area and said second active area; wherein said first artifact edge of said conductive layer and said first gate layer edge define a first offset, and said second artifact edge of said conductive layer and said second gate layer edge define a second offset, wherein said first offset and said second offset are not defined by a sidewall spacer.
15. 15. The camouflaged circuit structure of claim 14 wherein said first active area is a source region and said second active area is a drain region.
16. 16. The camouflaged circuit structure of claim 14 wherein said first offset and said second offset each have a width, said width being approximately equal to a width of a typical sidewall spacer for the integrated circuit.
17. 17. The camouflaged circuit structure of claim 14 wherein said conductive layer is a suicide layer and said gate layer is a polysilicon layer.
18. 18. The camouflaged circuit structure of any one of claims 14 to 17 wherein said camouflaged circuit is a false transistor.