JP2006080314A - 結合基板の製造方法 - Google Patents

結合基板の製造方法 Download PDF

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Publication number
JP2006080314A
JP2006080314A JP2004262966A JP2004262966A JP2006080314A JP 2006080314 A JP2006080314 A JP 2006080314A JP 2004262966 A JP2004262966 A JP 2004262966A JP 2004262966 A JP2004262966 A JP 2004262966A JP 2006080314 A JP2006080314 A JP 2006080314A
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JP
Japan
Prior art keywords
substrate
bonding
bonded
manufacturing
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2004262966A
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English (en)
Japanese (ja)
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JP2006080314A5 (enExample
Inventor
Tadashi Ahei
忠司 阿閉
Takaharu Moriwaki
隆治 森脇
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP2004262966A priority Critical patent/JP2006080314A/ja
Priority to US11/222,903 priority patent/US7642112B2/en
Publication of JP2006080314A publication Critical patent/JP2006080314A/ja
Publication of JP2006080314A5 publication Critical patent/JP2006080314A5/ja
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76259—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along a porous layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02043—Cleaning before device manufacture, i.e. Begin-Of-Line process
    • H01L21/02052—Wet cleaning only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Element Separation (AREA)
  • Pressure Welding/Diffusion-Bonding (AREA)
JP2004262966A 2004-09-09 2004-09-09 結合基板の製造方法 Withdrawn JP2006080314A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2004262966A JP2006080314A (ja) 2004-09-09 2004-09-09 結合基板の製造方法
US11/222,903 US7642112B2 (en) 2004-09-09 2005-09-09 Method of manufacturing bonded substrate stack

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2004262966A JP2006080314A (ja) 2004-09-09 2004-09-09 結合基板の製造方法

Publications (2)

Publication Number Publication Date
JP2006080314A true JP2006080314A (ja) 2006-03-23
JP2006080314A5 JP2006080314A5 (enExample) 2007-10-11

Family

ID=36126083

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2004262966A Withdrawn JP2006080314A (ja) 2004-09-09 2004-09-09 結合基板の製造方法

Country Status (2)

Country Link
US (1) US7642112B2 (enExample)
JP (1) JP2006080314A (enExample)

Cited By (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008177531A (ja) * 2006-12-18 2008-07-31 Soi Tec Silicon On Insulator Technologies ダブルプラズマｕｔｂｏｘ
JP2008214491A (ja) * 2007-03-05 2008-09-18 Ulvac Japan Ltd 表面処理方法
JP2008227207A (ja) * 2007-03-14 2008-09-25 Sumco Corp 貼り合わせウェーハの製造方法
JP2009004741A (ja) * 2007-05-18 2009-01-08 Semiconductor Energy Lab Co Ltd Ｓｏｉ基板の作製方法、及び半導体装置の作製方法
JP2009517855A (ja) * 2005-11-28 2009-04-30 エス． オー． アイ． テック シリコン オン インシュレーター テクノロジーズ 分子接合による結合のためのプロセスおよび装置
JP2009135350A (ja) * 2007-12-03 2009-06-18 Semiconductor Energy Lab Co Ltd 半導体装置の作製方法
JP2009253184A (ja) * 2008-04-10 2009-10-29 Shin Etsu Chem Co Ltd 貼り合わせ基板の製造方法
JP2011187716A (ja) * 2010-03-09 2011-09-22 Tokyo Electron Ltd 接合システム、接合方法、プログラム及びコンピュータ記憶媒体
JP2012069927A (ja) * 2010-08-23 2012-04-05 Semiconductor Energy Lab Co Ltd Ｓｏｉ基板の作製方法
CN103460343A (zh) * 2011-04-08 2013-12-18 Ev集团E·索尔纳有限责任公司 晶片的永久粘合方法
JP2014510418A (ja) * 2011-04-08 2014-04-24 エーファウ・グループ・エー・タルナー・ゲーエムベーハー ウェーハを永久的に結合する方法
JP2014090186A (ja) * 2013-12-04 2014-05-15 Semiconductor Energy Lab Co Ltd 半導体装置の作製方法
JP2015041744A (ja) * 2013-08-23 2015-03-02 東京エレクトロン株式会社 接合方法および接合システム
JP2015211130A (ja) * 2014-04-25 2015-11-24 ボンドテック株式会社 基板接合装置および基板接合方法
JP2017508280A (ja) * 2014-02-07 2017-03-23 サンエディソン・セミコンダクター・リミテッドＳｕｎＥｄｉｓｏｎ Ｓｅｍｉｃｏｎｄｕｃｔｏｒ Ｌｉｍｉｔｅｄ 層状半導体構造体の製造方法
WO2018116746A1 (ja) * 2016-12-19 2018-06-28 信越半導体株式会社 Ｓｏｉウェーハの製造方法
US10083933B2 (en) 2011-01-25 2018-09-25 Ev Group E. Thallner Gmbh Method for permanent bonding of wafers
US10825793B2 (en) 2011-04-08 2020-11-03 Ev Group E. Thallner Gmbh Method for permanently bonding wafers
JP2022034744A (ja) * 2020-08-19 2022-03-04 住友金属鉱山株式会社 基板接合装置
WO2022070835A1 (ja) * 2020-09-30 2022-04-07 ボンドテック株式会社 基板接合方法および基板接合システム

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US7361574B1 (en) * 2006-11-17 2008-04-22 Sharp Laboratories Of America, Inc Single-crystal silicon-on-glass from film transfer
JP5220335B2 (ja) * 2007-04-11 2013-06-26 信越化学工業株式会社 Ｓｏｉ基板の製造方法
TWI492275B (zh) * 2008-04-10 2015-07-11 Shinetsu Chemical Co The method of manufacturing the bonded substrate
KR101629193B1 (ko) * 2008-06-26 2016-06-10 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Ｓｏｉ 기판의 제작 방법
US8481411B2 (en) * 2009-06-10 2013-07-09 Seoul Opto Device Co., Ltd. Method of manufacturing a semiconductor substrate having a cavity
WO2010143778A1 (ko) * 2009-06-10 2010-12-16 서울옵토디바이스주식회사 반도체 기판, 그 제조 방법, 반도체 소자 및 그 제조 방법
US8860183B2 (en) * 2009-06-10 2014-10-14 Seoul Viosys Co., Ltd. Semiconductor substrate, semiconductor device, and manufacturing methods thereof
CN104795313B (zh) 2009-08-26 2017-12-08 首尔伟傲世有限公司 制造半导体基底的方法和制造发光装置的方法
JP5570838B2 (ja) * 2010-02-10 2014-08-13 ソウル バイオシス カンパニー リミテッド 半導体基板、その製造方法、半導体デバイス及びその製造方法
JP6981356B2 (ja) * 2018-04-24 2021-12-15 東京エレクトロン株式会社 成膜装置及び成膜方法
US20230207397A1 (en) * 2021-12-29 2023-06-29 Tokyo Electron Limited Transistor stacking by wafer bonding

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JPH03294934A (ja) 1990-04-13 1991-12-26 Nippon Telegr & Teleph Corp <Ntt> 高級プログラム言語用デバッガ
JP2608351B2 (ja) 1990-08-03 1997-05-07 キヤノン株式会社 半導体部材及び半導体部材の製造方法
US5451547A (en) * 1991-08-26 1995-09-19 Nippondenso Co., Ltd. Method of manufacturing semiconductor substrate
FR2681472B1 (fr) * 1991-09-18 1993-10-29 Commissariat Energie Atomique Procede de fabrication de films minces de materiau semiconducteur.
KR0137125B1 (ko) * 1992-11-16 1998-06-15 모리시타 요이찌 광도파로소자와 그 제조방법
US5453652A (en) * 1992-12-17 1995-09-26 Matsushita Electric Industrial Co., Ltd. Surface acoustic wave device with interdigital transducers formed on a holding substrate thereof and a method of producing the same
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JP3294934B2 (ja) 1994-03-11 2002-06-24 キヤノン株式会社 半導体基板の作製方法及び半導体基板
US5932048A (en) * 1995-04-06 1999-08-03 Komatsu Electronic Metals Co., Ltd. Method of fabricating direct-bonded semiconductor wafers
JPH09331049A (ja) * 1996-04-08 1997-12-22 Canon Inc 貼り合わせｓｏｉ基板の作製方法及びｓｏｉ基板
TW507106B (en) * 1998-03-11 2002-10-21 Matsushita Electric Industrial Co Ltd Method for producing an alignment chemisorption monomolecular film
US6881644B2 (en) * 1999-04-21 2005-04-19 Silicon Genesis Corporation Smoothing method for cleaved films made using a release layer
TW502458B (en) * 1999-06-09 2002-09-11 Toshiba Corp Bonding type semiconductor substrate, semiconductor light emission element and manufacturing method thereof
US6902987B1 (en) * 2000-02-16 2005-06-07 Ziptronix, Inc. Method for low temperature bonding and bonded structure
JP4628580B2 (ja) 2001-04-18 2011-02-09 信越半導体株式会社 貼り合せ基板の製造方法
JP2002343565A (ja) * 2001-05-18 2002-11-29 Sharp Corp 有機ｌｅｄ表示パネルの製造方法、その方法により製造された有機ｌｅｄ表示パネル、並びに、その方法に用いられるベースフィルム及び基板
CN1434493A (zh) * 2002-01-23 2003-08-06 联华电子股份有限公司 自生长疏水性纳米分子有机防扩散膜及其制备方法
JP4016701B2 (ja) 2002-04-18 2007-12-05 信越半導体株式会社 貼り合せ基板の製造方法
JP4219660B2 (ja) * 2002-11-18 2009-02-04 信越化学工業株式会社 ウエハダイシング・ダイボンドシート
US6852652B1 (en) * 2003-09-29 2005-02-08 Sharp Laboratories Of America, Inc. Method of making relaxed silicon-germanium on glass via layer transfer

Cited By (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009517855A (ja) * 2005-11-28 2009-04-30 エス． オー． アイ． テック シリコン オン インシュレーター テクノロジーズ 分子接合による結合のためのプロセスおよび装置
JP2012238873A (ja) * 2005-11-28 2012-12-06 Soytec 分子接合による結合のためのプロセスおよび装置
JP2008177531A (ja) * 2006-12-18 2008-07-31 Soi Tec Silicon On Insulator Technologies ダブルプラズマｕｔｂｏｘ
JP2008214491A (ja) * 2007-03-05 2008-09-18 Ulvac Japan Ltd 表面処理方法
US8802540B2 (en) 2007-03-14 2014-08-12 Sumco Corporation Method of manufacturing bonded wafer
JP2008227207A (ja) * 2007-03-14 2008-09-25 Sumco Corp 貼り合わせウェーハの製造方法
JP2009004741A (ja) * 2007-05-18 2009-01-08 Semiconductor Energy Lab Co Ltd Ｓｏｉ基板の作製方法、及び半導体装置の作製方法
US9059247B2 (en) 2007-05-18 2015-06-16 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing SOI substrate and method for manufacturing semiconductor device
JP2009135350A (ja) * 2007-12-03 2009-06-18 Semiconductor Energy Lab Co Ltd 半導体装置の作製方法
JP2009253184A (ja) * 2008-04-10 2009-10-29 Shin Etsu Chem Co Ltd 貼り合わせ基板の製造方法
JP2011187716A (ja) * 2010-03-09 2011-09-22 Tokyo Electron Ltd 接合システム、接合方法、プログラム及びコンピュータ記憶媒体
JP2012069927A (ja) * 2010-08-23 2012-04-05 Semiconductor Energy Lab Co Ltd Ｓｏｉ基板の作製方法
US10083933B2 (en) 2011-01-25 2018-09-25 Ev Group E. Thallner Gmbh Method for permanent bonding of wafers
JP2014516469A (ja) * 2011-04-08 2014-07-10 エーファウ・グループ・エー・タルナー・ゲーエムベーハー ウェーハを永久的に結合する方法
CN103460343A (zh) * 2011-04-08 2013-12-18 Ev集团E·索尔纳有限责任公司 晶片的永久粘合方法
JP2014510418A (ja) * 2011-04-08 2014-04-24 エーファウ・グループ・エー・タルナー・ゲーエムベーハー ウェーハを永久的に結合する方法
US10825793B2 (en) 2011-04-08 2020-11-03 Ev Group E. Thallner Gmbh Method for permanently bonding wafers
JP2015041744A (ja) * 2013-08-23 2015-03-02 東京エレクトロン株式会社 接合方法および接合システム
JP2014090186A (ja) * 2013-12-04 2014-05-15 Semiconductor Energy Lab Co Ltd 半導体装置の作製方法
JP2017508280A (ja) * 2014-02-07 2017-03-23 サンエディソン・セミコンダクター・リミテッドＳｕｎＥｄｉｓｏｎ Ｓｅｍｉｃｏｎｄｕｃｔｏｒ Ｌｉｍｉｔｅｄ 層状半導体構造体の製造方法
JP2015211130A (ja) * 2014-04-25 2015-11-24 ボンドテック株式会社 基板接合装置および基板接合方法
WO2018116746A1 (ja) * 2016-12-19 2018-06-28 信越半導体株式会社 Ｓｏｉウェーハの製造方法
CN110024080A (zh) * 2016-12-19 2019-07-16 信越半导体株式会社 Soi晶圆的制造方法
US10763157B2 (en) 2016-12-19 2020-09-01 Shin-Etsu Handotai Co., Ltd. Method for manufacturing SOI wafer
JP2018101663A (ja) * 2016-12-19 2018-06-28 信越半導体株式会社 Ｓｏｉウェーハの製造方法
CN110024080B (zh) * 2016-12-19 2023-05-02 信越半导体株式会社 Soi晶圆的制造方法
JP2022034744A (ja) * 2020-08-19 2022-03-04 住友金属鉱山株式会社 基板接合装置
JP7512761B2 (ja) 2020-08-19 2024-07-09 住友金属鉱山株式会社 基板接合装置
WO2022070835A1 (ja) * 2020-09-30 2022-04-07 ボンドテック株式会社 基板接合方法および基板接合システム
US12409644B2 (en) 2020-09-30 2025-09-09 Tadatomo Suga Substrate bonding method and substrate bonding system

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US20060073644A1 (en) 2006-04-06
US7642112B2 (en) 2010-01-05

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