JP5622988B2 - 半導体基板の作製方法 - Google Patents
半導体基板の作製方法 Download PDFInfo
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- JP5622988B2 JP5622988B2 JP2010211811A JP2010211811A JP5622988B2 JP 5622988 B2 JP5622988 B2 JP 5622988B2 JP 2010211811 A JP2010211811 A JP 2010211811A JP 2010211811 A JP2010211811 A JP 2010211811A JP 5622988 B2 JP5622988 B2 JP 5622988B2
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- semiconductor
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- semiconductor substrate
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- etching
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Classifications
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02032—Preparing bulk and homogeneous wafers by reclaiming or re-processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02008—Multistep processes
- H01L21/0201—Specific process step
- H01L21/02024—Mirror polishing
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- H01—ELECTRIC ELEMENTS
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30604—Chemical etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30604—Chemical etching
- H01L21/30608—Anisotropic liquid etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
- H01L21/3247—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering for altering the shape, e.g. smoothing the surface
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
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Description
本実施の形態では、半導体基板の再生方法について、図1、図2を用いて説明する。
本実施の形態に係るSOI基板の製造方法は、ボンド基板である半導体基板から分離させた半導体層をベース基板に接合してSOI基板を製造する。そして、半導体層が分離された後の半導体基板に再生処理を施して、ボンド基板として再利用する。以下、図2〜図5と図6のSOI基板作製工程図を参照して、本実施の形態に係るSOI基板の製造方法の一例について説明する。
O2+hν1(λ1nm)→O(3P)+O(3P) (1)
O(3P)+O2→O3 (2)
O3+hν2(λ2nm)→O(1D)+O2 (3)
O2+hν3(λ3nm)→O(1D)+O(3P) (4)
O(3P)+O2→O3 (5)
O3+hν3(λ3nm)→O(1D)+O2 (6)
また、損傷半導体領域を選択的に除去した後に水素を含む雰囲気中で熱処理を行うことにより、良好な平坦性を有する再生半導体基板を得ることができる。
本実施の形態では、耐熱性の高いシリコン基板等をベース基板として用いてSOI基板を作製する場合について説明する。なお、本実施の形態において示す方法は、多くの部分で先の実施の形態と共通している。よって、本実施の形態では、主に相違点について説明することとする。図面については、先の実施の形態と共通であるため、ここでは特に示さない。
3Si+4HNO3 → 3SiO2+2H2O+4NO (1)
SiO2+6HF → 2H++〔SiF6〕2−+2H2O (2)
102 絶縁層
104 脆化領域
120 ベース基板
121 半導体基板
122 絶縁層
123 絶縁層
124 半導体層
125 半導体領域
126 段差部
127 半導体領域
128 段差部
129 半導体領域
130 半導体基板
132 再生半導体基板
133 半導体領域
134 ブリスター
135 領域
251 半導体層
252 半導体層
254 絶縁層
255 ゲート電極
256 ゲート電極
257 低濃度不純物領域
258 チャネル形成領域
259 高濃度不純物領域
260 チャネル形成領域
261 サイドウォール絶縁層
262 サイドウォール絶縁層
267 高濃度不純物領域
268 絶縁層
269 層間絶縁層
270 配線
280 トランジスタ
281 トランジスタ
301 段差部
302 中央部
401 シリコン基板
402 熱酸化膜
403 脆化領域
404 亀裂までの深さ
Claims (3)
- 周縁部に第1の損傷半導体領域と絶縁層とを含む段差部を有し、かつ、前記段差部に囲まれた領域に、前記第1の損傷半導体領域よりも薄い第2の損傷半導体領域を有する半導体基板に対し、
前記絶縁層を除去する第1のエッチング処理と、
前記半導体基板に含まれる半導体材料を酸化する物質、前記酸化された半導体材料を溶解する物質、並びに前記半導体材料の酸化の速度及び前記酸化された半導体材料の溶解の速度を制御する物質、を含む混合液を用いて、未損傷の半導体領域に対して前記第1の損傷半導体領域及び前記第2の損傷半導体領域を選択的に除去する第2のエッチング処理と、
前記第2のエッチング処理の後に、水素を含む雰囲気下で加熱する処理と、
を行い、
前記第2のエッチング処理を、前記段差部に囲まれた領域に対する前記周縁部のエッチング選択比が2未満に低下した後に停止させることを特徴とする半導体基板の作製方法。 - 請求項1において、
前記第2のエッチング処理により、前記段差部の接平面と前記半導体基板の裏面とのなす角が0.5°以下の領域を少なくとも除去することを特徴とする半導体基板の作製方法。 - 請求項1または2において、
前記半導体基板に含まれる半導体材料を酸化する物質として硝酸を用い、
前記酸化された半導体材料を溶解する物質としてフッ酸を用い、
前記半導体材料の酸化の速度及び前記酸化された半導体材料の溶解の速度を制御する物質として酢酸を用いることを特徴とする半導体基板の作製方法。
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SG (1) | SG178179A1 (ja) |
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-
2010
- 2010-09-13 SG SG2012006623A patent/SG178179A1/en unknown
- 2010-09-13 KR KR1020127011943A patent/KR101731809B1/ko active IP Right Grant
- 2010-09-13 WO PCT/JP2010/066123 patent/WO2011043178A1/en active Application Filing
- 2010-09-16 TW TW099131476A patent/TWI525682B/zh not_active IP Right Cessation
- 2010-09-22 JP JP2010211811A patent/JP5622988B2/ja not_active Expired - Fee Related
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SG178179A1 (en) | 2012-03-29 |
WO2011043178A1 (en) | 2011-04-14 |
KR20120091193A (ko) | 2012-08-17 |
TWI525682B (zh) | 2016-03-11 |
US20110086492A1 (en) | 2011-04-14 |
TW201126590A (en) | 2011-08-01 |
JP2011100977A (ja) | 2011-05-19 |
US8288245B2 (en) | 2012-10-16 |
KR101731809B1 (ko) | 2017-05-02 |
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