FR2858875B1 - Procede de realisation de couches minces de materiau semi-conducteur a partir d'une plaquette donneuse - Google Patents

Procede de realisation de couches minces de materiau semi-conducteur a partir d'une plaquette donneuse

Info

Publication number
FR2858875B1
FR2858875B1 FR0309885A FR0309885A FR2858875B1 FR 2858875 B1 FR2858875 B1 FR 2858875B1 FR 0309885 A FR0309885 A FR 0309885A FR 0309885 A FR0309885 A FR 0309885A FR 2858875 B1 FR2858875 B1 FR 2858875B1
Authority
FR
France
Prior art keywords
semiconductor material
thin layers
donor wafer
making thin
making
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
FR0309885A
Other languages
English (en)
Other versions
FR2858875A1 (fr
Inventor
Christophe Maleville
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Original Assignee
Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to FR0309885A priority Critical patent/FR2858875B1/fr
Application filed by Soitec SA filed Critical Soitec SA
Priority to CNB2004800230633A priority patent/CN100440478C/zh
Priority to EP04769359A priority patent/EP1654758A1/fr
Priority to JP2006523083A priority patent/JP4855254B2/ja
Priority to KR1020067002479A priority patent/KR100882380B1/ko
Priority to PCT/IB2004/002969 priority patent/WO2005015631A1/fr
Publication of FR2858875A1 publication Critical patent/FR2858875A1/fr
Priority to US11/084,748 priority patent/US7297611B2/en
Application granted granted Critical
Publication of FR2858875B1 publication Critical patent/FR2858875B1/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • H01L21/02032—Preparing bulk and homogeneous wafers by reclaiming or re-processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76259—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along a porous layer
FR0309885A 2003-08-12 2003-08-12 Procede de realisation de couches minces de materiau semi-conducteur a partir d'une plaquette donneuse Expired - Lifetime FR2858875B1 (fr)

Priority Applications (7)

Application Number Priority Date Filing Date Title
FR0309885A FR2858875B1 (fr) 2003-08-12 2003-08-12 Procede de realisation de couches minces de materiau semi-conducteur a partir d'une plaquette donneuse
EP04769359A EP1654758A1 (fr) 2003-08-12 2004-08-11 Procede de production de couches minces d'un materiau semi-conducteur a partir d'une tranche du type donneur a double face
JP2006523083A JP4855254B2 (ja) 2003-08-12 2004-08-11 両面を有するドナーウェハから半導体材料の薄層を形成するための方法
KR1020067002479A KR100882380B1 (ko) 2003-08-12 2004-08-11 도너웨이퍼 양면으로부터의 반도체 재료 박막 제조방법 및 이에 의한 반도체-온-절연체 구조체
CNB2004800230633A CN100440478C (zh) 2003-08-12 2004-08-11 由双面施予晶片生成半导体材料薄层的方法
PCT/IB2004/002969 WO2005015631A1 (fr) 2003-08-12 2004-08-11 Procede de production de couches minces d'un materiau semi-conducteur a partir d'une tranche du type donneur a double face
US11/084,748 US7297611B2 (en) 2003-08-12 2005-03-21 Method for producing thin layers of semiconductor material from a donor wafer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0309885A FR2858875B1 (fr) 2003-08-12 2003-08-12 Procede de realisation de couches minces de materiau semi-conducteur a partir d'une plaquette donneuse

Publications (2)

Publication Number Publication Date
FR2858875A1 FR2858875A1 (fr) 2005-02-18
FR2858875B1 true FR2858875B1 (fr) 2006-02-10

Family

ID=34112741

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0309885A Expired - Lifetime FR2858875B1 (fr) 2003-08-12 2003-08-12 Procede de realisation de couches minces de materiau semi-conducteur a partir d'une plaquette donneuse

Country Status (7)

Country Link
US (1) US7297611B2 (fr)
EP (1) EP1654758A1 (fr)
JP (1) JP4855254B2 (fr)
KR (1) KR100882380B1 (fr)
CN (1) CN100440478C (fr)
FR (1) FR2858875B1 (fr)
WO (1) WO2005015631A1 (fr)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090325362A1 (en) * 2003-01-07 2009-12-31 Nabil Chhaimi Method of recycling an epitaxied donor wafer
EP1588415B1 (fr) * 2003-01-07 2012-11-28 Soitec Recyclage par des moyens mecaniques d'une plaquette comprenant une structure multicouche apres separation d'une couche mince de celle-ci
US20070148917A1 (en) * 2005-12-22 2007-06-28 Sumco Corporation Process for Regeneration of a Layer Transferred Wafer and Regenerated Layer Transferred Wafer
KR100839355B1 (ko) * 2006-11-28 2008-06-19 삼성전자주식회사 기판의 재생 방법
FR2929758B1 (fr) * 2008-04-07 2011-02-11 Commissariat Energie Atomique Procede de transfert a l'aide d'un substrat ferroelectrique
US20100167454A1 (en) * 2008-12-31 2010-07-01 Twin Creeks Technologies, Inc. Double-sided donor for preparing a pair of thin laminae
US7927975B2 (en) 2009-02-04 2011-04-19 Micron Technology, Inc. Semiconductor material manufacture
US8198172B2 (en) * 2009-02-25 2012-06-12 Micron Technology, Inc. Methods of forming integrated circuits using donor and acceptor substrates
US8871109B2 (en) * 2009-04-28 2014-10-28 Gtat Corporation Method for preparing a donor surface for reuse
US8318588B2 (en) * 2009-08-25 2012-11-27 Semiconductor Energy Laboratory Co., Ltd. Method for reprocessing semiconductor substrate, method for manufacturing reprocessed semiconductor substrate, and method for manufacturing SOI substrate
WO2011043178A1 (fr) 2009-10-09 2011-04-14 Semiconductor Energy Laboratory Co., Ltd. Procédé de retraitement de substrat semi-conducteur, procédé de fabrication de substrat semi-conducteur retraité et procédé de fabrication de substrat de silicium sur isolant
US8367517B2 (en) * 2010-01-26 2013-02-05 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing SOI substrate
KR20120040791A (ko) * 2010-10-20 2012-04-30 삼성엘이디 주식회사 웨이퍼 재생 방법
US9123529B2 (en) 2011-06-21 2015-09-01 Semiconductor Energy Laboratory Co., Ltd. Method for reprocessing semiconductor substrate, method for manufacturing reprocessed semiconductor substrate, and method for manufacturing SOI substrate
JP5417399B2 (ja) * 2011-09-15 2014-02-12 信越化学工業株式会社 複合ウェーハの製造方法
US9808891B2 (en) * 2014-01-16 2017-11-07 Taiwan Semiconductor Manufacturing Co., Ltd. Tool and method of reflow
DE102015003193A1 (de) * 2015-03-12 2016-09-15 Siltectra Gmbh Vorrichtung und Verfahren zum kontinuierlichen Behandeln eines Festkörpers mittels Laserstrahlen
US20180033609A1 (en) * 2016-07-28 2018-02-01 QMAT, Inc. Removal of non-cleaved/non-transferred material from donor substrate
FR3074608B1 (fr) * 2017-12-05 2019-12-06 Soitec Procede de preparation d'un residu de substrat donneur, substrat obtenu a l'issu de ce procede, et utilisation d'un tel susbtrat

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2681472B1 (fr) * 1991-09-18 1993-10-29 Commissariat Energie Atomique Procede de fabrication de films minces de materiau semiconducteur.
JP3257580B2 (ja) * 1994-03-10 2002-02-18 キヤノン株式会社 半導体基板の作製方法
CA2233096C (fr) * 1997-03-26 2003-01-07 Canon Kabushiki Kaisha Substrat et methode de production
JPH11121310A (ja) * 1997-10-09 1999-04-30 Denso Corp 半導体基板の製造方法
JP3697106B2 (ja) * 1998-05-15 2005-09-21 キヤノン株式会社 半導体基板の作製方法及び半導体薄膜の作製方法
EP1273035B1 (fr) * 2000-04-14 2012-09-12 Soitec Procede pour la decoupe d'au moins une couche mince dans un substrat ou lingot, notamment en materiau(x) semi-conducteur(s)
US6566158B2 (en) * 2001-08-17 2003-05-20 Rosemount Aerospace Inc. Method of preparing a semiconductor using ion implantation in a SiC layer
FR2834123B1 (fr) * 2001-12-21 2005-02-04 Soitec Silicon On Insulator Procede de report de couches minces semi-conductrices et procede d'obtention d'une plaquette donneuse pour un tel procede de report

Also Published As

Publication number Publication date
JP4855254B2 (ja) 2012-01-18
US20050164471A1 (en) 2005-07-28
WO2005015631A1 (fr) 2005-02-17
EP1654758A1 (fr) 2006-05-10
US7297611B2 (en) 2007-11-20
JP2007502533A (ja) 2007-02-08
FR2858875A1 (fr) 2005-02-18
CN100440478C (zh) 2008-12-03
CN1836320A (zh) 2006-09-20
KR100882380B1 (ko) 2009-02-05
KR20060039016A (ko) 2006-05-04

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