FR2872343B1 - Substrat semi-conducteur et son procede de preparation - Google Patents

Substrat semi-conducteur et son procede de preparation

Info

Publication number
FR2872343B1
FR2872343B1 FR0506261A FR0506261A FR2872343B1 FR 2872343 B1 FR2872343 B1 FR 2872343B1 FR 0506261 A FR0506261 A FR 0506261A FR 0506261 A FR0506261 A FR 0506261A FR 2872343 B1 FR2872343 B1 FR 2872343B1
Authority
FR
France
Prior art keywords
preparing
same
semiconductor substrate
semiconductor
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
FR0506261A
Other languages
English (en)
Other versions
FR2872343A1 (fr
Inventor
Dirk Dantz
Andreas Huber
Reinhold Wahlich
Brian Murphy
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siltronic AG
Original Assignee
Siltronic AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siltronic AG filed Critical Siltronic AG
Publication of FR2872343A1 publication Critical patent/FR2872343A1/fr
Application granted granted Critical
Publication of FR2872343B1 publication Critical patent/FR2872343B1/fr
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/185—Joining of semiconductor bodies for junction formation
    • H01L21/187—Joining of semiconductor bodies for junction formation by direct bonding
    • E—FIXED CONSTRUCTIONS
    • E01—CONSTRUCTION OF ROADS, RAILWAYS, OR BRIDGES
    • E01D—CONSTRUCTION OF BRIDGES, ELEVATED ROADWAYS OR VIADUCTS; ASSEMBLY OF BRIDGES
    • E01D19/00—Structural or constructional details of bridges
    • E01D19/04—Bearings; Hinges
    • E01D19/041—Elastomeric bearings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
FR0506261A 2004-06-24 2005-06-21 Substrat semi-conducteur et son procede de preparation Active FR2872343B1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE102004030612A DE102004030612B3 (de) 2004-06-24 2004-06-24 Halbleitersubstrat und Verfahren zu dessen Herstellung

Publications (2)

Publication Number Publication Date
FR2872343A1 FR2872343A1 (fr) 2005-12-30
FR2872343B1 true FR2872343B1 (fr) 2011-02-25

Family

ID=35506430

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0506261A Active FR2872343B1 (fr) 2004-06-24 2005-06-21 Substrat semi-conducteur et son procede de preparation

Country Status (6)

Country Link
US (2) US7491966B2 (fr)
JP (1) JP4465306B2 (fr)
KR (1) KR100745598B1 (fr)
CN (1) CN100358128C (fr)
DE (1) DE102004030612B3 (fr)
FR (1) FR2872343B1 (fr)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10326578B4 (de) * 2003-06-12 2006-01-19 Siltronic Ag Verfahren zur Herstellung einer SOI-Scheibe
FR2887074A1 (fr) * 2005-06-09 2006-12-15 St Microelectronics Crolles 2 Formation d'un masque sur un circuit electronique integre
FR2887075B1 (fr) * 2005-06-09 2007-10-12 St Microelectronics Crolles 2 Realisation de deux elements superposes au sein d'un circuit electronique integre
US7456057B2 (en) * 2005-12-31 2008-11-25 Corning Incorporated Germanium on glass and glass-ceramic structures
US8101501B2 (en) * 2007-10-10 2012-01-24 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing semiconductor device
KR100962610B1 (ko) 2008-03-17 2010-06-11 주식회사 티지솔라 열처리 방법
US11181688B2 (en) 2009-10-13 2021-11-23 Skorpios Technologies, Inc. Integration of an unprocessed, direct-bandgap chip into a silicon photonic device
US8630326B2 (en) 2009-10-13 2014-01-14 Skorpios Technologies, Inc. Method and system of heterogeneous substrate bonding for photonic integration
US9923105B2 (en) 2013-10-09 2018-03-20 Skorpios Technologies, Inc. Processing of a direct-bandgap chip after bonding to a silicon photonic device
US8735191B2 (en) * 2012-01-04 2014-05-27 Skorpios Technologies, Inc. Method and system for template assisted wafer bonding using pedestals
US9922967B2 (en) 2010-12-08 2018-03-20 Skorpios Technologies, Inc. Multilevel template assisted wafer bonding
US8222084B2 (en) 2010-12-08 2012-07-17 Skorpios Technologies, Inc. Method and system for template assisted wafer bonding
CN105336748B (zh) 2012-01-18 2019-05-03 斯考皮欧技术有限公司 Cmos电子器件与光子器件的垂直集成
JP2015516672A (ja) * 2012-02-26 2015-06-11 ソレクセル、インコーポレイテッド レーザ分割及び装置層移設のためのシステム及び方法
US9406551B2 (en) * 2012-09-27 2016-08-02 Infineon Technologies Austria Ag Method for manufacturing a semiconductor substrate, and method for manufacturing semiconductor devices integrated in a semiconductor substrate
FR3001225B1 (fr) * 2013-01-22 2016-01-22 Commissariat Energie Atomique Procede de fabrication d’une structure par collage direct
CN104078407B (zh) * 2013-03-29 2018-12-04 济南晶正电子科技有限公司 薄膜和制造薄膜的方法
US10833175B2 (en) * 2015-06-04 2020-11-10 International Business Machines Corporation Formation of dislocation-free SiGe finFET using porous silicon
CN110459501A (zh) * 2019-05-30 2019-11-15 中国电子科技集团公司第五十五研究所 一种用于减薄圆片的加固拿持结构及其制备方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0553852B1 (fr) 1992-01-30 2003-08-20 Canon Kabushiki Kaisha Procédé de production de substrats semi-conducteurs
US6136684A (en) * 1995-07-21 2000-10-24 Canon Kabushiki Kaisha Semiconductor substrate and process for production thereof
FR2748851B1 (fr) 1996-05-15 1998-08-07 Commissariat Energie Atomique Procede de realisation d'une couche mince de materiau semiconducteur
JP4623451B2 (ja) 1997-07-30 2011-02-02 忠弘 大見 半導体基板及びその作製方法
US6271101B1 (en) * 1998-07-29 2001-08-07 Semiconductor Energy Laboratory Co., Ltd. Process for production of SOI substrate and process for production of semiconductor device
US6602767B2 (en) 2000-01-27 2003-08-05 Canon Kabushiki Kaisha Method for transferring porous layer, method for making semiconductor devices, and method for making solar battery
JP2002237607A (ja) 2000-01-27 2002-08-23 Canon Inc 多孔質層の転写方法、半導体素子の製造方法及び太陽電池の製造方法
CN1119830C (zh) * 2000-04-27 2003-08-27 中国科学院上海冶金研究所 一种器件转移方法
JP2002110688A (ja) 2000-09-29 2002-04-12 Canon Inc Ｓｏｉの熱処理方法及び製造方法
DE10131249A1 (de) * 2001-06-28 2002-05-23 Wacker Siltronic Halbleitermat Verfahren zur Herstellung eines Films oder einer Schicht aus halbleitendem Material
EP1427010B1 (fr) * 2002-11-29 2012-01-11 STMicroelectronics Srl Procédé de fabrication d'un substrat semiconducteur comprenant au moins une cavité enterrée
DE102004054564B4 (de) * 2004-11-11 2008-11-27 Siltronic Ag Halbleitersubstrat und Verfahren zu dessen Herstellung

Also Published As

Publication number Publication date
DE102004030612B3 (de) 2006-04-20
US7803695B2 (en) 2010-09-28
US20090065891A1 (en) 2009-03-12
JP4465306B2 (ja) 2010-05-19
CN1716577A (zh) 2006-01-04
FR2872343A1 (fr) 2005-12-30
KR100745598B1 (ko) 2007-08-02
US7491966B2 (en) 2009-02-17
US20050287767A1 (en) 2005-12-29
KR20060045830A (ko) 2006-05-17
CN100358128C (zh) 2007-12-26
JP2006013511A (ja) 2006-01-12

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