JP5572347B2 - Soi基板の作製方法 - Google Patents
Soi基板の作製方法 Download PDFInfo
- Publication number
- JP5572347B2 JP5572347B2 JP2009201771A JP2009201771A JP5572347B2 JP 5572347 B2 JP5572347 B2 JP 5572347B2 JP 2009201771 A JP2009201771 A JP 2009201771A JP 2009201771 A JP2009201771 A JP 2009201771A JP 5572347 B2 JP5572347 B2 JP 5572347B2
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- Prior art keywords
- single crystal
- substrate
- crystal semiconductor
- semiconductor substrate
- insulating layer
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- Expired - Fee Related
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Recrystallisation Techniques (AREA)
- Thin Film Transistor (AREA)
Description
本実施の形態では、SOI基板の作製方法の一例に関して図面を参照して説明する。
本実施の形態では、上記実施の形態において、単結晶半導体基板100と単結晶半導体基板150が貼り合わされて形成された積層基板200をSOI基板の製造プロセスにおいてボンド基板として用いる場合に関して図面を参照して説明する。
本実施の形態では、SOI基板の製造プロセスにおいて、ボンド基板として用いる単結晶半導体基板とベース基板との貼り合わせ方法に関して図面を参照して詳細に説明する。具体的には、上記実施の形態において、図1(A)〜(D)、図2(A)〜(D)、図6(A)〜(D)に対応している。
O2+hν(λ1nm)→O(3P)+O(3P) ・・・ (1)
O(3P)+O2→O3 ・・・ (2)
O3+hν(λ2nm)→O(1D)+O2 ・・・ (3)
O2+hν(λ3nm)→O(1D)+O(3P) ・・・ (4)
O(3P)+O2→O3 ・・・ (5)
O3+hν(λ3nm)→O(1D)+O2 ・・・ (6)
102 絶縁層
103 イオン
104 脆化領域
120 ベース基板
121 窒素含有層
124 単結晶半導体層
132 酸化膜
142 絶縁層
144 絶縁層
146 絶縁層
150 単結晶半導体基板
200 積層基板
Claims (4)
- ボンド基板となる第1の単結晶半導体基板と、第1の基板とを準備する第1の工程と、
前記第1の単結晶半導体基板に、加速されたイオンを照射して、前記第1の単結晶半導体基板中に脆化領域を形成し、絶縁層を介して前記第1の単結晶半導体基板と前記第1の基板とを貼り合わせる第2の工程と、
前記脆化領域において、前記第1の単結晶半導体基板を分離して、前記第1の基板上に前記絶縁層を介して単結晶半導体層を形成する第3の工程とを有し、
前記分離された第1の単結晶半導体基板に第1の接合層を形成する第4の工程と、第2の単結晶半導体基板に第2の接合層を形成する第5の工程とを経て、前記第1の接合層及び前記第2の接合層を介して、前記第1の単結晶半導体基板を、前記第2の単結晶半導体基板に貼り合わせて、積層基板を形成して、前記積層基板を、前記第1の工程におけるボンド基板として使用することを特徴とするSOI基板の作製方法。 - 請求項1において、
前記第1の接合層は、前記第2の接合層と異なる材料を有することを特徴とするSOI基板の作製方法。 - 請求項1又は請求項2において、
前記第1の接合層を、前記第2の工程における絶縁層に用いることを特徴とするSOI基板の作製方法。 - 請求項1乃至請求項3のいずれか一において、
前記第1の基板として、ガラス基板、単結晶半導体基板又は多結晶半導体基板を用いるSOI基板の作製方法。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009201771A JP5572347B2 (ja) | 2008-09-05 | 2009-09-01 | Soi基板の作製方法 |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008227725 | 2008-09-05 | ||
JP2008227725 | 2008-09-05 | ||
JP2009201771A JP5572347B2 (ja) | 2008-09-05 | 2009-09-01 | Soi基板の作製方法 |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2010087492A JP2010087492A (ja) | 2010-04-15 |
JP2010087492A5 JP2010087492A5 (ja) | 2012-10-11 |
JP5572347B2 true JP5572347B2 (ja) | 2014-08-13 |
Family
ID=41799628
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2009201771A Expired - Fee Related JP5572347B2 (ja) | 2008-09-05 | 2009-09-01 | Soi基板の作製方法 |
Country Status (3)
Country | Link |
---|---|
US (1) | US8187953B2 (ja) |
JP (1) | JP5572347B2 (ja) |
SG (1) | SG159484A1 (ja) |
Families Citing this family (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5364345B2 (ja) * | 2008-11-12 | 2013-12-11 | 株式会社半導体エネルギー研究所 | Soi基板の作製方法 |
US8318588B2 (en) * | 2009-08-25 | 2012-11-27 | Semiconductor Energy Laboratory Co., Ltd. | Method for reprocessing semiconductor substrate, method for manufacturing reprocessed semiconductor substrate, and method for manufacturing SOI substrate |
KR101731809B1 (ko) * | 2009-10-09 | 2017-05-02 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 반도체 기판의 재생 방법, 재생된 반도체 기판의 제조 방법, 및 soi 기판의 제조 방법 |
US8367519B2 (en) * | 2009-12-30 | 2013-02-05 | Memc Electronic Materials, Inc. | Method for the preparation of a multi-layered crystalline structure |
KR20120124352A (ko) * | 2010-02-05 | 2012-11-13 | 스미토모덴키고교가부시키가이샤 | 탄화규소 기판의 제조 방법 |
US9287353B2 (en) | 2010-11-30 | 2016-03-15 | Kyocera Corporation | Composite substrate and method of manufacturing the same |
AU2011337629A1 (en) * | 2010-11-30 | 2013-05-02 | Kyocera Corporation | Composite substrate and production method |
TWI570809B (zh) * | 2011-01-12 | 2017-02-11 | 半導體能源研究所股份有限公司 | 半導體裝置及其製造方法 |
US9123529B2 (en) | 2011-06-21 | 2015-09-01 | Semiconductor Energy Laboratory Co., Ltd. | Method for reprocessing semiconductor substrate, method for manufacturing reprocessed semiconductor substrate, and method for manufacturing SOI substrate |
CN106409650B (zh) * | 2015-08-03 | 2019-01-29 | 沈阳硅基科技有限公司 | 一种硅片直接键合方法 |
CN109478493A (zh) * | 2016-07-12 | 2019-03-15 | Qmat股份有限公司 | 供体衬底进行回收的方法 |
US20180033609A1 (en) * | 2016-07-28 | 2018-02-01 | QMAT, Inc. | Removal of non-cleaved/non-transferred material from donor substrate |
WO2018011731A1 (en) * | 2016-07-12 | 2018-01-18 | QMAT, Inc. | Method of a donor substrate undergoing reclamation |
US11289330B2 (en) | 2019-09-30 | 2022-03-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor-on-insulator (SOI) substrate and method for forming |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH1140786A (ja) * | 1997-07-18 | 1999-02-12 | Denso Corp | 半導体基板及びその製造方法 |
JP2000124092A (ja) * | 1998-10-16 | 2000-04-28 | Shin Etsu Handotai Co Ltd | 水素イオン注入剥離法によってsoiウエーハを製造する方法およびこの方法で製造されたsoiウエーハ |
JP2000223682A (ja) * | 1999-02-02 | 2000-08-11 | Canon Inc | 基体の処理方法及び半導体基板の製造方法 |
EP1039513A3 (en) | 1999-03-26 | 2008-11-26 | Canon Kabushiki Kaisha | Method of producing a SOI wafer |
FR2834123B1 (fr) * | 2001-12-21 | 2005-02-04 | Soitec Silicon On Insulator | Procede de report de couches minces semi-conductrices et procede d'obtention d'une plaquette donneuse pour un tel procede de report |
TWI233154B (en) * | 2002-12-06 | 2005-05-21 | Soitec Silicon On Insulator | Method for recycling a substrate |
JP5284576B2 (ja) * | 2006-11-10 | 2013-09-11 | 信越化学工業株式会社 | 半導体基板の製造方法 |
-
2009
- 2009-08-26 SG SG200905695-3A patent/SG159484A1/en unknown
- 2009-08-31 US US12/550,520 patent/US8187953B2/en not_active Expired - Fee Related
- 2009-09-01 JP JP2009201771A patent/JP5572347B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US8187953B2 (en) | 2012-05-29 |
JP2010087492A (ja) | 2010-04-15 |
US20100062546A1 (en) | 2010-03-11 |
SG159484A1 (en) | 2010-03-30 |
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