FR2382770A1 - Procede de formation de tres petites ouvertures de contact dans un dispositif de circuit integre - Google Patents

Procede de formation de tres petites ouvertures de contact dans un dispositif de circuit integre

Info

Publication number
FR2382770A1
FR2382770A1 FR7817175A FR7817175A FR2382770A1 FR 2382770 A1 FR2382770 A1 FR 2382770A1 FR 7817175 A FR7817175 A FR 7817175A FR 7817175 A FR7817175 A FR 7817175A FR 2382770 A1 FR2382770 A1 FR 2382770A1
Authority
FR
France
Prior art keywords
forming
integrated circuit
circuit device
contact openings
small contact
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7817175A
Other languages
English (en)
Other versions
FR2382770B1 (fr
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CTU of Delaware Inc
Original Assignee
Mostek Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mostek Corp filed Critical Mostek Corp
Publication of FR2382770A1 publication Critical patent/FR2382770A1/fr
Application granted granted Critical
Publication of FR2382770B1 publication Critical patent/FR2382770B1/fr
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/35—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices with charge storage in a depletion layer, e.g. charge coupled devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/32—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells

Abstract

La présente invention concerne un procédé de fabrication de dispositif à semiconducteur. Selon ce procédé, on prévoit en cours de fabrication, la formation de couches de silicium polycristallin de recouvrement qui sont disposées au-dessus de portions sélectionnées d'un substrat semiconducteur 12 et isolées du substrat ainsi que l'une de l'autre. Application notamment à la fabrication de mémoires à accès aléatoire.
FR7817175A 1977-01-26 1978-06-08 Procede de formation de tres petites ouvertures de contact dans un dispositif de circuit integre Granted FR2382770A1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US76239877A 1977-01-26 1977-01-26

Publications (2)

Publication Number Publication Date
FR2382770A1 true FR2382770A1 (fr) 1978-09-29
FR2382770B1 FR2382770B1 (fr) 1983-06-03

Family

ID=25064929

Family Applications (5)

Application Number Title Priority Date Filing Date
FR7802068A Granted FR2382768A1 (fr) 1977-01-26 1978-01-25 Procede de preparation d'une surface de substrat d'un dispositif semiconducteur isoplanar
FR7817173A Granted FR2382769A1 (fr) 1977-01-26 1978-06-08 Procede de fabrication de couches de silicium polycristallin a haute definition
FR7817175A Granted FR2382770A1 (fr) 1977-01-26 1978-06-08 Procede de formation de tres petites ouvertures de contact dans un dispositif de circuit integre
FR7817174A Granted FR2382767A1 (fr) 1977-01-26 1978-06-08 Procede de fabrication de dispositif semiconducteur
FR7817176A Granted FR2382745A1 (fr) 1977-01-26 1978-06-08 Cellule de memoire

Family Applications Before (2)

Application Number Title Priority Date Filing Date
FR7802068A Granted FR2382768A1 (fr) 1977-01-26 1978-01-25 Procede de preparation d'une surface de substrat d'un dispositif semiconducteur isoplanar
FR7817173A Granted FR2382769A1 (fr) 1977-01-26 1978-06-08 Procede de fabrication de couches de silicium polycristallin a haute definition

Family Applications After (2)

Application Number Title Priority Date Filing Date
FR7817174A Granted FR2382767A1 (fr) 1977-01-26 1978-06-08 Procede de fabrication de dispositif semiconducteur
FR7817176A Granted FR2382745A1 (fr) 1977-01-26 1978-06-08 Cellule de memoire

Country Status (5)

Country Link
JP (10) JPS5394190A (fr)
DE (1) DE2802048A1 (fr)
FR (5) FR2382768A1 (fr)
GB (5) GB1595543A (fr)
IT (1) IT1089299B (fr)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1089299B (it) * 1977-01-26 1985-06-18 Mostek Corp Procedimento per fabbricare un dispositivo semiconduttore
JPS5713772A (en) * 1980-06-30 1982-01-23 Hitachi Ltd Semiconductor device and manufacture thereof
GB2290167B (en) * 1994-06-08 1999-01-20 Hyundai Electronics Ind Method for fabricating a semiconductor device
US9954176B1 (en) 2016-10-06 2018-04-24 International Business Machines Corporation Dielectric treatments for carbon nanotube devices

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3429029A (en) * 1963-06-28 1969-02-25 Ibm Semiconductor device
DE2018027A1 (de) * 1969-04-15 1970-10-22 Tokyo Shibaura Electric Co. Ltd., Kawasaki (Japan) Verfahren zum Einbringen extrem feiner öffnungen
DE2134385A1 (de) * 1970-07-10 1972-02-03 Motorola Inc Maskier verfahren für Halbleiteranordnungen
US3810795A (en) * 1972-06-30 1974-05-14 Ibm Method for making self-aligning structure for charge-coupled and bucket brigade devices

Family Cites Families (30)

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Publication number Priority date Publication date Assignee Title
GB1175392A (en) * 1966-09-14 1969-12-23 Hitachi Ltd Method of Treating Protective Coatings for Semiconductor Devices
US3590477A (en) 1968-12-19 1971-07-06 Ibm Method for fabricating insulated-gate field effect transistors having controlled operating characeristics
US3825997A (en) * 1969-10-02 1974-07-30 Sony Corp Method for making semiconductor device
DE2040180B2 (de) 1970-01-22 1977-08-25 Intel Corp, Mountain View, Calif. (V.St.A.) Verfahren zur verhinderung von mechanischen bruechen einer duennen, die oberflaeche eines halbleiterkoerpers ueberdeckende isolierschichten ueberziehenden elektrisch leitenden schicht
US3811974A (en) * 1971-07-19 1974-05-21 North American Rockwell Silicon nitride-silicon oxide etchant
JPS5112507B2 (fr) 1971-10-22 1976-04-20
JPS5139835B2 (fr) * 1971-12-27 1976-10-29
DE2218035A1 (de) * 1972-04-14 1973-10-31 Vepa Ag Verfahren und vorrichtung zum kontinuierlichen fixieren und schrumpfen von synthese-fasern
DE2320195A1 (de) 1972-04-24 1973-12-13 Standard Microsyst Smc Durch ionenimplantation hergestellter speicherfeldeffekt-transistor mit siliciumbasis
JPS5910073B2 (ja) * 1972-10-27 1984-03-06 株式会社日立製作所 シリコン・ゲ−トｍｏｓ型半導体装置の製造方法
US3898105A (en) * 1973-10-25 1975-08-05 Mostek Corp Method for making FET circuits
JPS50123274A (fr) * 1974-03-15 1975-09-27
JPS5912495B2 (ja) 1974-10-01 1984-03-23 カブシキガイシヤ ニツポンジドウシヤブヒンソウゴウケンキユウシヨ 衝突検知装置
US3984822A (en) * 1974-12-30 1976-10-05 Intel Corporation Double polycrystalline silicon gate memory device
JPS51114079A (en) * 1975-03-31 1976-10-07 Fujitsu Ltd Construction of semiconductor memory device
JPS51118393A (en) * 1975-04-10 1976-10-18 Matsushita Electric Ind Co Ltd Semicondector unit
JPS51118392A (en) 1975-04-10 1976-10-18 Matsushita Electric Ind Co Ltd Manuforcturing process for semiconductor unit
US4002511A (en) * 1975-04-16 1977-01-11 Ibm Corporation Method for forming masks comprising silicon nitride and novel mask structures produced thereby
US4012757A (en) * 1975-05-05 1977-03-15 Intel Corporation Contactless random-access memory cell and cell pair
JPS51142982A (en) * 1975-05-05 1976-12-08 Intel Corp Method of producing single crystal silicon ic
JPS51139263A (en) * 1975-05-28 1976-12-01 Hitachi Ltd Method of selective oxidation of silicon substrate
NL7506594A (nl) * 1975-06-04 1976-12-07 Philips Nv Werkwijze voor het vervaardigen van een halfge- leiderinrichting en halfgeleiderinrichting ver- vaardigd met behulp van de werkwijze.
IT1061530B (it) * 1975-06-12 1983-04-30 Ncr Co Metodo per la formazione di connessioni elettriche in regioni selezionate di una superficie di un dispositivo semiconduttore a circuito integrato
DE2532594B2 (de) * 1975-07-21 1980-05-22 Siemens Ag, 1000 Berlin Und 8000 Muenchen Halbleiterspeicher
GB1540450A (en) 1975-10-29 1979-02-14 Intel Corp Self-aligning double polycrystalline silicon etching process
JPS6034270B2 (ja) * 1976-01-12 1985-08-07 テキサス・インスツルメンツ・インコ−ポレイテツド 半導体メモリ装置およびその製造方法
US4240092A (en) 1976-09-13 1980-12-16 Texas Instruments Incorporated Random access memory cell with different capacitor and transistor oxide thickness
US4112575A (en) * 1976-12-20 1978-09-12 Texas Instruments Incorporated Fabrication methods for the high capacity ram cell
IT1089299B (it) * 1977-01-26 1985-06-18 Mostek Corp Procedimento per fabbricare un dispositivo semiconduttore
FR2584786B1 (fr) * 1985-07-15 1989-10-27 Valeo Montage de butee de debrayage et butee de debrayage propre a un tel montage

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3429029A (en) * 1963-06-28 1969-02-25 Ibm Semiconductor device
DE2018027A1 (de) * 1969-04-15 1970-10-22 Tokyo Shibaura Electric Co. Ltd., Kawasaki (Japan) Verfahren zum Einbringen extrem feiner öffnungen
DE2134385A1 (de) * 1970-07-10 1972-02-03 Motorola Inc Maskier verfahren für Halbleiteranordnungen
US3810795A (en) * 1972-06-30 1974-05-14 Ibm Method for making self-aligning structure for charge-coupled and bucket brigade devices

Also Published As

Publication number Publication date
JPS62290181A (ja) 1987-12-17
FR2382768B1 (fr) 1983-06-10
FR2382770B1 (fr) 1983-06-03
JPH0917799A (ja) 1997-01-17
JP2720911B2 (ja) 1998-03-04
JPH04107840U (ja) 1992-09-17
IT1089299B (it) 1985-06-18
GB1595546A (en) 1981-08-12
JPS62290152A (ja) 1987-12-17
FR2382769B1 (fr) 1983-06-03
JPH0362300B2 (fr) 1991-09-25
FR2382745B1 (fr) 1983-06-03
JPS62290180A (ja) 1987-12-17
JPH0918003A (ja) 1997-01-17
JPS5760852A (en) 1982-04-13
FR2382745A1 (fr) 1978-09-29
JPS5394190A (en) 1978-08-17
GB1595548A (en) 1981-08-12
GB1595543A (en) 1981-08-12
FR2382767B1 (fr) 1983-06-03
GB1595547A (en) 1981-08-12
FR2382767A1 (fr) 1978-09-29
JPH098299A (ja) 1997-01-10
DE2802048A1 (de) 1978-07-27
GB1595545A (en) 1981-08-12
DE2802048C2 (fr) 1993-02-11
FR2382769A1 (fr) 1978-09-29
JPS62290147A (ja) 1987-12-17
FR2382768A1 (fr) 1978-09-29

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Legal Events

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CA Change of address
CD Change of name or company name
TP Transmission of property