DE69716112D1 - Taktanpassung mit feinregelung - Google Patents

Taktanpassung mit feinregelung

Info

Publication number
DE69716112D1
DE69716112D1 DE69716112T DE69716112T DE69716112D1 DE 69716112 D1 DE69716112 D1 DE 69716112D1 DE 69716112 T DE69716112 T DE 69716112T DE 69716112 T DE69716112 T DE 69716112T DE 69716112 D1 DE69716112 D1 DE 69716112D1
Authority
DE
Germany
Prior art keywords
edge
clock signal
rising
falling
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69716112T
Other languages
English (en)
Other versions
DE69716112T2 (de
Inventor
Brent Keeth
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Technology Inc
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Publication of DE69716112D1 publication Critical patent/DE69716112D1/de
Application granted granted Critical
Publication of DE69716112T2 publication Critical patent/DE69716112T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/225—Clock input buffers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/06—Address interface arrangements, e.g. address buffers

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Dram (AREA)
  • Electric Clocks (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Pulse Circuits (AREA)
DE69716112T 1996-12-03 1997-12-03 Taktanpassung mit feinregelung Expired - Lifetime DE69716112T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/759,351 US6115318A (en) 1996-12-03 1996-12-03 Clock vernier adjustment
PCT/US1997/022001 WO1998025345A1 (en) 1996-12-03 1997-12-03 Clock vernier adjustment

Publications (2)

Publication Number Publication Date
DE69716112D1 true DE69716112D1 (de) 2002-11-07
DE69716112T2 DE69716112T2 (de) 2003-05-28

Family

ID=25055332

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69716112T Expired - Lifetime DE69716112T2 (de) 1996-12-03 1997-12-03 Taktanpassung mit feinregelung

Country Status (8)

Country Link
US (1) US6115318A (de)
EP (1) EP0943177B1 (de)
JP (1) JP2001505693A (de)
KR (1) KR100435612B1 (de)
AT (1) ATE225581T1 (de)
AU (1) AU5513998A (de)
DE (1) DE69716112T2 (de)
WO (1) WO1998025345A1 (de)

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JP2001505693A (ja) 2001-04-24
WO1998025345A1 (en) 1998-06-11
EP0943177A1 (de) 1999-09-22
KR100435612B1 (ko) 2004-06-12
EP0943177B1 (de) 2002-10-02
AU5513998A (en) 1998-06-29
KR20000069287A (ko) 2000-11-25
ATE225581T1 (de) 2002-10-15
US6115318A (en) 2000-09-05
DE69716112T2 (de) 2003-05-28

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