US5719508A - Loss of lock detector for master timing generator - Google Patents
Loss of lock detector for master timing generator Download PDFInfo
- Publication number
- US5719508A US5719508A US08/595,583 US59558396A US5719508A US 5719508 A US5719508 A US 5719508A US 59558396 A US59558396 A US 59558396A US 5719508 A US5719508 A US 5719508A
- Authority
- US
- United States
- Prior art keywords
- frequency signal
- signal
- locked
- logic level
- error
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000001514 detection method Methods 0.000 claims abstract description 16
- 230000001360 synchronised effect Effects 0.000 claims abstract description 4
- 238000000034 method Methods 0.000 claims description 3
- 238000012544 monitoring process Methods 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 11
- 230000000630 rising effect Effects 0.000 description 9
- 238000013461 design Methods 0.000 description 4
- 238000012360 testing method Methods 0.000 description 4
- 238000004891 communication Methods 0.000 description 3
- 238000003491 array Methods 0.000 description 2
- 230000007704 transition Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 1
- 230000001427 coherent effect Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229920000729 poly(L-lysine) polymer Polymers 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 230000011664 signaling Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/095—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using a lock detector
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S331/00—Oscillators
- Y10S331/02—Phase locked loop having lock indicating or detecting means
Definitions
- This invention relates generally to the field of clock holdover circuits for digital communication systems and, in particular, to a loss of lock detector for a phase locked loop.
- All digital communication systems require some degree of synchronization to incoming signals by the receivers.
- the basic level of synchronization required for coherent reception is the phase synchronization of the incoming signal with a locally generated carrier.
- PLL phase locked loop
- Phase locked loops are servo-controlled loops, whose control parameter is the phase of a locally generated replica of the incoming signal.
- PLLs have three basic components: a phase detector, a loop filter, and a voltage controlled oscillator (VCO).
- VCO voltage controlled oscillator
- the phase detector is a device that produces a measure of the difference in phase between the incoming signal and the local replica. As the incoming signal and the local replica change with respect to each other, the phase difference (or the phase error) becomes a time-varying signal.
- the phase detector generates an up control signal and a down control signal for the loop filter at the input of the VCO.
- the loop filter governs the PLL's response to these variations in the error signal.
- the loop filter is generally a low pass filter for providing an error signal that is solely a function of the phase difference that is needed.
- the VCO is the device that produces the carrier replica.
- the VCO is an oscillator whose frequency is controlled by a voltage level at the device input.
- the frequency of the output signal of the VCO is a monotonic function of its input voltage over some range of input and output. A positive input voltage (up control signal) will cause the VCO output frequency to increase, while a negative voltage (down control signal) will cause it to be less.
- Phase lock is achieved by feeding the filtered version of the phase difference between the incoming signal and the output of the VCO back to the input of the VCO.
- a well-designed loop should trace changes in the phase of the incoming signal, but not be overly responsive to receiver noise.
- Loss of lock detectors are typically accomplished in discrete implementation.
- the out-of-lock state is detected with loss of lock detection circuits (LLDs), which monitor the lock status of the PLL.
- LLDs loss of lock detection circuits
- Some conventional lock detection schemes monitor the up control signal and the down control signal at the output of the phase detector to ascertain the lock status of the PLL. If the up control signal and down control signal are not pulsing, the loop node voltage remains substantially constant and the PLL should be in phase lock. When the up and down control signals are steadily generating pulses charging or discharging the loop filter to adjust the input voltage of the VCO, the loop must be in motion and thus out of phase lock.
- loss of lock detectors simply monitor the clock reference signal to determine when and if it degrades or is lost.
- a loss of lock signal may also be obtained by feeding the filtered output of the phase comparator (the VCO control voltage) into an analog window comparator. In these implementations, the lock signal goes high when the PLL is in a steady state phase and frequency lock condition, and goes low when the loop is out-of-phase.
- U.S. Pat. No. 5,278,520 discloses a lock detection circuit for providing a lock detection signal when the reference and the lock signal have a first logic state at a first transition of a control signal, and a second logic state at a second logic transition.
- the lock detection signal must return to a valid state for a predetermined number of periods before the phase lock status indicates a valid lock condition. Since the device disclosed in the above-identified patent uses the state of the reference and locked signal and checks these states with a sample clock, additional circuitry is needed for obtaining a time slot on the reference clock signal.
- Prior art lock sensors can generally be used for passive monitoring and evaluation, since the lock signal obtained with the current sensors is rather ambiguous. Thus, under certain conditions, the lock signal obtained with the prior art circuits may remain low even if the PLL is in phase lock condition. Therefore, the lock signal is not suitable to tell other active circuits whether to start using the clock generator signal.
- processors used in digital communication systems need to synthesize one or more phase-locked frequencies from a reference clock.
- the reference clock can be a recovered frequency, or an internal flee-running clock.
- the processor requires a loss of lock signal (LOL) as part of selecting a suitable clock reference to be used as the timing generator reference.
- LLOL loss of lock signal
- processors as for example in NT4F20AA, since the mixed signal ASICs were not developed, the only alternative is to seek an all digital detector to be implemented in one of several field programmable gate arrays of the processor.
- the field programmable gate array utilization of this processor is quite high, so that a simple implementation of the LLD is necessary.
- a LLD which is able to detect the occurrence of a phase lock condition at the output of the phase detector and provide a reliable phase lock signal to another circuit such as a microprocessor, for determining when and whether to start using the clock signal generated by the by the PLL clock driver circuit.
- PLL circuits such as clock signal generator circuits and clock driver circuits
- Either the reference clock or the synthesized clock is absent. This can come about either through the link being lost or through a failure of the internal dividers or clock references. The loss of lock detector needs to respond to both high and failed low conditions of the two clocks; and
- the reference clock frequency is outside the capture range of the PLL.
- the design for the present LLD tests the reference against the VCO and the VCO against the reference so that loss of lock due to missing clocks (either missing reference or failed VCO) are detected.
- the device of the present invention does not require the additional circuitry to set up a timing window.
- Still another object of the present invention is to provide a LLD with a simple design which is operable in a wide range of settings.
- the invention comprises a loss of lock detection circuit for a PLL where locked frequency lags the reference frequency by 90°.
- the alternate phase relationship is detected by swapping the reference and locked frequency inputs. Cases where frequency tracking without lock or significant phase wander within ⁇ 90° occur are not detected.
- the conventional analog detector has a similar limitation.
- a digital loss of lock detection device for a phase locked loop (PLL) which generates a locked frequency signal synchronized with a reference frequency signal.
- the device comprises a first latching means for providing a first error signal when the reference frequency signal has a first logic level and the locked frequency signal transits from the first logic level to a second logic level.
- a second latching means gives a second error signal when the reference frequency signal has the second logic level and the locked frequency signal transits from the second logic level to the first logic level.
- a third latching means provides a third error signal to indicate when the locked frequency signal has the first logic level and the reference frequency signal transits from the second logic level to the first logic level.
- a fourth latching means gives a fourth error signal when said locked frequency signal has the second logic level and the reference frequency signal transits from the first logic level to the second logic level.
- the first to fourth error signals are ORed to obtain a loss of lock signal when any of the first to fourth error signals is in the first logic state.
- a reset signal initializes the latching means.
- a fifth latching means may also be provided for latching the second error signal to give a fifth error signal to the OR gate upon detection of a phase error greater than ⁇ 90°.
- the present invention tests both edges of the reference common clock against the locked common clock, and both edges of the locked common clock are tested against the reference common clock; thus, all failures of either the reference clock or the locked clock are detected.
- FIG. 1 is a block diagram of a Phase Locked Loop (PLL) with a Loss of Lock Detector (LLD) circuit according to the present invention
- FIG. 2 is the logic circuit diagram of the LLD circuit
- FIG. 3 is a timing diagram of the input and output signals for the LLD circuit, for the case when the reference clock fails high;
- FIG. 4 is a timing diagram of the input and output signals for the LLD circuit, for the case when the reference clock fails low;
- FIG. 5 is a timing diagram of the input and output signals for the LLD circuit, for the case when the locked clock fails high;
- FIG. 6 is a timing diagram of the input and output signals for the LLD circuit, for the case when the locked clock fails low;
- FIG. 7 is a timing diagram of the input and output signals for the LLD circuit, for the case when an error of phase higher than ⁇ 90° is detected.
- FIG. 8 is a timing diagram of the input and output signals for the LLD circuit, for the case when an error of phase higher than -90° is detected.
- the Loss of Lock Detector of the present invention is designed for the NT4F20AA processor, but a similar design may be used for other processors.
- the master timing generator used on the NT4F20AA synthesizes two phase-locked frequencies, 19.44 MHz and 12.352 Mhz, from a reference clock.
- the reference clock can be any one of three frequencies: 19.44 MHz recovered from the drawer link manchester encoded signal, 1.544 MHz recovered from the T1 link, or an internal 19.44 MHz free-running clock.
- the NT4F20AA processor requires a loss of lock signal as part of selecting a suitable clock reference to be used as the MTG reference.
- the master timing generator divides any reference clock and both synthesized clocks to a common frequency, 8 KHz in this case. Therefore, the LLD can be simplified to test phase lock of the locked frequency and this reference common frequency.
- the LLD of the present invention responds to both failed high and low conditions of the reference and synthesized dock references, and also signals when the reference clock frequency is outside the capture range of the master timing generator (MTG).
- FIG. 1 illustrates a phase locked loop, generally referred to by numeral 1, and the digital LLD of the present invention generally referred to by numeral 10.
- the PLL circuit comprises the Voltage Controlled Oscillator (VCXO) 11 which generates the local frequency fC as a multiple of the locked frequency f L .
- Divider 12 provides frequency f L . This frequency is phase compared in block 13 with the reference frequency f R recovered after divider 12. The phase error output by comparator 13 is input to low pass filter 15 and then transformed into a voltage level 16 in amplifier 17, for controlling the frequency of oscillator 11.
- the alternate phase relationship is detected in the LLD 10 by swapping the locked frequency and the reference frequency received on lines 18 and 19 respectively.
- the LOL signal is obtained at output 20.
- the diagram is repeated for the other synthesized clock; the two loss-of-lock signals are ORed, and sent to the processor.
- FIG. 2 illustrates the logic circuit diagram of the LLD circuit 10. The five manifestations of the loss-of-lock detected by this circuit are:
- locked and reference clocks are active, but the reference clock is outside PLL tracking range or failed control section.
- flip-flops 21 to 24 Each of these conditions is tested by flip-flops 21 to 24.
- the outputs of the flip-flops are connected to an OR circuit 25 and the loss of lock signal (LOL) is obtained at output 20.
- LLOL loss of lock signal
- Flip-flops 21 to 24 are failed clock detectors. To reduce circuitry, the Q outputs of these flip-flops are not latched under the assumption that a lost clock signal would be a permanent condition. However, if there is cause to expect intermittent clocks, a scheme can be used where the outputs of the first to fourth flip-flops 21 to 24 are latched by fifth to eighth latching devices, respectively, just as is done for flip-flop 22.
- FIGS. 3 to 8 Timing diagrams depicting these situations are shown in FIGS. 3 to 8 and therefore the description of FIG. 2 is being made together with the description of FIGS. 3 to 8, respectively.
- FIG. 4 the signals for an "output low” failure of the reference clock (f R ) is shown.
- FIG. 5 Depicted in FIG. 5 is the LLD signaling an "output high" failure of the locked clock (f L ).
- An open circuit failure of the locked clock will also be detected since the locked clock 11 (VCXO) output is pulled up in the master timing generator 1.
- the LLD signals an "output low” failure of the locked clock (f L ).
- FIG. 7 shows the situation where the master timing generator 1 is unable to capture the reference frequency clock, either due to an offset of the reference frequency or a failure of the MTG 1 circuitry.
- the ">90° phase error" term is only approximate, since the actual error is a frequency offset, namely a time varying phase.
- FIG. 8 Operation of the LLD for negative phase error is shown in FIG. 8.
- the first indication of the loss of lock occurs on the rising edge of the reference frequency at time F in the same manner as shown at time C in FIG. 5.
- the rising edge of the reference frequency clocks the incorrect high state of the locked frequency to the output 33 of flip-flop 23. Beyond this initial detection, operation of the detector is identical to that shown in FIG. 7.
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
Description
Claims (12)
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/595,583 US5719508A (en) | 1996-02-01 | 1996-02-01 | Loss of lock detector for master timing generator |
CA002195175A CA2195175A1 (en) | 1996-02-01 | 1997-01-15 | Loss of lock detector for master timing generator |
GB9701946A GB2309839B (en) | 1996-02-01 | 1997-01-30 | Loss of lock detector for master timing generator |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/595,583 US5719508A (en) | 1996-02-01 | 1996-02-01 | Loss of lock detector for master timing generator |
Publications (1)
Publication Number | Publication Date |
---|---|
US5719508A true US5719508A (en) | 1998-02-17 |
Family
ID=24383842
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US08/595,583 Expired - Lifetime US5719508A (en) | 1996-02-01 | 1996-02-01 | Loss of lock detector for master timing generator |
Country Status (3)
Country | Link |
---|---|
US (1) | US5719508A (en) |
CA (1) | CA2195175A1 (en) |
GB (1) | GB2309839B (en) |
Cited By (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5926047A (en) * | 1997-08-29 | 1999-07-20 | Micron Technology, Inc. | Synchronous clock generator including a delay-locked loop signal loss detector |
US5940608A (en) | 1997-02-11 | 1999-08-17 | Micron Technology, Inc. | Method and apparatus for generating an internal clock signal that is synchronized to an external clock signal |
US6011732A (en) | 1997-08-20 | 2000-01-04 | Micron Technology, Inc. | Synchronous clock generator including a compound delay-locked loop |
US6016282A (en) | 1998-05-28 | 2000-01-18 | Micron Technology, Inc. | Clock vernier adjustment |
US6026050A (en) | 1997-07-09 | 2000-02-15 | Micron Technology, Inc. | Method and apparatus for adaptively adjusting the timing of a clock signal used to latch digital signals, and memory device using same |
US6029250A (en) | 1998-09-09 | 2000-02-22 | Micron Technology, Inc. | Method and apparatus for adaptively adjusting the timing offset between a clock signal and digital signals transmitted coincident with that clock signal, and memory device and system using same |
US6115318A (en) | 1996-12-03 | 2000-09-05 | Micron Technology, Inc. | Clock vernier adjustment |
US6256259B1 (en) | 1997-03-05 | 2001-07-03 | Micron Technology, Inc. | Delay-locked loop with binary-coupled capacitor |
US6269451B1 (en) | 1998-02-27 | 2001-07-31 | Micron Technology, Inc. | Method and apparatus for adjusting data timing by delaying clock signal |
US6279090B1 (en) | 1998-09-03 | 2001-08-21 | Micron Technology, Inc. | Method and apparatus for resynchronizing a plurality of clock signals used in latching respective digital signals applied to a packetized memory device |
US20010024135A1 (en) * | 1997-06-20 | 2001-09-27 | Harrison Ronnie M. | Method and apparatus for generating a sequence of clock signals |
WO2001078235A1 (en) | 2000-04-06 | 2001-10-18 | Telefonaktiebolaget Lm Ericsson | Sliding-window based signal monitoring |
US6338127B1 (en) | 1998-08-28 | 2002-01-08 | Micron Technology, Inc. | Method and apparatus for resynchronizing a plurality of clock signals used to latch respective digital signals, and memory device using same |
US6349399B1 (en) | 1998-09-03 | 2002-02-19 | Micron Technology, Inc. | Method and apparatus for generating expect data from a captured bit pattern, and memory device using same |
US6374360B1 (en) | 1998-12-11 | 2002-04-16 | Micron Technology, Inc. | Method and apparatus for bit-to-bit timing correction of a high speed memory bus |
US6430696B1 (en) | 1998-11-30 | 2002-08-06 | Micron Technology, Inc. | Method and apparatus for high speed data capture utilizing bit-to-bit timing correction, and memory device using same |
US6686777B1 (en) * | 2002-10-09 | 2004-02-03 | Agilent Technologies, Inc. | Phase detector having improved timing margins |
US20040095197A1 (en) * | 2002-11-18 | 2004-05-20 | Wang David Y. | Lock detector circuit for phase locked loop |
US20040103226A1 (en) * | 2001-06-28 | 2004-05-27 | Brian Johnson | Method and system for adjusting the timing offset between a clock signal and respective digital signals transmitted along with clock signal, and memory device and computer system using same |
US20050091464A1 (en) * | 2003-10-27 | 2005-04-28 | Ralph James | System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding |
US20050286505A1 (en) * | 1999-03-01 | 2005-12-29 | Harrison Ronnie M | Method and apparatus for generating a phase dependent control signal |
US7183863B1 (en) * | 1998-10-20 | 2007-02-27 | Lucent Technologies Inc. | Self-initializing frequency detector |
US20080301533A1 (en) * | 2003-06-12 | 2008-12-04 | Micron Technology, Inc. | Dynamic synchronization of data capture on an optical or other high speed communications link |
US10574242B2 (en) | 2017-10-12 | 2020-02-25 | Synaptics Incorporated | Phase locked loop sampler and restorer |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6343096B1 (en) * | 1998-07-16 | 2002-01-29 | Telefonaktiebolaget Lm Ericsson | Clock pulse degradation detector |
EP2633620B1 (en) * | 2010-10-26 | 2018-02-28 | Marvell World Trade Ltd. | Pll dual edge lock detector |
EP3285401B1 (en) * | 2016-08-19 | 2020-01-29 | Aselsan Elektronik Sanayi ve Ticaret Anonim Sirketi | A system and a method for detecting loss of phase lock |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4613777A (en) * | 1983-12-24 | 1986-09-23 | Hewlett-Packard Company | Binary signal comparator using two d flip-flops for precise triggering |
US5126690A (en) * | 1991-08-08 | 1992-06-30 | International Business Machines Corporation | Phase locked loop lock detector including loss of lock and gain of lock detectors |
US5159279A (en) * | 1990-11-27 | 1992-10-27 | Dsc Communications Corporation | Apparatus and method for detecting out-of-lock condition in a phase lock loop |
US5278520A (en) * | 1992-10-26 | 1994-01-11 | Codex, Corp. | Phase lock detection in a phase lock loop |
US5530383A (en) * | 1994-12-05 | 1996-06-25 | May; Michael R. | Method and apparatus for a frequency detection circuit for use in a phase locked loop |
-
1996
- 1996-02-01 US US08/595,583 patent/US5719508A/en not_active Expired - Lifetime
-
1997
- 1997-01-15 CA CA002195175A patent/CA2195175A1/en not_active Abandoned
- 1997-01-30 GB GB9701946A patent/GB2309839B/en not_active Expired - Fee Related
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4613777A (en) * | 1983-12-24 | 1986-09-23 | Hewlett-Packard Company | Binary signal comparator using two d flip-flops for precise triggering |
US5159279A (en) * | 1990-11-27 | 1992-10-27 | Dsc Communications Corporation | Apparatus and method for detecting out-of-lock condition in a phase lock loop |
US5126690A (en) * | 1991-08-08 | 1992-06-30 | International Business Machines Corporation | Phase locked loop lock detector including loss of lock and gain of lock detectors |
US5278520A (en) * | 1992-10-26 | 1994-01-11 | Codex, Corp. | Phase lock detection in a phase lock loop |
US5530383A (en) * | 1994-12-05 | 1996-06-25 | May; Michael R. | Method and apparatus for a frequency detection circuit for use in a phase locked loop |
Cited By (55)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6115318A (en) | 1996-12-03 | 2000-09-05 | Micron Technology, Inc. | Clock vernier adjustment |
US5940608A (en) | 1997-02-11 | 1999-08-17 | Micron Technology, Inc. | Method and apparatus for generating an internal clock signal that is synchronized to an external clock signal |
US6340904B1 (en) | 1997-02-11 | 2002-01-22 | Micron Technology, Inc. | Method and apparatus for generating an internal clock signal that is synchronized to an external clock signal |
US6262921B1 (en) | 1997-03-05 | 2001-07-17 | Micron Technology, Inc. | Delay-locked loop with binary-coupled capacitor |
US6483757B2 (en) | 1997-03-05 | 2002-11-19 | Micron Technology, Inc. | Delay-locked loop with binary-coupled capacitor |
US6490207B2 (en) | 1997-03-05 | 2002-12-03 | Micron Technology, Inc. | Delay-locked loop with binary-coupled capacitor |
US6490224B2 (en) | 1997-03-05 | 2002-12-03 | Micron Technology, Inc. | Delay-locked loop with binary-coupled capacitor |
US6400641B1 (en) | 1997-03-05 | 2002-06-04 | Micron Technology, Inc. | Delay-locked loop with binary-coupled capacitor |
US6256259B1 (en) | 1997-03-05 | 2001-07-03 | Micron Technology, Inc. | Delay-locked loop with binary-coupled capacitor |
US20010024135A1 (en) * | 1997-06-20 | 2001-09-27 | Harrison Ronnie M. | Method and apparatus for generating a sequence of clock signals |
US20080126059A1 (en) * | 1997-06-20 | 2008-05-29 | Micron Technology, Inc. | Method and apparatus for generating a sequence of clock signals |
US20050249028A1 (en) * | 1997-06-20 | 2005-11-10 | Harrison Ronnie M | Method and apparatus for generating a sequence of clock signals |
US7889593B2 (en) | 1997-06-20 | 2011-02-15 | Round Rock Research, Llc | Method and apparatus for generating a sequence of clock signals |
US8565008B2 (en) | 1997-06-20 | 2013-10-22 | Round Rock Research, Llc | Method and apparatus for generating a sequence of clock signals |
US6026050A (en) | 1997-07-09 | 2000-02-15 | Micron Technology, Inc. | Method and apparatus for adaptively adjusting the timing of a clock signal used to latch digital signals, and memory device using same |
US6011732A (en) | 1997-08-20 | 2000-01-04 | Micron Technology, Inc. | Synchronous clock generator including a compound delay-locked loop |
US6201424B1 (en) | 1997-08-29 | 2001-03-13 | Micron Technology, Inc. | Synchronous clock generator including a delay-locked loop signal loss detector |
US5926047A (en) * | 1997-08-29 | 1999-07-20 | Micron Technology, Inc. | Synchronous clock generator including a delay-locked loop signal loss detector |
US6499111B2 (en) | 1998-02-27 | 2002-12-24 | Micron Technology, Inc. | Apparatus for adjusting delay of a clock signal relative to a data signal |
US6327196B1 (en) | 1998-02-27 | 2001-12-04 | Micron Technology, Inc. | Synchronous memory device having an adjustable data clocking circuit |
US6269451B1 (en) | 1998-02-27 | 2001-07-31 | Micron Technology, Inc. | Method and apparatus for adjusting data timing by delaying clock signal |
US6378079B1 (en) | 1998-02-27 | 2002-04-23 | Micron Technology, Inc. | Computer system having memory device with adjustable data clocking |
US6643789B2 (en) | 1998-02-27 | 2003-11-04 | Micron Technology, Inc. | Computer system having memory device with adjustable data clocking using pass gates |
US6016282A (en) | 1998-05-28 | 2000-01-18 | Micron Technology, Inc. | Clock vernier adjustment |
US6338127B1 (en) | 1998-08-28 | 2002-01-08 | Micron Technology, Inc. | Method and apparatus for resynchronizing a plurality of clock signals used to latch respective digital signals, and memory device using same |
US6279090B1 (en) | 1998-09-03 | 2001-08-21 | Micron Technology, Inc. | Method and apparatus for resynchronizing a plurality of clock signals used in latching respective digital signals applied to a packetized memory device |
US6477675B2 (en) | 1998-09-03 | 2002-11-05 | Micron Technology, Inc. | Method and apparatus for generating expect data from a captured bit pattern, and memory device using same |
US6349399B1 (en) | 1998-09-03 | 2002-02-19 | Micron Technology, Inc. | Method and apparatus for generating expect data from a captured bit pattern, and memory device using same |
US6647523B2 (en) | 1998-09-03 | 2003-11-11 | Micron Technology, Inc. | Method for generating expect data from a captured bit pattern, and memory device using same |
US7954031B2 (en) | 1998-09-03 | 2011-05-31 | Round Rock Research, Llc | Method and apparatus for generating expect data from a captured bit pattern, and memory device using same |
US20100106997A1 (en) * | 1998-09-03 | 2010-04-29 | Micron Technology, Inc. | Method and apparatus for generating expect data from a captured bit pattern, and memory device using same |
US7657813B2 (en) | 1998-09-03 | 2010-02-02 | Micron Technology, Inc. | Method and apparatus for generating expect data from a captured bit pattern, and memory device using same |
US20080195908A1 (en) * | 1998-09-03 | 2008-08-14 | Micron Technology, Inc. | Method and apparatus for generating expect data from a captured bit pattern, and memory device using same |
US20040158785A1 (en) * | 1998-09-03 | 2004-08-12 | Manning Troy A. | Method and apparatus for generating expect data from a captured bit pattern, and memory device using same |
US6029250A (en) | 1998-09-09 | 2000-02-22 | Micron Technology, Inc. | Method and apparatus for adaptively adjusting the timing offset between a clock signal and digital signals transmitted coincident with that clock signal, and memory device and system using same |
US7183863B1 (en) * | 1998-10-20 | 2007-02-27 | Lucent Technologies Inc. | Self-initializing frequency detector |
US6430696B1 (en) | 1998-11-30 | 2002-08-06 | Micron Technology, Inc. | Method and apparatus for high speed data capture utilizing bit-to-bit timing correction, and memory device using same |
US6374360B1 (en) | 1998-12-11 | 2002-04-16 | Micron Technology, Inc. | Method and apparatus for bit-to-bit timing correction of a high speed memory bus |
US6662304B2 (en) | 1998-12-11 | 2003-12-09 | Micron Technology, Inc. | Method and apparatus for bit-to-bit timing correction of a high speed memory bus |
US20080279323A1 (en) * | 1999-03-01 | 2008-11-13 | Harrison Ronnie M | Method and apparatus for generating a phase dependent control signal |
US20050286505A1 (en) * | 1999-03-01 | 2005-12-29 | Harrison Ronnie M | Method and apparatus for generating a phase dependent control signal |
US8433023B2 (en) | 1999-03-01 | 2013-04-30 | Round Rock Research, Llc | Method and apparatus for generating a phase dependent control signal |
US8107580B2 (en) | 1999-03-01 | 2012-01-31 | Round Rock Research, Llc | Method and apparatus for generating a phase dependent control signal |
WO2001078235A1 (en) | 2000-04-06 | 2001-10-18 | Telefonaktiebolaget Lm Ericsson | Sliding-window based signal monitoring |
US20040103226A1 (en) * | 2001-06-28 | 2004-05-27 | Brian Johnson | Method and system for adjusting the timing offset between a clock signal and respective digital signals transmitted along with clock signal, and memory device and computer system using same |
US6801989B2 (en) | 2001-06-28 | 2004-10-05 | Micron Technology, Inc. | Method and system for adjusting the timing offset between a clock signal and respective digital signals transmitted along with that clock signal, and memory device and computer system using same |
US6686777B1 (en) * | 2002-10-09 | 2004-02-03 | Agilent Technologies, Inc. | Phase detector having improved timing margins |
US20040095197A1 (en) * | 2002-11-18 | 2004-05-20 | Wang David Y. | Lock detector circuit for phase locked loop |
US6765444B2 (en) * | 2002-11-18 | 2004-07-20 | Neoaxiom Corporation | Cross clocked lock detector circuit for phase locked loop |
US20080301533A1 (en) * | 2003-06-12 | 2008-12-04 | Micron Technology, Inc. | Dynamic synchronization of data capture on an optical or other high speed communications link |
US8181092B2 (en) | 2003-06-12 | 2012-05-15 | Round Rock Research, Llc | Dynamic synchronization of data capture on an optical or other high speed communications link |
US8892974B2 (en) | 2003-06-12 | 2014-11-18 | Round Rock Research, Llc | Dynamic synchronization of data capture on an optical or other high speed communications link |
US20050091464A1 (en) * | 2003-10-27 | 2005-04-28 | Ralph James | System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding |
US20060206742A1 (en) * | 2003-10-27 | 2006-09-14 | Ralph James | System and method for using a learning sequence to establish communications on a high- speed nonsynchronous interface in the absence of clock forwarding |
US10574242B2 (en) | 2017-10-12 | 2020-02-25 | Synaptics Incorporated | Phase locked loop sampler and restorer |
Also Published As
Publication number | Publication date |
---|---|
GB2309839A (en) | 1997-08-06 |
GB9701946D0 (en) | 1997-03-19 |
GB2309839B (en) | 2000-12-06 |
CA2195175A1 (en) | 1997-08-02 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US5719508A (en) | Loss of lock detector for master timing generator | |
EP0051473B1 (en) | Phase-locked loop with initialization loop | |
EP0671829B1 (en) | Clock regeneration circuit | |
US4806878A (en) | Phase comparator lock detect circuit and a synthesizer using same | |
US6111442A (en) | Phase-locked loop circuit with dynamic backup | |
US4297650A (en) | Phase locked loop carrier recovery circuit with false lock prevention | |
US4849704A (en) | Duty cycle independent phase detector | |
US6421404B1 (en) | Phase-difference detector and clock-recovery circuit using the same | |
US6998889B2 (en) | Circuit, apparatus and method for obtaining a lock state value | |
JP3028955B1 (en) | Lock detection method and device in PLL lock circuit | |
US7082178B2 (en) | Lock detector circuit for dejitter phase lock loop (PLL) | |
US6757349B1 (en) | PLL frequency synthesizer with lock detection circuit | |
US4068181A (en) | Digital phase comparator | |
US5986486A (en) | Circuits and methods for a phase lock loop for synchronous reference clocks | |
US5656977A (en) | Frequency-lock indicator circuit with frequency-only detection | |
JPH0588023B2 (en) | ||
JP2002124937A (en) | Off-synchronization detector | |
EP0756799B1 (en) | Device for deriving a clock signal from a synchronizing signal and a video recorder provided with the device | |
US7023944B2 (en) | Method and circuit for glitch-free changing of clocks having different phases | |
CN113541915B (en) | Method and device for realizing fast clock recovery with wide dynamic range | |
JPS6348928A (en) | Clock control system for network synchronization | |
US6680991B1 (en) | Detection of frequency differences between signals | |
JPH06164381A (en) | Out-of-synchronism detection circuit for pll | |
JPH04271634A (en) | Interface circuit and phase locked loop used therefor | |
US20240007110A1 (en) | Clock and data recovery circuit using neural network circuit to obtain frequency difference information |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: NORTHERN TELECOM LIMITED, CANADA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:BNR INC.;REEL/FRAME:008432/0024 Effective date: 19960429 Owner name: BNR INC., NORTH CAROLINA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:DALY, WILLIAM GEORGE;REEL/FRAME:008560/0625 Effective date: 19951211 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
AS | Assignment |
Owner name: NORTEL NETWORKS CORPORATION, CANADA Free format text: CHANGE OF NAME;ASSIGNOR:NORTHERN TELECOM LIMITED;REEL/FRAME:010567/0001 Effective date: 19990429 |
|
AS | Assignment |
Owner name: NORTEL NETWORKS LIMITED, CANADA Free format text: CHANGE OF NAME;ASSIGNOR:NORTEL NETWORKS CORPORATION;REEL/FRAME:011195/0706 Effective date: 20000830 Owner name: NORTEL NETWORKS LIMITED,CANADA Free format text: CHANGE OF NAME;ASSIGNOR:NORTEL NETWORKS CORPORATION;REEL/FRAME:011195/0706 Effective date: 20000830 |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
FPAY | Fee payment |
Year of fee payment: 8 |
|
SULP | Surcharge for late payment |
Year of fee payment: 7 |
|
REMI | Maintenance fee reminder mailed | ||
FPAY | Fee payment |
Year of fee payment: 12 |
|
AS | Assignment |
Owner name: CIENA LUXEMBOURG S.A.R.L.,LUXEMBOURG Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:NORTEL NETWORKS LIMITED;REEL/FRAME:024213/0653 Effective date: 20100319 Owner name: CIENA LUXEMBOURG S.A.R.L., LUXEMBOURG Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:NORTEL NETWORKS LIMITED;REEL/FRAME:024213/0653 Effective date: 20100319 |
|
AS | Assignment |
Owner name: CIENA CORPORATION,MARYLAND Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:CIENA LUXEMBOURG S.A.R.L.;REEL/FRAME:024252/0060 Effective date: 20100319 Owner name: CIENA CORPORATION, MARYLAND Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:CIENA LUXEMBOURG S.A.R.L.;REEL/FRAME:024252/0060 Effective date: 20100319 |
|
AS | Assignment |
Owner name: DEUTSCHE BANK AG NEW YORK BRANCH, NEW YORK Free format text: SECURITY INTEREST;ASSIGNOR:CIENA CORPORATION;REEL/FRAME:033329/0417 Effective date: 20140715 |
|
AS | Assignment |
Owner name: BANK OF AMERICA, N.A., AS ADMINISTRATIVE AGENT, NO Free format text: PATENT SECURITY AGREEMENT;ASSIGNOR:CIENA CORPORATION;REEL/FRAME:033347/0260 Effective date: 20140715 |
|
AS | Assignment |
Owner name: CIENA CORPORATION, MARYLAND Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:DEUTSCHE BANK AG NEW YORK BRANCH;REEL/FRAME:050938/0389 Effective date: 20191028 |
|
AS | Assignment |
Owner name: BANK OF AMERICA, N.A., AS COLLATERAL AGENT, ILLINO Free format text: PATENT SECURITY AGREEMENT;ASSIGNOR:CIENA CORPORATION;REEL/FRAME:050969/0001 Effective date: 20191028 |
|
AS | Assignment |
Owner name: CIENA CORPORATION, MARYLAND Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:BANK OF AMERICA, N.A.;REEL/FRAME:065630/0232 Effective date: 20231024 |