ATE128254T1 - Digitale taktpufferschaltung mit regelbarer verzögerung. - Google Patents
Digitale taktpufferschaltung mit regelbarer verzögerung.Info
- Publication number
- ATE128254T1 ATE128254T1 AT91102364T AT91102364T ATE128254T1 AT E128254 T1 ATE128254 T1 AT E128254T1 AT 91102364 T AT91102364 T AT 91102364T AT 91102364 T AT91102364 T AT 91102364T AT E128254 T1 ATE128254 T1 AT E128254T1
- Authority
- AT
- Austria
- Prior art keywords
- clock signal
- buffer circuit
- clock buffer
- digital clock
- adjustable delay
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/10—Distribution of clock signals, e.g. skew
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
- H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
- H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
- H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
- H03L7/0816—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Pulse Circuits (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Dram (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US07/489,079 US5118975A (en) | 1990-03-05 | 1990-03-05 | Digital clock buffer circuit providing controllable delay |
Publications (1)
Publication Number | Publication Date |
---|---|
ATE128254T1 true ATE128254T1 (de) | 1995-10-15 |
Family
ID=23942318
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AT91102364T ATE128254T1 (de) | 1990-03-05 | 1991-02-19 | Digitale taktpufferschaltung mit regelbarer verzögerung. |
Country Status (8)
Country | Link |
---|---|
US (1) | US5118975A (de) |
EP (1) | EP0445574B1 (de) |
JP (1) | JP2892515B2 (de) |
AT (1) | ATE128254T1 (de) |
AU (1) | AU640448B2 (de) |
CA (1) | CA2037593A1 (de) |
DE (1) | DE69113083T2 (de) |
IE (1) | IE910706A1 (de) |
Families Citing this family (97)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2658015B1 (fr) * | 1990-02-06 | 1994-07-29 | Bull Sa | Circuit verrouille en phase et multiplieur de frequence en resultant. |
US5212484A (en) * | 1990-03-05 | 1993-05-18 | Thinking Machines Corporation | Digital to analog converter system employing plural digital to analog converters which is insensitive to resistance variations |
US5239206A (en) * | 1990-03-06 | 1993-08-24 | Advanced Micro Devices, Inc. | Synchronous circuit with clock skew compensating function and circuits utilizing same |
US5220206A (en) * | 1990-06-29 | 1993-06-15 | Analog Devices, Inc. | Control apparatus with improved recovery from power reduction, and storage device therefor |
US5305451A (en) * | 1990-09-05 | 1994-04-19 | International Business Machines Corporation | Single phase clock distribution circuit for providing clock signals to multiple chip integrated circuit systems |
US5231319A (en) * | 1991-08-22 | 1993-07-27 | Ncr Corporation | Voltage variable delay circuit |
WO1993006544A1 (en) * | 1991-09-23 | 1993-04-01 | Digital Equipment Corporation | Method and apparatus for clock skew reduction through absolute delay regulation |
US5294842A (en) * | 1991-09-23 | 1994-03-15 | Digital Equipment Corp. | Update synchronizer |
US5214680A (en) * | 1991-11-01 | 1993-05-25 | Hewlett-Packard Company | CMOS pseudo-NMOS programmable capacitance time vernier and method of calibration |
EP0541288B1 (de) * | 1991-11-05 | 1998-07-08 | Fu-Chieh Hsu | Redundanzarchitektur für Schaltungsmodul |
US5831467A (en) * | 1991-11-05 | 1998-11-03 | Monolithic System Technology, Inc. | Termination circuit with power-down mode for use in circuit module architecture |
US5498990A (en) * | 1991-11-05 | 1996-03-12 | Monolithic System Technology, Inc. | Reduced CMOS-swing clamping circuit for bus lines |
FR2690022B1 (fr) * | 1992-03-24 | 1997-07-11 | Bull Sa | Circuit a retard variable. |
US5317202A (en) * | 1992-05-28 | 1994-05-31 | Intel Corporation | Delay line loop for 1X on-chip clock generation with zero skew and 50% duty cycle |
JP3381938B2 (ja) * | 1992-06-05 | 2003-03-04 | 株式会社東芝 | 入力遷移検知パルス発生回路 |
US5298866A (en) * | 1992-06-04 | 1994-03-29 | Kaplinsky Cecil H | Clock distribution circuit with active de-skewing |
JPH0621788A (ja) * | 1992-07-01 | 1994-01-28 | Mitsubishi Electric Corp | 半導体集積回路 |
WO1994003901A1 (en) * | 1992-08-10 | 1994-02-17 | Monolithic System Technology, Inc. | Fault-tolerant, high-speed bus system and bus interface for wafer-scale integration |
US5414832A (en) * | 1992-12-17 | 1995-05-09 | International Business Machines Corporation | Tunable synchronous electronic communication apparatus |
JPH0744432B2 (ja) * | 1993-02-24 | 1995-05-15 | 日本電気株式会社 | クロック生成装置 |
SE501190C2 (sv) * | 1993-04-28 | 1994-12-05 | Ellemtel Utvecklings Ab | Digitalt styrd kristalloscillator |
US5459422A (en) * | 1993-06-02 | 1995-10-17 | Advanced Micro Devices, Inc. | Edge selective delay circuit |
JP2576366B2 (ja) * | 1993-06-23 | 1997-01-29 | 日本電気株式会社 | 可変遅延バッファ回路 |
FR2710800B1 (fr) * | 1993-09-27 | 1995-12-15 | Sgs Thomson Microelectronics | Ligne à retard numérique. |
FR2711287B1 (fr) * | 1993-10-11 | 1996-01-05 | Sgs Thomson Microelectronics | Circuit d'indication de relation de phase entre plusieurs signaux de même fréquence et son application à un circuit d'ajustage des déphasages entre ces signaux. |
US5564022A (en) * | 1994-02-09 | 1996-10-08 | Intel Corporation | Method and apparatus for automatically inserting clock buffers into a logic block to reduce clock skew |
US5440515A (en) * | 1994-03-08 | 1995-08-08 | Motorola Inc. | Delay locked loop for detecting the phase difference of two signals having different frequencies |
JPH07273618A (ja) * | 1994-03-30 | 1995-10-20 | Nec Corp | クロックドライバ回路 |
US5655113A (en) | 1994-07-05 | 1997-08-05 | Monolithic System Technology, Inc. | Resynchronization circuit for a memory system and method of operating same |
US5828250A (en) * | 1994-09-06 | 1998-10-27 | Intel Corporation | Differential delay line clock generator with feedback phase control |
JP2771464B2 (ja) * | 1994-09-29 | 1998-07-02 | 日本電気アイシーマイコンシステム株式会社 | ディジタルpll回路 |
US5796673A (en) * | 1994-10-06 | 1998-08-18 | Mosaid Technologies Incorporated | Delay locked loop implementation in a synchronous dynamic random access memory |
US5486783A (en) * | 1994-10-31 | 1996-01-23 | At&T Corp. | Method and apparatus for providing clock de-skewing on an integrated circuit board |
US5826068A (en) | 1994-11-09 | 1998-10-20 | Adaptec, Inc. | Integrated circuit with a serial port having only one pin |
US5572719A (en) * | 1994-11-22 | 1996-11-05 | Advanced Micro Devices | Clock control system for microprocessors including a delay sensing circuit |
KR0138220B1 (ko) * | 1994-12-30 | 1998-05-15 | 김주용 | 위상동기루프회로의 클럭지연보상 및 듀티제어 장치 |
JP3639000B2 (ja) * | 1995-06-13 | 2005-04-13 | 富士通株式会社 | 位相合わせ装置及び遅延制御回路 |
JPH0916282A (ja) * | 1995-07-04 | 1997-01-17 | Toshiba Corp | クロック制御方式 |
US5744991A (en) * | 1995-10-16 | 1998-04-28 | Altera Corporation | System for distributing clocks using a delay lock loop in a programmable logic circuit |
US5757218A (en) * | 1996-03-12 | 1998-05-26 | International Business Machines Corporation | Clock signal duty cycle correction circuit and method |
US5838179A (en) * | 1996-07-03 | 1998-11-17 | General Signal Corporation | Clock compensation circuit |
GB2355328B (en) * | 1996-08-13 | 2001-05-23 | Fujitsu Ltd | Semiconductor device |
TW340262B (en) | 1996-08-13 | 1998-09-11 | Fujitsu Ltd | Semiconductor device, system consisting of semiconductor devices and digital delay circuit |
WO1998013742A1 (fr) * | 1996-09-25 | 1998-04-02 | Matsushita Electric Industrial Co., Ltd. | Circuit de conversion frequence-tension, circuit d'evaluation de quantite de retard, systeme a circuit de conversion frequence-tension, procede d'adaptation des caracteristiques entree/sortie du circuit de conversion, et dispositif de reglage automatique pour les caracteristiques entree/sortie dudit circuit |
JP3388134B2 (ja) * | 1997-04-10 | 2003-03-17 | 富士通株式会社 | 位相比較回路、dll回路および半導体集積回路 |
KR100237567B1 (ko) * | 1997-05-07 | 2000-01-15 | 김영환 | 지연잠금 회로 |
EP0878910B1 (de) * | 1997-05-16 | 2007-05-23 | Fujitsu Limited | Laufzeitunterschiedverringerungsschaltung |
US5910740A (en) * | 1997-06-18 | 1999-06-08 | Raytheon Company | Phase locked loop having memory |
WO1999022382A1 (fr) * | 1997-10-24 | 1999-05-06 | Takashi Suzuki | Equipement electrique et electronique |
US5949262A (en) * | 1998-01-07 | 1999-09-07 | International Business Machines Corporation | Method and apparatus for coupled phase locked loops |
US6522188B1 (en) * | 1998-04-10 | 2003-02-18 | Top Layer Networks, Inc. | High-speed data bus for network switching |
US6246704B1 (en) * | 1998-04-30 | 2001-06-12 | Stmicroelectronics, Inc. | Automatic on-chip clock tuning methodology and circuitry |
US6055287A (en) * | 1998-05-26 | 2000-04-25 | Mcewan; Thomas E. | Phase-comparator-less delay locked loop |
JP3763673B2 (ja) * | 1998-06-11 | 2006-04-05 | 富士通株式会社 | Dll回路 |
US6137334A (en) | 1998-07-06 | 2000-10-24 | Micron Technology, Inc. | Logic circuit delay stage and delay line utilizing same |
JP2000035831A (ja) * | 1998-07-21 | 2000-02-02 | Nec Corp | 可変閾値電圧トランジスタを用いた低スキュークロックツリー回路 |
CA2250538A1 (en) | 1998-10-30 | 2000-04-30 | Mosaid Technologies Incorporated | Duty cycle regulator |
US6831493B2 (en) | 1998-10-30 | 2004-12-14 | Mosaid Technologies Incorporated | Duty cycle regulator |
GB9828037D0 (en) * | 1998-12-18 | 1999-02-10 | Sgs Thomson Microelectronics | Circuitry and a method for introducing a delay |
KR100284741B1 (ko) * | 1998-12-18 | 2001-03-15 | 윤종용 | 로컬클럭 신호 발생회로 및 방법, 내부클럭신호 발생회로 및방법,이를 이용한 반도체 메모리 장치 |
GB2348327B (en) | 1999-02-18 | 2003-02-19 | Sgs Thomson Microelectronics | Clock skew removal appartus |
JP4394788B2 (ja) | 1999-05-10 | 2010-01-06 | 株式会社アドバンテスト | 遅延時間判定装置 |
US6275085B1 (en) * | 1999-05-24 | 2001-08-14 | Micron Technology, Inc. | Comparator for determining process variations |
JP2001075671A (ja) * | 1999-09-08 | 2001-03-23 | Nec Corp | 位相補償回路 |
ATE390788T1 (de) | 1999-10-14 | 2008-04-15 | Bluearc Uk Ltd | Vorrichtung und verfahren zur hardware-ausführung oder hardware-beschleunigung von betriebssystemfunktionen |
ATE401597T1 (de) * | 2000-01-24 | 2008-08-15 | Broadcom Corp | System und verfahren zur kompensation von durch versorgungsspannung induzierten signalverzögerungsfehlanpassungen |
US6748549B1 (en) * | 2000-06-26 | 2004-06-08 | Intel Corporation | Clocking an I/O buffer, having a selectable phase difference from the system clock, to and from a remote I/O buffer clocked in phase with the system clock |
US6831490B1 (en) * | 2000-07-18 | 2004-12-14 | Hewlett-Packard Development Company, L.P. | Clock synchronization circuit and method |
DE10064929A1 (de) * | 2000-12-23 | 2002-07-04 | Alcatel Sa | Verfahren und Kompensationsmodul zur Phasenkompensation von Taktsignalen |
US6621882B2 (en) | 2001-03-02 | 2003-09-16 | General Dynamics Information Systems, Inc. | Method and apparatus for adjusting the clock delay in systems with multiple integrated circuits |
US6850107B2 (en) | 2001-08-29 | 2005-02-01 | Micron Technology, Inc. | Variable delay circuit and method, and delay locked loop, memory device and computer system using same |
US6501307B1 (en) | 2001-11-12 | 2002-12-31 | Pericom Semiconductor Corp. | Spread-spectrum clock buffer/driver that modulates clock period by switching loads |
JP2003188720A (ja) * | 2001-12-21 | 2003-07-04 | Mitsubishi Electric Corp | Pll回路 |
US6720810B1 (en) * | 2002-06-14 | 2004-04-13 | Xilinx, Inc. | Dual-edge-correcting clock synchronization circuit |
CA2494967A1 (en) * | 2002-08-08 | 2004-02-19 | Timelab Corporation | Clock distributor circuit for maintaining a phase relationship between remote operating nodes and a reference clock on a chip |
US7457822B1 (en) | 2002-11-01 | 2008-11-25 | Bluearc Uk Limited | Apparatus and method for hardware-based file system |
US8041735B1 (en) | 2002-11-01 | 2011-10-18 | Bluearc Uk Limited | Distributed file system and method |
JP4279023B2 (ja) * | 2003-03-25 | 2009-06-17 | 富士通株式会社 | 状態表示情報設定回路 |
US6839301B2 (en) * | 2003-04-28 | 2005-01-04 | Micron Technology, Inc. | Method and apparatus for improving stability and lock time for synchronous circuits |
US20050007154A1 (en) * | 2003-07-07 | 2005-01-13 | Patella Benjamin J. | System and method for evaluating the speed of a circuit |
US7236057B2 (en) * | 2003-08-26 | 2007-06-26 | Toshiba America Electronic Components, Inc. | Spread spectrum clock generator |
US7233210B2 (en) * | 2003-08-26 | 2007-06-19 | Toshiba America Electric Components, Inc. | Spread spectrum clock generator |
US20050046458A1 (en) * | 2003-08-28 | 2005-03-03 | Schroeder Charles G. | Digital delay elements constructed in a programmable logic device |
US7421606B2 (en) * | 2004-05-18 | 2008-09-02 | Micron Technology, Inc. | DLL phase detection using advanced phase equalization |
US7078950B2 (en) * | 2004-07-20 | 2006-07-18 | Micron Technology, Inc. | Delay-locked loop with feedback compensation |
US7088156B2 (en) * | 2004-08-31 | 2006-08-08 | Micron Technology, Inc. | Delay-locked loop having a pre-shift phase detector |
US8405435B2 (en) * | 2004-11-10 | 2013-03-26 | Lsi Corporation | Delay locked loop having internal test path |
US7177775B2 (en) * | 2005-04-29 | 2007-02-13 | International Business Machines Corporation | Testable digital delay line |
EP1772795A1 (de) * | 2005-10-10 | 2007-04-11 | STMicroelectronics (Research & Development) Limited | Schneller Pufferzeiger in einem Takt |
US7821301B2 (en) * | 2006-01-11 | 2010-10-26 | International Business Machines Corporation | Method and apparatus for measuring and compensating for static phase error in phase locked loops |
US7355380B2 (en) * | 2006-05-19 | 2008-04-08 | Transwitch Corporation | Methods and apparatus for testing delay locked loops and clock skew |
US7639054B1 (en) * | 2008-01-16 | 2009-12-29 | Altera Corporation | Techniques for generating programmable delays |
US8094698B2 (en) * | 2008-01-29 | 2012-01-10 | Realtek Semiconductor Corp. | Method for generating a spread spectrum clock and apparatus thereof |
US8269563B2 (en) * | 2008-06-10 | 2012-09-18 | Qualcomm Incorporated | Dithering a digitally-controlled oscillator output in a phase-locked loop |
TWI623198B (zh) * | 2016-10-20 | 2018-05-01 | 國立高雄第一科技大學 | 增益解析度之互補型金氧半之全數位架構脈衝混合方法及其裝置 |
US10340931B1 (en) * | 2017-12-30 | 2019-07-02 | Tektronix, Inc. | Dynamic delay adjustment for multi-channel digital-to-analog converter synchronization |
KR102678655B1 (ko) * | 2019-07-05 | 2024-06-27 | 에스케이하이닉스 주식회사 | 메모리 인터페이스, 이를 포함하는 데이터 저장 장치 및 그 동작 방법 |
Family Cites Families (37)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2450008A1 (fr) * | 1979-02-21 | 1980-09-19 | Portejoie Jean Francois | Circuit de synchronisation de signaux numeriques plesiochrones par justification |
US4365210A (en) * | 1980-06-26 | 1982-12-21 | Motorola, Inc. | Data and clock recovery system having a phase-locked-loop and which controls dynamic loop response of a data stream of unknown data format |
US4339823A (en) * | 1980-08-15 | 1982-07-13 | Motorola, Inc. | Phase corrected clock signal recovery circuit |
DE3173313D1 (en) * | 1980-09-25 | 1986-02-06 | Toshiba Kk | Clock synchronization signal generating circuit |
US4369515A (en) * | 1980-10-06 | 1983-01-18 | Gte Automatic Electric Labs Inc. | Clock synchronization circuit |
JPS57203213A (en) * | 1981-06-08 | 1982-12-13 | Trio Kenwood Corp | Clock signal reproducing circuit |
JPS5814622A (ja) * | 1981-07-20 | 1983-01-27 | Advantest Corp | 遅延回路 |
US4412342A (en) * | 1981-12-18 | 1983-10-25 | Gte Automatic Electric Labs Inc. | Clock synchronization system |
US4519086A (en) * | 1982-06-16 | 1985-05-21 | Western Digital Corporation | MOS Phase lock loop synchronization circuit |
NL8203921A (nl) * | 1982-10-11 | 1984-05-01 | Philips Nv | Multipel redundant kloksysteem, bevattende een aantal onderling synchroniserende klokken, en klokschakeling voor gebruik in zo een kloksysteem. |
JPS5977605A (ja) * | 1982-10-26 | 1984-05-04 | Sansui Electric Co | 読取りクロツク生成方式 |
US4479216A (en) * | 1982-12-22 | 1984-10-23 | At&T Bell Laboratories | Skew-free clock circuit for integrated circuit chip |
JPS59225640A (ja) * | 1983-06-06 | 1984-12-18 | Nitsuko Ltd | クロツク位相同期方式 |
GB2143096B (en) * | 1983-07-06 | 1987-02-04 | Motorola Israel Ltd | Clock recovery circuit |
US4590602A (en) * | 1983-08-18 | 1986-05-20 | General Signal | Wide range clock recovery circuit |
US4516035A (en) * | 1983-08-22 | 1985-05-07 | Ncr Corporation | Phase synchronization and control circuit |
US4617679A (en) * | 1983-09-20 | 1986-10-14 | Nec Electronics U.S.A., Inc. | Digital phase lock loop circuit |
US4637018A (en) * | 1984-08-29 | 1987-01-13 | Burroughs Corporation | Automatic signal delay adjustment method |
US4633488A (en) * | 1984-11-13 | 1986-12-30 | Digital Equipment Corporation | Phase-locked loop for MFM data recording |
US4680779A (en) * | 1985-01-14 | 1987-07-14 | David Systems, Inc. | Distributed clock synchronization in a digital data switching system |
FR2577087B1 (fr) * | 1985-02-07 | 1987-03-06 | Thomson Csf Mat Tel | Dispositif de distribution d'horloge tripliquee, chaque signal d'horloge comportant un signal de synchronisation |
US4700347A (en) * | 1985-02-13 | 1987-10-13 | Bolt Beranek And Newman Inc. | Digital phase adjustment |
US4689575A (en) * | 1985-07-15 | 1987-08-25 | Rca Corporation | Clock synchronization circuit for a computer timer |
US4663523A (en) * | 1985-11-12 | 1987-05-05 | Xerox Corporation | Spatial pixel clock synchronization system |
US4635000A (en) * | 1985-11-12 | 1987-01-06 | Xerox Corporation | Temporal pixel clock synchronization system |
US4626798A (en) * | 1985-12-11 | 1986-12-02 | Gte Laboratories Incorporated | Phase-lock loop including integrated circuit voltage controlled oscillator |
FR2593341B1 (fr) * | 1986-01-20 | 1988-03-04 | Alcatel Thomson Faisceaux | Dispositif de recuperation de rythme |
US4759041A (en) * | 1987-02-19 | 1988-07-19 | Unisys Corporation | Local area network control system synchronization with phase-lock loop |
US4804928A (en) * | 1987-05-12 | 1989-02-14 | Texas Instruments Incorporated | Phase-frequency compare circuit for phase lock loop |
WO1989000311A1 (en) * | 1987-06-30 | 1989-01-12 | Unisys Corporation | Automatic clock de-skewing on a circuit board |
US4771196A (en) * | 1987-08-05 | 1988-09-13 | California Institute Of Technology | Electronically variable active analog delay line |
US4807266A (en) * | 1987-09-28 | 1989-02-21 | Compaq Computer Corporation | Circuit and method for performing equal duty cycle odd value clock division and clock synchronization |
US4873491A (en) * | 1987-10-19 | 1989-10-10 | Wilkins Jeffrey K | Phase shift circuit utilizing a variable time delay line |
US4908841A (en) * | 1987-10-30 | 1990-03-13 | Digital Equipment Corporation | Data decoding circuit including phase-locked loop timing |
US4829377A (en) * | 1988-03-03 | 1989-05-09 | Communications Satellite Corporation | Horizontal synchronization, clock synchronization, D. C. restoration and gain control scheme for an analog TV system |
JP2901657B2 (ja) * | 1988-09-14 | 1999-06-07 | 株式会社日立製作所 | クロック信号供給装置 |
US5043596A (en) * | 1988-09-14 | 1991-08-27 | Hitachi, Ltd. | Clock signal supplying device having a phase compensation circuit |
-
1990
- 1990-03-05 US US07/489,079 patent/US5118975A/en not_active Expired - Lifetime
-
1991
- 1991-02-14 AU AU71061/91A patent/AU640448B2/en not_active Ceased
- 1991-02-19 EP EP91102364A patent/EP0445574B1/de not_active Expired - Lifetime
- 1991-02-19 AT AT91102364T patent/ATE128254T1/de not_active IP Right Cessation
- 1991-02-19 DE DE69113083T patent/DE69113083T2/de not_active Expired - Fee Related
- 1991-03-04 IE IE070691A patent/IE910706A1/en unknown
- 1991-03-05 CA CA002037593A patent/CA2037593A1/en not_active Abandoned
- 1991-03-05 JP JP3038702A patent/JP2892515B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
AU640448B2 (en) | 1993-08-26 |
JPH04219022A (ja) | 1992-08-10 |
DE69113083D1 (de) | 1995-10-26 |
AU7106191A (en) | 1991-09-05 |
US5118975A (en) | 1992-06-02 |
EP0445574A3 (en) | 1992-10-21 |
EP0445574A2 (de) | 1991-09-11 |
CA2037593A1 (en) | 1991-09-06 |
IE910706A1 (en) | 1991-09-11 |
DE69113083T2 (de) | 1996-04-11 |
EP0445574B1 (de) | 1995-09-20 |
JP2892515B2 (ja) | 1999-05-17 |
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Legal Events
Date | Code | Title | Description |
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RER | Ceased as to paragraph 5 lit. 3 law introducing patent treaties |