EP0445574A3 - Digital clock buffer circuit providing controllable delay - Google Patents
Digital clock buffer circuit providing controllable delay Download PDFInfo
- Publication number
- EP0445574A3 EP0445574A3 EP19910102364 EP91102364A EP0445574A3 EP 0445574 A3 EP0445574 A3 EP 0445574A3 EP 19910102364 EP19910102364 EP 19910102364 EP 91102364 A EP91102364 A EP 91102364A EP 0445574 A3 EP0445574 A3 EP 0445574A3
- Authority
- EP
- European Patent Office
- Prior art keywords
- clock signal
- buffer circuit
- clock buffer
- digital clock
- circuit providing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/10—Distribution of clock signals, e.g. skew
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
- H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
- H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
- H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
- H03L7/0816—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Pulse Circuits (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Dram (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US489079 | 1990-03-05 | ||
US07/489,079 US5118975A (en) | 1990-03-05 | 1990-03-05 | Digital clock buffer circuit providing controllable delay |
Publications (3)
Publication Number | Publication Date |
---|---|
EP0445574A2 EP0445574A2 (en) | 1991-09-11 |
EP0445574A3 true EP0445574A3 (en) | 1992-10-21 |
EP0445574B1 EP0445574B1 (en) | 1995-09-20 |
Family
ID=23942318
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP91102364A Expired - Lifetime EP0445574B1 (en) | 1990-03-05 | 1991-02-19 | Digital clock buffer circuit providing controllable delay |
Country Status (8)
Country | Link |
---|---|
US (1) | US5118975A (en) |
EP (1) | EP0445574B1 (en) |
JP (1) | JP2892515B2 (en) |
AT (1) | ATE128254T1 (en) |
AU (1) | AU640448B2 (en) |
CA (1) | CA2037593A1 (en) |
DE (1) | DE69113083T2 (en) |
IE (1) | IE910706A1 (en) |
Families Citing this family (96)
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KR100284741B1 (en) * | 1998-12-18 | 2001-03-15 | 윤종용 | Local clock signal generation circuit and method, Internal clock signal generation circuit and method, Semiconductor memory device using the same |
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Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1989000311A1 (en) * | 1987-06-30 | 1989-01-12 | Unisys Corporation | Automatic clock de-skewing on a circuit board |
EP0359177A2 (en) * | 1988-09-14 | 1990-03-21 | Hitachi, Ltd. | Clock signal supplying device |
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-
1990
- 1990-03-05 US US07/489,079 patent/US5118975A/en not_active Expired - Lifetime
-
1991
- 1991-02-14 AU AU71061/91A patent/AU640448B2/en not_active Ceased
- 1991-02-19 EP EP91102364A patent/EP0445574B1/en not_active Expired - Lifetime
- 1991-02-19 DE DE69113083T patent/DE69113083T2/en not_active Expired - Fee Related
- 1991-02-19 AT AT91102364T patent/ATE128254T1/en not_active IP Right Cessation
- 1991-03-04 IE IE070691A patent/IE910706A1/en unknown
- 1991-03-05 JP JP3038702A patent/JP2892515B2/en not_active Expired - Fee Related
- 1991-03-05 CA CA002037593A patent/CA2037593A1/en not_active Abandoned
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
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WO1989000311A1 (en) * | 1987-06-30 | 1989-01-12 | Unisys Corporation | Automatic clock de-skewing on a circuit board |
EP0359177A2 (en) * | 1988-09-14 | 1990-03-21 | Hitachi, Ltd. | Clock signal supplying device |
Non-Patent Citations (1)
Title |
---|
IEEE JOURNAL OF SOLID-STATE CIRCUITS. vol. 24, no. 5, October 1989, NEW YORK US pages 1412 - 1418; TAI-ICHI ET AL.: 'A 10-ps Resolution, Process-Insensitive Timing Generator' * |
Also Published As
Publication number | Publication date |
---|---|
JP2892515B2 (en) | 1999-05-17 |
DE69113083D1 (en) | 1995-10-26 |
CA2037593A1 (en) | 1991-09-06 |
DE69113083T2 (en) | 1996-04-11 |
EP0445574B1 (en) | 1995-09-20 |
ATE128254T1 (en) | 1995-10-15 |
IE910706A1 (en) | 1991-09-11 |
US5118975A (en) | 1992-06-02 |
JPH04219022A (en) | 1992-08-10 |
EP0445574A2 (en) | 1991-09-11 |
AU7106191A (en) | 1991-09-05 |
AU640448B2 (en) | 1993-08-26 |
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