DE69602686T2 - Verfahren zur Herstellung einer Elektrodenstruktur für eine Halbleitervorrichtung - Google Patents

Verfahren zur Herstellung einer Elektrodenstruktur für eine Halbleitervorrichtung

Info

Publication number
DE69602686T2
DE69602686T2 DE69602686T DE69602686T DE69602686T2 DE 69602686 T2 DE69602686 T2 DE 69602686T2 DE 69602686 T DE69602686 T DE 69602686T DE 69602686 T DE69602686 T DE 69602686T DE 69602686 T2 DE69602686 T2 DE 69602686T2
Authority
DE
Germany
Prior art keywords
electrode
semiconductor device
aluminum
oxide layer
circuit board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69602686T
Other languages
German (de)
English (en)
Other versions
DE69602686D1 (de
Inventor
Yoshihiro Bessho
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Application granted granted Critical
Publication of DE69602686D1 publication Critical patent/DE69602686D1/de
Publication of DE69602686T2 publication Critical patent/DE69602686T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/064—Manufacture or treatment of conductive parts of the interconnections by modifying the conductivity of conductive parts, e.g. by alloying
    • H10W20/065—Manufacture or treatment of conductive parts of the interconnections by modifying the conductivity of conductive parts, e.g. by alloying by making at least a portion of the conductive part non-conductive, e.g. by oxidation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/012—Manufacture or treatment of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H10W72/01221—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using local deposition
    • H10W72/01225—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using local deposition in solid form, e.g. by using a powder or by stud bumping
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07231—Techniques
    • H10W72/07236—Soldering or alloying
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/221—Structures or relative sizes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/242—Dispositions, e.g. layouts relative to the surface, e.g. recessed, protruding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H10W72/252—Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/29—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5522—Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/853—On the same surface
    • H10W72/856—Bump connectors and die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/981—Auxiliary members, e.g. spacers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Wire Bonding (AREA)
  • Electrodes Of Semiconductors (AREA)
DE69602686T 1995-07-14 1996-07-15 Verfahren zur Herstellung einer Elektrodenstruktur für eine Halbleitervorrichtung Expired - Lifetime DE69602686T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17838695 1995-07-14

Publications (2)

Publication Number Publication Date
DE69602686D1 DE69602686D1 (de) 1999-07-08
DE69602686T2 true DE69602686T2 (de) 1999-10-21

Family

ID=16047590

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69602686T Expired - Lifetime DE69602686T2 (de) 1995-07-14 1996-07-15 Verfahren zur Herstellung einer Elektrodenstruktur für eine Halbleitervorrichtung

Country Status (8)

Country Link
US (2) US6387794B2 (https=)
EP (1) EP0753890B1 (https=)
KR (1) KR100236448B1 (https=)
CN (1) CN1107979C (https=)
DE (1) DE69602686T2 (https=)
MY (1) MY118453A (https=)
SG (1) SG54349A1 (https=)
TW (1) TW318321B (https=)

Families Citing this family (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3030271B2 (ja) 1997-05-19 2000-04-10 富士通株式会社 半導体部品の実装方法
DE69811296D1 (de) * 1997-07-11 2003-03-20 Bosch Gmbh Robert Erhöhte Haftung der Unterseitenbeschichtung von Flip-Chips
JP3421548B2 (ja) 1997-09-10 2003-06-30 富士通株式会社 半導体ベアチップ、半導体ベアチップの製造方法、及び半導体ベアチップの実装構造
TW451535B (en) * 1998-09-04 2001-08-21 Sony Corp Semiconductor device and package, and fabrication method thereof
JP3399518B2 (ja) * 1999-03-03 2003-04-21 インターナショナル・ビジネス・マシーンズ・コーポレーション 半導体構造およびその製造方法
JP3526788B2 (ja) 1999-07-01 2004-05-17 沖電気工業株式会社 半導体装置の製造方法
JP4722318B2 (ja) * 2000-06-05 2011-07-13 ローム株式会社 チップ抵抗器
US7084716B2 (en) * 2001-04-10 2006-08-01 Picosecond Pulse Labs Ultrafast sampler with coaxial transition
US6900710B2 (en) 2001-04-10 2005-05-31 Picosecond Pulse Labs Ultrafast sampler with non-parallel shockline
US20030116346A1 (en) * 2001-12-21 2003-06-26 Forster James Allam Low cost area array probe for circuits having solder-ball contacts are manufactured using a wire bonding machine
US20040007779A1 (en) * 2002-07-15 2004-01-15 Diane Arbuthnot Wafer-level method for fine-pitch, high aspect ratio chip interconnect
US7358834B1 (en) 2002-08-29 2008-04-15 Picosecond Pulse Labs Transmission line voltage controlled nonlinear signal processors
US7646095B2 (en) * 2003-09-30 2010-01-12 Panasonic Corporation Semiconductor device
US20070075436A1 (en) * 2003-10-06 2007-04-05 Nec Corporation Electronic device and manufacturing method of the same
US7351656B2 (en) * 2005-01-21 2008-04-01 Kabushiki Kaihsa Toshiba Semiconductor device having oxidized metal film and manufacture method of the same
JP2007053130A (ja) * 2005-08-15 2007-03-01 Matsushita Electric Ind Co Ltd 接合構造および接合方法
US20070045812A1 (en) * 2005-08-31 2007-03-01 Micron Technology, Inc. Microfeature assemblies including interconnect structures and methods for forming such interconnect structures
US7612629B2 (en) 2006-05-26 2009-11-03 Picosecond Pulse Labs Biased nonlinear transmission line comb generators
US20080005204A1 (en) * 2006-06-30 2008-01-03 Scientific-Atlanta, Inc. Systems and Methods for Applying Retention Rules
US7700475B1 (en) * 2006-10-05 2010-04-20 Marvell International Ltd. Pillar structure on bump pad
KR100811034B1 (ko) * 2007-04-30 2008-03-06 삼성전기주식회사 전자소자 내장 인쇄회로기판의 제조방법
JP4431606B2 (ja) * 2007-10-05 2010-03-17 シャープ株式会社 半導体装置、半導体装置の実装方法、および半導体装置の実装構造
US8570239B2 (en) * 2008-10-10 2013-10-29 LHC2 Inc. Spiraling surface antenna
TW201133745A (en) * 2009-08-27 2011-10-01 Advanpack Solutions Private Ltd Stacked bump interconnection structure and semiconductor package formed using the same
JP5303489B2 (ja) * 2010-02-16 2013-10-02 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US8927391B2 (en) * 2011-05-27 2015-01-06 Taiwan Semiconductor Manufacturing Company, Ltd. Package-on-package process for applying molding compound
US9105552B2 (en) * 2011-10-31 2015-08-11 Taiwan Semiconductor Manufacturing Company, Ltd. Package on package devices and methods of packaging semiconductor dies
CN102672340B (zh) * 2012-05-29 2014-08-06 李光 直接在铝材上进行金丝球超声波焊接工艺
TWI536508B (zh) 2012-08-24 2016-06-01 日本特殊陶業股份有限公司 Wiring board
JP5523641B1 (ja) * 2012-08-24 2014-06-18 日本特殊陶業株式会社 配線基板
CN108109980A (zh) * 2017-12-01 2018-06-01 中芯长电半导体（江阴）有限公司 芯片尺寸封装结构及其制备方法

Family Cites Families (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3629669A (en) 1968-11-25 1971-12-21 Gen Motors Corp Passivated wire-bonded semiconductor device
JPS4952973A (https=) 1972-09-22 1974-05-23
US4258382A (en) 1978-07-03 1981-03-24 National Semiconductor Corporation Expanded pad structure
JPS5827334A (ja) * 1981-08-11 1983-02-18 Nippon Telegr & Teleph Corp <Ntt> 半導体装置
JPS5833848A (ja) * 1981-08-24 1983-02-28 Toshiba Corp 半導体装置
JPS58184728A (ja) * 1982-04-22 1983-10-28 Tdk Corp 半導体素子とその製造法
JPS58197736A (ja) 1982-05-13 1983-11-17 Nec Corp 半導体装置
JPS59161852A (ja) 1983-03-04 1984-09-12 Nec Corp 半導体装置
JPS63236339A (ja) 1987-03-24 1988-10-03 Nec Corp 半導体集積回路装置
JPS63269541A (ja) * 1987-04-27 1988-11-07 Nec Corp 半導体装置
US5014111A (en) * 1987-12-08 1991-05-07 Matsushita Electric Industrial Co., Ltd. Electrical contact bump and a package provided with the same
JPH0221622A (ja) 1988-07-08 1990-01-24 Nec Corp 半導体装置
JPH0682704B2 (ja) 1989-06-27 1994-10-19 株式会社東芝 半導体装置
JPH0360035A (ja) * 1989-07-27 1991-03-15 Nec Corp 半導体装置
US5074947A (en) * 1989-12-18 1991-12-24 Epoxy Technology, Inc. Flip chip technology using electrically conductive polymers and dielectrics
JPH03191527A (ja) 1989-12-20 1991-08-21 Nec Corp 半導体素子の電極構造
JPH03208354A (ja) * 1990-01-10 1991-09-11 Mitsubishi Electric Corp 半導体装置およびその製造方法
JPH03295247A (ja) * 1990-04-12 1991-12-26 Fujitsu Ltd 半導体装置の製造方法
JP2563652B2 (ja) 1990-07-17 1996-12-11 株式会社東芝 半導体装置及びその製造方法
JPH04124880A (ja) 1990-09-17 1992-04-24 Hitachi Ltd 半導体式圧力センサ
US5136365A (en) * 1990-09-27 1992-08-04 Motorola, Inc. Anisotropic conductive adhesive and encapsulant material
JPH04214642A (ja) 1990-12-12 1992-08-05 Mitsubishi Electric Corp 樹脂封止型半導体装置
JP2731040B2 (ja) 1991-02-05 1998-03-25 三菱電機株式会社 半導体装置の製造方法
US5565378A (en) * 1992-02-17 1996-10-15 Mitsubishi Denki Kabushiki Kaisha Process of passivating a semiconductor device bonding pad by immersion in O2 or O3 solution
US5261593A (en) * 1992-08-19 1993-11-16 Sheldahl, Inc. Direct application of unpackaged integrated circuit to flexible printed circuit
US5436503A (en) 1992-11-18 1995-07-25 Matsushita Electronics Corporation Semiconductor device and method of manufacturing the same
JP3191527B2 (ja) 1993-10-05 2001-07-23 株式会社明電舎 一相断線常時監視方式
US5508561A (en) 1993-11-15 1996-04-16 Nec Corporation Apparatus for forming a double-bump structure used for flip-chip mounting
JP2687856B2 (ja) * 1993-12-17 1997-12-08 日本電気株式会社 バンプの製造方法及び製造装置
JP3295247B2 (ja) 1994-10-17 2002-06-24 株式会社アマダ パネルベンダ用マニピュレータの制御装置

Also Published As

Publication number Publication date
EP0753890A2 (en) 1997-01-15
TW318321B (https=) 1997-10-21
US20010014523A1 (en) 2001-08-16
US6387794B2 (en) 2002-05-14
SG54349A1 (en) 1998-11-16
EP0753890B1 (en) 1999-06-02
KR970008446A (ko) 1997-02-24
MY118453A (en) 2004-11-30
US20020081830A1 (en) 2002-06-27
CN1107979C (zh) 2003-05-07
KR100236448B1 (ko) 1999-12-15
DE69602686D1 (de) 1999-07-08
CN1147150A (zh) 1997-04-09
US6603207B2 (en) 2003-08-05
EP0753890A3 (en) 1997-03-05

Similar Documents

Publication Publication Date Title
DE69602686T2 (de) Verfahren zur Herstellung einer Elektrodenstruktur für eine Halbleitervorrichtung
DE69022087T2 (de) Verfahren zum Herstellen einer Halbleiteranordnung.
DE69534543T2 (de) Halbleiteranordnung, Montagesubstrat für die Halbleiteranordnung und Verfahren zum Ersetzen der Halbleiteranordnung
DE69133497T2 (de) Leiterrahmen für eine Halbleiteranordnung und dessen Herstellungsverfahren
DE69527330T2 (de) Halbleiteranordnung und Herstellungsverfahren
DE69119952T2 (de) Oberflächenmontierbare Halbleitervorrichtung mit selbstbeladenen Lötverbindungen
DE102012105840B4 (de) Verfahren zum Befestigen einer Metallfläche auf einen Träger und Verfahren zum Befestigen eines Chips auf einen Chipträger
DE4313980B4 (de) Integrierte Hybridschaltung und Verfahren zu deren Herstellung
DE10101948B4 (de) Verfahren zum Anordnen eines Halbleiterchips auf einem Substrat und auf einem Substrat montierbarer Halbleiterbaustein
DE102019130778B4 (de) Ein Package, welches ein Chip Kontaktelement aus zwei verschiedenen elektrisch leitfähigen Materialien aufweist, sowie ein Verfahren zum Herstellen eines Package
DE69813701T2 (de) Elektrodenstruktur einer Siliziumhalbleiteranordnung
DE102006012322A1 (de) Substrat für eine elektronische Einheit und Verfahren zu deren Herstellung, elektronische Einheit und Verfahren zu deren Herstellung
DE102005028951B4 (de) Anordnung zur elektrischen Verbindung einer Halbleiter-Schaltungsanordnung mit einer äusseren Kontakteinrichtung
DE10333841A1 (de) Halbleiterbauteil in Halbleiterchipgröße mit flipchipartigen Außenkontakten und Verfahren zur Herstellung desselben
DE3330068A1 (de) Hybrid-integrierte schaltung und verfahren zur herstellung derselben
DE2345149A1 (de) Elektronisches hybrid-bauteil mit halbleiter-chips
DE19717611A1 (de) Struktur zum Anbringen von elektronischen Komponenten und Verfahren zum Anbringen der elektronischen Komponenten
EP1324389B1 (de) Halbleiterbauelement im Chip-Format und Verfahren zu seiner Herstellung
DE102012109319A1 (de) Bump-on-Trace-Baugruppenstruktur und Verfahren zur Herstellung derselben
DE112017002198T5 (de) Halbleitereinrichtung
DE112012006812T5 (de) Elektronische Komponente und Fertigungsverfahren für elektronische Komponente
DE10011368A1 (de) Halbleiterbauelement und Verfahren zu seiner Herstellung
JP3356649B2 (ja) 半導体装置及びその製造方法
DE68914927T2 (de) Halbleiteranordnung vom mit Plastik umhüllten Typ und Verfahren zur Herstellung derselben.
DE3828700C2 (de) Kupferplattierter Leiterrahmen für Halbleiter-Kunststoff-Gehäuse

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: PANASONIC CORP., KADOMA, OSAKA, JP