JPH03295247A - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法

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Publication number
JPH03295247A
JPH03295247A JP2097383A JP9738390A JPH03295247A JP H03295247 A JPH03295247 A JP H03295247A JP 2097383 A JP2097383 A JP 2097383A JP 9738390 A JP9738390 A JP 9738390A JP H03295247 A JPH03295247 A JP H03295247A
Authority
JP
Japan
Prior art keywords
pad part
hole
film
exposed
pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2097383A
Other languages
English (en)
Inventor
Hajime Kiyokawa
肇 清川
Hidetoshi Nishio
英俊 西尾
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP2097383A priority Critical patent/JPH03295247A/ja
Publication of JPH03295247A publication Critical patent/JPH03295247A/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • H01L2224/486—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48617—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950 °C
    • H01L2224/48624—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0504—14th Group
    • H01L2924/05042—Si3N4

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 〔概要］ 半導体チップに設けられたアルミニウムパッド部にワイ
ヤをボンディングした構成の半導体８１１を製造する方
法に関し、 筒中な方法を用いてアルミニウムパッド部の腐食を防止
して高信頼性の半導体装置を製造することを目的とし、 パッド部にワイヤをボンディング後、過酸化水素に浸漬
してパッド部の表面に酸化膜を形成する工程を含む。
〔産業上の利用分野〕
本発明は、半導体チップに設けられたアルミニウムパッ
ド部にワイヤをボンディングした構成の半導体装置を製
造する方法に関する。
近年、半導体装置は種々の分野で広く用いられており、
高信頼性が要求されている。この場合、半導体装置とし
ては例えば湿度の面において過酷な環境に置かれること
もあり、このような場合においても信頼性を維持する必
要がある。
〔従来の技術〕
従来、上記のような半導体装置を製造するに際し、半導
体チップにアルミニウムパッド部を設け、チップ全面に
ＣＶＤ法等で窒化シリコン膜を設けて耐湿性のためのカ
バー膜とし、しかる後、パッド部における窒化シリコン
躾を除去してパッド部を一部露出させ、この露出したパ
ッド部に金等のワイヤをボンディングしていた。この場
合、チップ全面に窒化シリコン膜を形成し、パッド部に
おける窒化シリコン膜を除去するまでの工程を前工程と
称し、しかる後、半導体チップをパッケージに′ｌＡｌ
１シてパッド部にワイヤボンディングし、樹脂封入する
までの工程を後工程（アセンブリ工程）と称し、夫々別
工程とされている。
〔発明が解決しようとする課題〕
前記従来の方法は、パッド部の一部を露出させた部分に
ワイヤボンディングするだけであるので、パッド部が露
出している部分において耐湿性が悪く、パッド部が腐食
し易く、導通不良を起す等、信頼性が低い問題点があっ
た。
そこで、このような問題点を解決するべく、従来、パッ
ド部にワイヤボンディングした後、露出しているパッド
部に再びＣＶＤ法にて窒化シリコン躾を形成する方法が
開発されている。然るに、この方法は、後工程（アセン
ブリ工程）の中に、前工程でしか行なわないＣＶＤ法の
工程を入れなければならず、従って、能率が悪く、作業
時間を多く必要とし、コスト高になる問題点があった。
特に、前工程を終了した段階で製品を輸出し、後工程の
設備しかない外国の工場でアセンブリを行なうようなシ
ステムをとった場合、外国の工場にもＣＶＤ法の装置を
設置しなければならず、コスト高となり、不都合である
。
本発明は、簡単な方法を用いてアルミニウムパッド部の
腐食を防止して高信頼性の半導体装置を製造する方法を
提供することを目的とする。
〔課題を解決するための手段〕
上記問題点は、パッド部にワイヤをボンディング後、過
酸化水素に浸漬してパッド部の表面に酸化膜を形成する
工程を含むことを特徴とする半導体装置の製造方法によ
って解決される。
〔作用〕
本発明では、ワイヤボンディング終了後に過酸化水素に
浸漬して表面に酸化膜を形成しているので、処理が簡単
であり、このようなパッド部の腐食防止処理を後工程（
アセンブリ工程）の中に簡単に組入れることができ、能
率的であり、作業時間も少なくて済む。
〔実施例〕
第１図は本発明の一実施例の製造工程図を示す。
同図（Ａ）において、半導体チップ１の表面全面にプラ
ズマＣＶＤ法にて窒化シリコン膜２を形成し、次に同図
（Ｂ）に示す如く、半導体チップ１の表面に設けられて
いる厚さ１μｍ１−辺　１００μｍの大きさのアルミニ
ウムパッド部３上に形成された窒化シリコン膜２にパッ
ド部３よりも小さい面積の孔２ａを形成してパッド部３
の表面の一部を露出させる。ここまでをいわゆる前工程
と称する工程で製造する。
続いて後工程と称する工程に移し、同図（Ｃ）に示ス如
く、孔２ａによって露出したパッド部３に直径５０μｍ
〜８０μｍの金のワイヤ４をボンディングする。次にこ
のようにして作成されたチップ本体全体を、濃度数１０
％で常温の過酸化水素（Ｈ２Ｏ２）に数分間浸ｉする。
これにより、同図（Ｄ＞及び第２図の平面図に示す如く
、孔２ａによって露出したパッド部３の表面には鹸化ア
ルミニウムＭ５が形成される。このとき、金は一般に過
酸化水素程度の弱い酸には酸化されることはなく、又、
窒化シリコン膜２も酸化されることはないので、特に問
題はない。
このように、孔２ａによって露出したアルミニウムパッ
ド部３の表面は酸化アルミニウム膜５によって保護され
、簡単な方法によって耐湿性を保持でき、腐食を防止で
きる。この場合、単に過酸化水素に浸漬するだけの極め
て簡単な方法であるので、後工程の中に簡単に組入れる
ことができ、後工程の中にプラズマＣＶＤ法の工程を入
れなければならない従来例に比して能率的であり、作業
時間が少なくて済み、しかも−度に大量のチップ本体を
処理できる。
なお、この後でチップ本体に設けられたワイヤをＦｅ−
Ｎｉ合金系あるいはＣｕ系のリードフレームに接続する
。このように、チップ本体を過酸化水素に浸漬した後で
リードフレームを接続するようにすれば、リードフレー
ムの表面に酸化アルミニウム膜が形成されることはなく
、特に問題ない。
〔発明の効果〕
以上説明した如く、本発明によれば、ワイヤボンディン
グ終了後に過酸化水素に浸漬するようにしているので、
極めて簡単な方法でパッド部に保護膜を形成でき、従っ
て、後工程（アセンブリ工程）の中に簡単に組入れるこ
とができ、後工程の中にプラズマＣＶＤ法による工程を
入れなければならない従来例に比して能率的であり、作
業時間も少なくて済み、又、−度に天吊のチップ本体を
処理でき、低コストである。
第２図は本発明によって製造される半導体装置の要部の
平面図である。
図において、 １は半導体チップ、 ２は窒化シリコン膜、 ２ａは孔、 ３はアルミニウムパッド部、 ４はワイヤ、 ５は酸化アルミニウム膜 を示す。

Claims (1)

    【特許請求の範囲】
  1. 　パッド部（３）にワイヤ（４）をボンディング後、過
    酸化水素に浸漬して該パッド部（３）の表面に酸化膜を
    形成する工程を含むことを特徴とする半導体装置の製造
    方法。
JP2097383A 1990-04-12 1990-04-12 半導体装置の製造方法 Pending JPH03295247A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2097383A JPH03295247A (ja) 1990-04-12 1990-04-12 半導体装置の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2097383A JPH03295247A (ja) 1990-04-12 1990-04-12 半導体装置の製造方法

Publications (1)

Publication Number Publication Date
JPH03295247A true JPH03295247A (ja) 1991-12-26

Family

ID=14190989

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2097383A Pending JPH03295247A (ja) 1990-04-12 1990-04-12 半導体装置の製造方法

Country Status (1)

Country Link
JP (1) JPH03295247A (ja)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5565378A (en) * 1992-02-17 1996-10-15 Mitsubishi Denki Kabushiki Kaisha Process of passivating a semiconductor device bonding pad by immersion in O2 or O3 solution
EP0753890A3 (en) * 1995-07-14 1997-03-05 Matsushita Electric Ind Co Ltd Electrode structure for semiconductor device, method of making the same, and mounted body comprising a semiconductor device
JP2010114880A (ja) * 2008-11-04 2010-05-20 Samsung Electronics Co Ltd 表面弾性波素子、表面弾性波装置、及びこれらの製造方法

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5565378A (en) * 1992-02-17 1996-10-15 Mitsubishi Denki Kabushiki Kaisha Process of passivating a semiconductor device bonding pad by immersion in O2 or O3 solution
EP0753890A3 (en) * 1995-07-14 1997-03-05 Matsushita Electric Ind Co Ltd Electrode structure for semiconductor device, method of making the same, and mounted body comprising a semiconductor device
US6387794B2 (en) 1995-07-14 2002-05-14 Matsushita Electric Industrial Co., Ltd. Electrode structure for semiconductor device, method for forming the same, mounted body including semiconductor device and semiconductor device
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