DE69011738D1 - Halbleiter-Speichereinrichtung. - Google Patents

Halbleiter-Speichereinrichtung.

Info

Publication number
DE69011738D1
DE69011738D1 DE69011738T DE69011738T DE69011738D1 DE 69011738 D1 DE69011738 D1 DE 69011738D1 DE 69011738 T DE69011738 T DE 69011738T DE 69011738 T DE69011738 T DE 69011738T DE 69011738 D1 DE69011738 D1 DE 69011738D1
Authority
DE
Germany
Prior art keywords
storage device
semiconductor storage
semiconductor
storage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69011738T
Other languages
English (en)
Other versions
DE69011738T2 (de
Inventor
Mitsuru Shimizu
Syuso Fujii
Shozo Saito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Toshiba Electronic Device Solutions Corp
Original Assignee
Toshiba Corp
Toshiba Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Toshiba Microelectronics Corp filed Critical Toshiba Corp
Publication of DE69011738D1 publication Critical patent/DE69011738D1/de
Application granted granted Critical
Publication of DE69011738T2 publication Critical patent/DE69011738T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/145—Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/145—Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor
    • G11C5/146—Substrate bias generators
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
    • G06F2201/81—Threshold
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Dram (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Semiconductor Memories (AREA)
DE69011738T 1989-05-20 1990-04-26 Halbleiter-Speichereinrichtung. Expired - Fee Related DE69011738T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1127524A JPH07105160B2 (ja) 1989-05-20 1989-05-20 半導体記憶装置

Publications (2)

Publication Number Publication Date
DE69011738D1 true DE69011738D1 (de) 1994-09-29
DE69011738T2 DE69011738T2 (de) 1995-02-02

Family

ID=14962149

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69011738T Expired - Fee Related DE69011738T2 (de) 1989-05-20 1990-04-26 Halbleiter-Speichereinrichtung.

Country Status (5)

Country Link
US (1) US5119337A (de)
EP (1) EP0399240B1 (de)
JP (1) JPH07105160B2 (de)
KR (1) KR930004177B1 (de)
DE (1) DE69011738T2 (de)

Families Citing this family (39)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5063304A (en) * 1990-04-27 1991-11-05 Texas Instruments Incorporated Integrated circuit with improved on-chip power supply control
JP3158420B2 (ja) * 1990-08-30 2001-04-23 日本電気株式会社 温度検出回路および温度検出回路を備えた半導体装置
JP3050326B2 (ja) * 1990-11-30 2000-06-12 日本電気株式会社 半導体集積回路
JP3084759B2 (ja) * 1991-01-29 2000-09-04 日本電気株式会社 ダイナミックランダムアクセスメモリ装置
US5315598A (en) * 1991-04-04 1994-05-24 Texas Instruments Incorporated Method to reduce burn-in time and inducing infant failure
KR940004408B1 (ko) * 1991-08-23 1994-05-25 삼성전자 주식회사 반도체 메모리 장치의 자동 스트레스 모드 테스트장치
US5422852A (en) * 1992-02-27 1995-06-06 Texas Instruments Incorporated Method and system for screening logic circuits
US5212442A (en) * 1992-03-20 1993-05-18 Micron Technology, Inc. Forced substrate test mode for packaged integrated circuits
US5353254A (en) * 1992-05-21 1994-10-04 Texas Instruments Incorporated Semiconductor memory device having burn-in test circuit
JP3147991B2 (ja) * 1992-05-25 2001-03-19 株式会社東芝 半導体記憶装置
JP2848117B2 (ja) * 1992-05-27 1999-01-20 日本電気株式会社 半導体記憶回路
JPH0620471A (ja) * 1992-06-30 1994-01-28 Hitachi Ltd ダイナミック型ｒａｍ
JPH0628853A (ja) * 1992-07-08 1994-02-04 Mitsubishi Electric Corp 半導体記憶装置の基板電圧発生回路
KR950003014B1 (ko) * 1992-07-31 1995-03-29 삼성전자 주식회사 반도체 메모리 장치의 번-인 테스트회로 및 번-인 테스트방법
JP2977385B2 (ja) * 1992-08-31 1999-11-15 株式会社東芝 ダイナミックメモリ装置
KR960005387Y1 (ko) * 1992-09-24 1996-06-28 문정환 반도체 메모리의 번 인 테스트(Burn-In Test) 장치
JP3016998B2 (ja) * 1993-09-24 2000-03-06 日本電気株式会社 半導体記憶装置
KR0122100B1 (ko) * 1994-03-10 1997-11-26 김광호 스트레스회로를 가지는 반도체집적회로 및 그 스트레스전압공급방법
JP2822881B2 (ja) * 1994-03-30 1998-11-11 日本電気株式会社 半導体集積回路装置
US5497348A (en) * 1994-05-31 1996-03-05 Texas Instruments Incorporated Burn-in detection circuit
US5619459A (en) * 1995-05-31 1997-04-08 Micron Technology, Inc. On-chip mobile ion contamination test circuit
JP3629308B2 (ja) * 1995-08-29 2005-03-16 株式会社ルネサステクノロジ 半導体装置およびその試験方法
US5905682A (en) * 1997-08-22 1999-05-18 Micron Technology, Inc. Method and apparatus for biasing the substrate of an integrated circuit to an externally adjustable voltage
US6134144A (en) * 1997-09-19 2000-10-17 Integrated Memory Technologies, Inc. Flash memory array
US5949726A (en) * 1998-07-22 1999-09-07 Vanguard International Semiconductor Corporation Bias scheme to reduce burn-in test time for semiconductor memory while preventing junction breakdown
US6563367B1 (en) * 2000-08-16 2003-05-13 Altera Corporation Interconnection switch structures
US6661253B1 (en) 2000-08-16 2003-12-09 Altera Corporation Passgate structures for use in low-voltage applications
JP3866111B2 (ja) * 2002-01-18 2007-01-10 株式会社ルネサステクノロジ 半導体集積回路及びバーンイン方法
US6900650B1 (en) * 2004-03-01 2005-05-31 Transmeta Corporation System and method for controlling temperature during burn-in
US6897671B1 (en) * 2004-03-01 2005-05-24 Transmeta Corporation System and method for reducing heat dissipation during burn-in
JP5528670B2 (ja) * 2004-03-01 2014-06-25 インテレクチュアル ベンチャー ファンディング エルエルシー バーンイン試験に関するシステムおよび方法
US7248988B2 (en) * 2004-03-01 2007-07-24 Transmeta Corporation System and method for reducing temperature variation during burn in
US7292065B2 (en) * 2004-08-03 2007-11-06 Altera Corporation Enhanced passgate structures for reducing leakage current
US7800143B2 (en) * 2006-07-13 2010-09-21 Globalfoundries Inc. Dynamic random access memory with an amplified capacitor
US7679955B2 (en) 2006-08-02 2010-03-16 Advanced Micro Devices, Inc. Semiconductor switching device
JP5135608B2 (ja) * 2007-12-27 2013-02-06 ルネサスエレクトロニクス株式会社 半導体記憶装置
JP5187852B2 (ja) * 2009-03-30 2013-04-24 国立大学法人神戸大学 不良メモリセルの予知診断アーキテクチャーと予知診断方法
CN114487790B (zh) * 2022-04-06 2022-07-22 海光信息技术股份有限公司 老化监测电路、模组、方法及芯片
CN118641921A (zh) * 2023-03-13 2024-09-13 华为技术有限公司 一种芯片老化方法及装置

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55162257A (en) * 1979-06-05 1980-12-17 Fujitsu Ltd Semiconductor element having substrate bias generator circuit
JPS598913B2 (ja) * 1980-04-01 1984-02-28 富士通株式会社 記憶装置
US4527254A (en) * 1982-11-15 1985-07-02 International Business Machines Corporation Dynamic random access memory having separated VDD pads for improved burn-in
JPS59107493A (ja) * 1982-12-09 1984-06-21 Ricoh Co Ltd テスト回路付きｅｐｒｏｍメモリ装置
US4730279A (en) * 1985-03-30 1988-03-08 Kabushiki Kaisha Toshiba Static semiconductor memory device
JPS62114200A (ja) * 1985-11-13 1987-05-25 Mitsubishi Electric Corp 半導体メモリ装置
JPS62136919A (ja) * 1985-12-10 1987-06-19 Mitsubishi Electric Corp ドライバ−回路
JPS62170094A (ja) * 1986-01-21 1987-07-27 Mitsubishi Electric Corp 半導体記憶回路
JPS62229600A (ja) * 1986-03-31 1987-10-08 Toshiba Corp 不揮発性半導体記憶装置
JPS62250593A (ja) * 1986-04-23 1987-10-31 Hitachi Ltd ダイナミツク型ｒａｍ
US4819212A (en) * 1986-05-31 1989-04-04 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device with readout test circuitry
JPS6334796A (ja) * 1986-07-28 1988-02-15 Oki Electric Ind Co Ltd 半導体記憶装置
US4751679A (en) * 1986-12-22 1988-06-14 Motorola, Inc. Gate stress test of a MOS memory

Also Published As

Publication number Publication date
EP0399240A2 (de) 1990-11-28
EP0399240B1 (de) 1994-08-24
US5119337A (en) 1992-06-02
KR930004177B1 (ko) 1993-05-21
EP0399240A3 (de) 1991-07-03
JPH02306493A (ja) 1990-12-19
KR900019039A (ko) 1990-12-22
DE69011738T2 (de) 1995-02-02
JPH07105160B2 (ja) 1995-11-13

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee