DE3889872D1 - Halbleiterspeicheranordnung. - Google Patents

Halbleiterspeicheranordnung.

Info

Publication number
DE3889872D1
DE3889872D1 DE3889872T DE3889872T DE3889872D1 DE 3889872 D1 DE3889872 D1 DE 3889872D1 DE 3889872 T DE3889872 T DE 3889872T DE 3889872 T DE3889872 T DE 3889872T DE 3889872 D1 DE3889872 D1 DE 3889872D1
Authority
DE
Germany
Prior art keywords
memory device
semiconductor memory
semiconductor
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE3889872T
Other languages
English (en)
Inventor
Mitsuru Shimizu
Nobuyuki Ikumi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Toshiba Electronic Device Solutions Corp
Original Assignee
Toshiba Corp
Toshiba Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Toshiba Microelectronics Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE3889872D1 publication Critical patent/DE3889872D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
DE3889872T 1987-12-09 1988-10-26 Halbleiterspeicheranordnung. Expired - Lifetime DE3889872D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62311177A JPH01151095A (ja) 1987-12-09 1987-12-09 半導体メモリ

Publications (1)

Publication Number Publication Date
DE3889872D1 true DE3889872D1 (de) 1994-07-07

Family

ID=18014011

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3889872T Expired - Lifetime DE3889872D1 (de) 1987-12-09 1988-10-26 Halbleiterspeicheranordnung.

Country Status (5)

Country Link
US (1) US4896294A (de)
EP (1) EP0319691B1 (de)
JP (1) JPH01151095A (de)
KR (1) KR920007443B1 (de)
DE (1) DE3889872D1 (de)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5225275A (en) * 1986-07-11 1993-07-06 Kyocera Corporation Method of producing diamond films
JP2591314B2 (ja) * 1989-10-27 1997-03-19 日本電気株式会社 半導体メモリ装置
US5247655A (en) * 1989-11-07 1993-09-21 Chips And Technologies, Inc. Sleep mode refresh apparatus
US4985871A (en) * 1989-11-13 1991-01-15 Chips And Technologies, Inc. Memory controller for using reserved dram addresses for expanded memory space
US5264743A (en) * 1989-12-08 1993-11-23 Hitachi, Ltd. Semiconductor memory operating with low supply voltage
JPH0447587A (ja) * 1990-06-15 1992-02-17 Oki Electric Ind Co Ltd 半導体記憶装置
JP2982920B2 (ja) * 1990-07-10 1999-11-29 三菱電機株式会社 半導体記憶装置
JPH04305889A (ja) * 1991-04-02 1992-10-28 Mitsubishi Electric Corp シーケンシャルアクセスメモリ
JP3096362B2 (ja) * 1992-10-26 2000-10-10 沖電気工業株式会社 シリアルアクセスメモリ
US5414656A (en) * 1994-03-23 1995-05-09 Kenney; Donald M. Low charge consumption memory
JP3789173B2 (ja) * 1996-07-22 2006-06-21 Ｎｅｃエレクトロニクス株式会社 半導体記憶装置及び半導体記憶装置のアクセス方法
US6256221B1 (en) 1998-01-30 2001-07-03 Silicon Aquarius, Inc. Arrays of two-transistor, one-capacitor dynamic random access memory cells with interdigitated bitlines
US5963468A (en) * 1998-01-30 1999-10-05 Silicon Aquarius, Inc. Low latency memories and systems using the same
US7474557B2 (en) 2001-06-29 2009-01-06 International Business Machines Corporation MRAM array and access method thereof
JP2003168287A (ja) 2001-07-24 2003-06-13 Toshiba Corp メモリモジュール、メモリシステム、および、データ転送方法
JP2003197769A (ja) * 2001-12-21 2003-07-11 Mitsubishi Electric Corp 半導体記憶装置
US11740903B2 (en) 2016-04-26 2023-08-29 Onnivation, LLC Computing machine using a matrix space and matrix pointer registers for matrix and array processing
US10600475B2 (en) * 2016-05-18 2020-03-24 Sitaram Yadavalli Method and apparatus for storing and accessing matrices and arrays by columns and rows in a processing unit
US11237828B2 (en) * 2016-04-26 2022-02-01 Onnivation, LLC Secure matrix space with partitions for concurrent use
US11568920B2 (en) * 2017-08-02 2023-01-31 Samsung Electronics Co., Ltd. Dual row-column major dram
CN110600065B (zh) * 2019-08-16 2021-10-08 清华大学 具有对称特性的存储器单元及其构成的阵列电路

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2442131B2 (de) * 1974-09-03 1976-07-08 Siemens AG, 1000 Berlin und 8000 München Dynamisches ein-transistor-speicherelement
JPS57200988A (en) * 1981-06-03 1982-12-09 Nec Corp Storage device
US4554645A (en) * 1983-03-10 1985-11-19 International Business Machines Corporation Multi-port register implementation
JPS618796A (ja) * 1984-06-20 1986-01-16 Nec Corp ダイナミツクメモリ
JPS6250791A (ja) * 1985-08-30 1987-03-05 株式会社日立製作所 ダイナミツク型半導体メモリ装置
US4758988A (en) * 1985-12-12 1988-07-19 Motorola, Inc. Dual array EEPROM for high endurance capability

Also Published As

Publication number Publication date
EP0319691B1 (de) 1994-06-01
US4896294A (en) 1990-01-23
KR920007443B1 (ko) 1992-09-01
EP0319691A3 (en) 1990-12-27
EP0319691A2 (de) 1989-06-14
JPH01151095A (ja) 1989-06-13
KR890010915A (ko) 1989-08-11

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Legal Events

Date Code Title Description
8332 No legal effect for de