DE3889097D1 - Halbleiterspeicheranordnung. - Google Patents

Halbleiterspeicheranordnung.

Info

Publication number
DE3889097D1
DE3889097D1 DE3889097T DE3889097T DE3889097D1 DE 3889097 D1 DE3889097 D1 DE 3889097D1 DE 3889097 T DE3889097 T DE 3889097T DE 3889097 T DE3889097 T DE 3889097T DE 3889097 D1 DE3889097 D1 DE 3889097D1
Authority
DE
Germany
Prior art keywords
memory device
semiconductor memory
semiconductor
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE3889097T
Other languages
English (en)
Other versions
DE3889097T2 (de
Inventor
Akira C O Patent Div Yamaguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Publication of DE3889097D1 publication Critical patent/DE3889097D1/de
Application granted granted Critical
Publication of DE3889097T2 publication Critical patent/DE3889097T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/16—Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
DE3889097T 1988-01-07 1988-12-30 Halbleiterspeicheranordnung. Expired - Fee Related DE3889097T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63001659A JPH01178193A (ja) 1988-01-07 1988-01-07 半導体記憶装置

Publications (2)

Publication Number Publication Date
DE3889097D1 true DE3889097D1 (de) 1994-05-19
DE3889097T2 DE3889097T2 (de) 1994-07-28

Family

ID=11507650

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3889097T Expired - Fee Related DE3889097T2 (de) 1988-01-07 1988-12-30 Halbleiterspeicheranordnung.

Country Status (5)

Country Link
US (1) US5036491A (de)
EP (1) EP0323648B1 (de)
JP (1) JPH01178193A (de)
KR (1) KR920008055B1 (de)
DE (1) DE3889097T2 (de)

Families Citing this family (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03137900A (ja) * 1989-07-27 1991-06-12 Nec Corp 不揮発性半導体メモリ
EP0439952A3 (en) * 1990-01-31 1992-09-09 Sgs-Thomson Microelectronics, Inc. Dual-port cache tag memory
JP2604277B2 (ja) * 1990-02-28 1997-04-30 三菱電機株式会社 ダイナミック・ランダム・アクセス・メモリ
US5142540A (en) * 1990-03-13 1992-08-25 Glasser Lance A Multipart memory apparatus with error detection
JPH0821237B2 (ja) * 1990-06-27 1996-03-04 株式会社東芝 半導体記憶装置
JP3078000B2 (ja) * 1990-07-24 2000-08-21 三菱電機株式会社 情報処理装置
JPH04257048A (ja) * 1991-02-12 1992-09-11 Mitsubishi Electric Corp デュアルポートメモリ
JP3101336B2 (ja) * 1991-02-22 2000-10-23 富士通株式会社 半導体集積記憶回路
US5267199A (en) * 1991-06-28 1993-11-30 Digital Equipment Corporation Apparatus for simultaneous write access to a single bit memory
KR930005199A (ko) * 1991-08-30 1993-03-23 가나이 쓰토무 반도체 기억장치
US5282174A (en) * 1992-01-31 1994-01-25 At&T Bell Laboratories Dual-port memory with read and read/write ports
JPH05266654A (ja) * 1992-03-17 1993-10-15 Mitsubishi Electric Corp マルチポートメモリ装置
JPH0612107A (ja) * 1992-06-02 1994-01-21 Mitsubishi Electric Corp シーケンス演算プロセッサおよびシーケンス演算処理装置
US5502683A (en) * 1993-04-20 1996-03-26 International Business Machines Corporation Dual ported memory with word line access control
US5737569A (en) * 1993-06-30 1998-04-07 Intel Corporation Multiport high speed memory having contention arbitration capability without standby delay
US5375089A (en) * 1993-10-05 1994-12-20 Advanced Micro Devices, Inc. Plural port memory system utilizing a memory having a read port and a write port
WO1997027592A1 (en) * 1996-01-24 1997-07-31 Cypress Semiconductor Corporation Interdigitated memory array
US5781480A (en) * 1997-07-29 1998-07-14 Motorola, Inc. Pipelined dual port integrated circuit memory
US6118727A (en) * 1998-03-10 2000-09-12 Cypress Semiconductor Corporation Semiconductor memory with interdigitated array having bit line pairs accessible from either of two sides of the array
JP3226886B2 (ja) * 1999-01-29 2001-11-05 エヌイーシーマイクロシステム株式会社 半導体記憶装置とその制御方法
US6163495A (en) 1999-09-17 2000-12-19 Cypress Semiconductor Corp. Architecture, method(s) and circuitry for low power memories
US7120761B2 (en) * 2000-12-20 2006-10-10 Fujitsu Limited Multi-port memory based on DRAM core
JP2002314166A (ja) * 2001-04-16 2002-10-25 Nec Corp 磁気抵抗効果素子及びその製造方法
US6778466B2 (en) 2002-04-11 2004-08-17 Fujitsu Limited Multi-port memory cell
US8397034B1 (en) 2003-06-27 2013-03-12 Cypress Semiconductor Corporation Multi-port arbitration system and method
US7516280B1 (en) 2004-03-30 2009-04-07 Cypress Semiconductor Corporation Pulsed arbitration system and method
JP4662532B2 (ja) * 2004-06-03 2011-03-30 パナソニック株式会社 半導体記憶装置
JP4731152B2 (ja) * 2004-10-29 2011-07-20 ルネサスエレクトロニクス株式会社 半導体記憶装置
US7813213B1 (en) 2005-05-04 2010-10-12 Cypress Semiconductor Corporation Pulsed arbitration system
US7692974B2 (en) * 2007-09-26 2010-04-06 Infineon Technologies Ag Memory cell, memory device, device and method of accessing a memory cell
US8861289B2 (en) * 2013-01-14 2014-10-14 Freescale Semiconductor, Inc. Multiport memory with matching address control
US8867263B2 (en) * 2013-01-14 2014-10-21 Freescale Semiconductor, Inc. Multiport memory with matching address and data line control
JP6122170B1 (ja) * 2016-03-16 2017-04-26 株式会社東芝 不揮発性ｒａｍ及び不揮発性ｒａｍを含むシステム

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4104719A (en) * 1976-05-20 1978-08-01 The United States Of America As Represented By The Secretary Of The Navy Multi-access memory module for data processing systems
JPS58130494A (ja) * 1982-01-29 1983-08-03 Fujitsu Ltd マルチポ−トｄ−ｒａｍ
JPS59198585A (ja) * 1983-04-22 1984-11-10 Nec Corp マルチアクセス記憶装置
US4616347A (en) * 1983-05-31 1986-10-07 International Business Machines Corporation Multi-port system
US4577292A (en) * 1983-05-31 1986-03-18 International Business Machines Corporation Support circuitry for multi-port systems
US4599708A (en) * 1983-12-30 1986-07-08 International Business Machines Corporation Method and structure for machine data storage with simultaneous write and read
JPS618791A (ja) * 1984-06-20 1986-01-16 Nec Corp スタテイツク半導体メモリ
JPS61202396A (ja) * 1985-03-05 1986-09-08 Nec Corp デユアルポ−ト型ダイナミツク・ランダム・アクセス・メモリ
JPS62128341A (ja) * 1985-11-29 1987-06-10 Yokogawa Electric Corp ２ポ−トメモリへのアクセス制御方式
JPH0636314B2 (ja) * 1985-12-20 1994-05-11 日本電気株式会社 半導体記憶装置
US4742487A (en) * 1986-04-15 1988-05-03 International Business Machines Corporation Inhibit and transfer circuitry for memory cell being read from multiple ports
JPS62287497A (ja) * 1986-06-06 1987-12-14 Fujitsu Ltd 半導体記憶装置
JP2615088B2 (ja) * 1987-11-06 1997-05-28 株式会社日立製作所 半導体記憶装置

Also Published As

Publication number Publication date
EP0323648A2 (de) 1989-07-12
EP0323648B1 (de) 1994-04-13
KR920008055B1 (ko) 1992-09-22
EP0323648A3 (de) 1991-03-20
US5036491A (en) 1991-07-30
KR890012312A (ko) 1989-08-25
DE3889097T2 (de) 1994-07-28
JPH01178193A (ja) 1989-07-14

Similar Documents

Publication Publication Date Title
NL191814C (nl) Halfgeleidergeheugeninrichting.
DE3889097D1 (de) Halbleiterspeicheranordnung.
DE68923505D1 (de) Halbleiterspeicheranordnung.
DE68911044D1 (de) Halbleiterspeicher.
DE68918367D1 (de) Halbleiterspeicheranordnung.
DE3887224T2 (de) Halbleiterspeicheranordnung.
DE3884022T2 (de) Halbleiterspeicheranordnung.
DE69022537D1 (de) Halbleiterspeicheranordnung.
DE68923588T2 (de) Halbleiterspeicheranordnung.
DE3889872D1 (de) Halbleiterspeicheranordnung.
DE68918193D1 (de) Halbleiterspeicher.
DE69017518T2 (de) Halbleiterspeicheranordnung.
DE3865702D1 (de) Halbleiter-festwertspeichereinrichtung.
DE68924080T2 (de) Halbleiterspeichervorrichtung.
DE68923899D1 (de) Halbleiterspeicher.
DE3853437D1 (de) Halbleiterspeicheranordnung.
DE69023594T2 (de) Halbleiterspeicheranordnung.
DE3883822D1 (de) Halbleiterspeichervorrichtung.
DE69024000D1 (de) Halbleiterspeicheranordnung.
DE69016577T2 (de) Halbleiterspeicheranordnung.
DE69023587T2 (de) Halbleiterspeicheranordnung.
DE69022508D1 (de) Halbleiterspeicheranordnung.
DE69015746T2 (de) Halbleiterspeicheranordnung.
DE68914068D1 (de) Halbleiterspeicher.
DE69018841T2 (de) Halbleiterspeicheranordnung.

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee