DE69022537D1 - Halbleiterspeicheranordnung. - Google Patents

Halbleiterspeicheranordnung.

Info

Publication number
DE69022537D1
DE69022537D1 DE69022537T DE69022537T DE69022537D1 DE 69022537 D1 DE69022537 D1 DE 69022537D1 DE 69022537 T DE69022537 T DE 69022537T DE 69022537 T DE69022537 T DE 69022537T DE 69022537 D1 DE69022537 D1 DE 69022537D1
Authority
DE
Germany
Prior art keywords
memory device
semiconductor memory
semiconductor
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69022537T
Other languages
English (en)
Other versions
DE69022537T2 (de
Inventor
Kenichi Nakamura
Makoto Segawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE69022537D1 publication Critical patent/DE69022537D1/de
Publication of DE69022537T2 publication Critical patent/DE69022537T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/106—Data output latches
DE69022537T 1989-11-10 1990-11-09 Halbleiterspeicheranordnung. Expired - Fee Related DE69022537T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1292992A JP2534782B2 (ja) 1989-11-10 1989-11-10 半導体装置

Publications (2)

Publication Number Publication Date
DE69022537D1 true DE69022537D1 (de) 1995-10-26
DE69022537T2 DE69022537T2 (de) 1996-04-11

Family

ID=17789073

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69022537T Expired - Fee Related DE69022537T2 (de) 1989-11-10 1990-11-09 Halbleiterspeicheranordnung.

Country Status (5)

Country Link
US (1) US5043944A (de)
EP (1) EP0427286B1 (de)
JP (1) JP2534782B2 (de)
KR (1) KR930011785B1 (de)
DE (1) DE69022537T2 (de)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5311471A (en) * 1989-11-27 1994-05-10 Kabushiki Kaisha Toshiba Semiconductor memory device
JP2573392B2 (ja) * 1990-03-30 1997-01-22 株式会社東芝 半導体記憶装置
US5281865A (en) * 1990-11-28 1994-01-25 Hitachi, Ltd. Flip-flop circuit
JPH04214290A (ja) * 1990-12-12 1992-08-05 Mitsubishi Electric Corp 半導体記憶装置
US5255222A (en) * 1991-01-23 1993-10-19 Ramtron International Corporation Output control circuit having continuously variable drive current
JP2977296B2 (ja) * 1991-02-19 1999-11-15 沖電気工業株式会社 半導体メモリ装置
JPH05101201A (ja) * 1991-10-09 1993-04-23 Rohm Co Ltd オプシヨン設定回路
KR940010838B1 (ko) * 1991-10-28 1994-11-17 삼성전자 주식회사 데이타 출력 콘트롤 회로
US5327317A (en) * 1991-12-13 1994-07-05 Micron Technology, Inc. Self-terminating data line driver
US5694361A (en) * 1992-03-18 1997-12-02 Uchida; Toshiya Output circuit
KR0147398B1 (ko) * 1992-10-09 1998-12-01 로오라 케이 니퀴스트 랜덤 액세스 메모리
JP3317746B2 (ja) * 1993-06-18 2002-08-26 富士通株式会社 半導体記憶装置
JPH0883491A (ja) * 1994-09-13 1996-03-26 Mitsubishi Denki Eng Kk データ読出回路
JP3067094B2 (ja) * 1995-02-22 2000-07-17 三洋電機株式会社 光再生装置
US5914899A (en) * 1995-07-05 1999-06-22 Kabushiki Kaisha Toshiba Semiconductor memory having a page mode in which previous data in an output circuit is reset before new data is supplied
JPH0922593A (ja) * 1995-07-05 1997-01-21 Toshiba Microelectron Corp 半導体メモリ
JP3192077B2 (ja) * 1996-01-30 2001-07-23 日本電気株式会社 半導体記憶装置
US5784329A (en) * 1997-01-13 1998-07-21 Mitsubishi Semiconductor America, Inc. Latched DRAM write bus for quickly clearing DRAM array with minimum power usage
US5864244A (en) * 1997-05-09 1999-01-26 Kaplinsky; Cecil H. Tristate buffer circuit with transparent latching capability
JP3808623B2 (ja) * 1998-04-27 2006-08-16 株式会社東芝 データ入出力回路、半導体記憶装置および情報処理装置
JP3573701B2 (ja) * 2000-09-14 2004-10-06 Ｎｅｃエレクトロニクス株式会社 出力バッファ回路
DE102004053486B4 (de) * 2004-11-05 2011-06-22 Qimonda AG, 81739 Integrierter Halbleiterspeicher und Verfahren zum Betreiben eines integrierten Halbleiterspeichers
JP4104634B2 (ja) * 2006-05-23 2008-06-18 シャープ株式会社 半導体装置

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2945331C2 (de) * 1979-11-09 1984-05-30 Nixdorf Computer Ag, 4790 Paderborn Vorrichtung in einer Signal-oder Datenverarbeitungsanlage zur Einstellung einer Signalverarbeitungsschaltung
JPS58169383A (ja) * 1982-03-30 1983-10-05 Fujitsu Ltd 半導体記憶装置
JPS596560Y2 (ja) * 1982-11-30 1984-02-29 モトロ−ラ・インコ−ポレ−テツド 集積回路用ｆｅｔメモリのセンス増幅回路
JPS59110091A (ja) * 1982-12-14 1984-06-25 Nec Corp 出力回路
US4603403A (en) * 1983-05-17 1986-07-29 Kabushiki Kaisha Toshiba Data output circuit for dynamic memory device
JPS60119691A (ja) * 1983-11-30 1985-06-27 Nec Corp メモリ回路
US4766572A (en) * 1984-12-27 1988-08-23 Nec Corporation Semiconductor memory having a bypassable data output latch
US4817054A (en) * 1985-12-04 1989-03-28 Advanced Micro Devices, Inc. High speed RAM based data serializers
JPS62167698A (ja) * 1986-01-20 1987-07-24 Fujitsu Ltd 半導体記億装置
JPH0612632B2 (ja) * 1987-02-27 1994-02-16 日本電気株式会社 メモリ回路
JP2569538B2 (ja) * 1987-03-17 1997-01-08 ソニー株式会社 メモリ装置

Also Published As

Publication number Publication date
EP0427286B1 (de) 1995-09-20
JPH03154290A (ja) 1991-07-02
JP2534782B2 (ja) 1996-09-18
KR910010506A (ko) 1991-06-29
KR930011785B1 (ko) 1993-12-21
US5043944A (en) 1991-08-27
DE69022537T2 (de) 1996-04-11
EP0427286A3 (de) 1994-01-05
EP0427286A2 (de) 1991-05-15

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee