DE3853437T2 - Halbleiterspeicheranordnung. - Google Patents

Halbleiterspeicheranordnung.

Info

Publication number
DE3853437T2
DE3853437T2 DE3853437T DE3853437T DE3853437T2 DE 3853437 T2 DE3853437 T2 DE 3853437T2 DE 3853437 T DE3853437 T DE 3853437T DE 3853437 T DE3853437 T DE 3853437T DE 3853437 T2 DE3853437 T2 DE 3853437T2
Authority
DE
Germany
Prior art keywords
memory device
semiconductor memory
semiconductor
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE3853437T
Other languages
English (en)
Other versions
DE3853437D1 (de
Inventor
Junji Ogawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE3853437D1 publication Critical patent/DE3853437D1/de
Publication of DE3853437T2 publication Critical patent/DE3853437T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0207—Addressing or allocation; Relocation with multidimensional access, e.g. row/column, matrix
DE3853437T 1987-01-19 1988-01-18 Halbleiterspeicheranordnung. Expired - Fee Related DE3853437T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62009494A JPS63177235A (ja) 1987-01-19 1987-01-19 多次元アクセスメモリ

Publications (2)

Publication Number Publication Date
DE3853437D1 DE3853437D1 (de) 1995-05-04
DE3853437T2 true DE3853437T2 (de) 1995-07-27

Family

ID=11721789

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3853437T Expired - Fee Related DE3853437T2 (de) 1987-01-19 1988-01-18 Halbleiterspeicheranordnung.

Country Status (5)

Country Link
US (1) US4896301A (de)
EP (1) EP0276110B1 (de)
JP (1) JPS63177235A (de)
KR (1) KR910000151B1 (de)
DE (1) DE3853437T2 (de)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0682339B2 (ja) * 1990-08-31 1994-10-19 インターナショナル・ビジネス・マシーンズ・コーポレイション メモリ・アクセス・システムおよび方法
DE69123952T2 (de) * 1990-12-17 1997-04-30 Hewlett Packard Co Rechneradressierungseinrichtung
US5361339A (en) * 1992-05-04 1994-11-01 Xerox Corporation Circuit for fast page mode addressing of a RAM with multiplexed row and column address lines
US5357477A (en) * 1992-05-18 1994-10-18 Matsushita Electric Industrial Co., Ltd. Semiconductor memory having multiple data I/O with bit aligned access function
US5894515A (en) * 1995-08-14 1999-04-13 United Microelectronics Corporation Random access memory device having inconsistent write-in and read-out data
KR100299872B1 (ko) * 1998-06-29 2001-10-27 박종섭 다비트데이터기록제어회로
US8060756B2 (en) * 2003-08-07 2011-11-15 Rao G R Mohan Data security and digital rights management system
GB2487723A (en) * 2011-01-26 2012-08-08 Nds Ltd Protection device for stored data values comprising a switching circuit
KR20130048999A (ko) * 2011-11-03 2013-05-13 삼성전자주식회사 반도체 테스트 장치 및 그의 어드레스 스크램블 생성 방법
KR102091524B1 (ko) 2018-07-23 2020-03-23 삼성전자주식회사 어드레스를 스크램블하는 메모리 장치

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5919367A (ja) * 1982-07-26 1984-01-31 Toshiba Corp メモリ付ゲ−トアレイ
DD208499A3 (de) * 1982-10-26 1984-05-02 Adw Ddr Mehrdimensionaler paralleler speicher
US4559611A (en) * 1983-06-30 1985-12-17 International Business Machines Corporation Mapping and memory hardware for writing horizontal and vertical lines
US4594587A (en) * 1983-08-30 1986-06-10 Zenith Electronics Corporation Character oriented RAM mapping system and method therefor
JPS60113396A (ja) * 1983-11-25 1985-06-19 Toshiba Corp メモリｌｓｉ
US4688197A (en) * 1983-12-30 1987-08-18 Texas Instruments Incorporated Control of data access to memory for improved video system
JPS61175998A (ja) * 1985-01-29 1986-08-07 Nec Corp リ−ドオンリメモリ回路
JPS61235958A (ja) * 1985-04-12 1986-10-21 Mitsubishi Electric Corp 画像記憶装置
CA1259680A (en) * 1986-05-06 1989-09-19 Mosaid Technologies Inc. Digital signal scrambler
US4811297A (en) * 1986-12-16 1989-03-07 Fujitsu Limited Boundary-free semiconductor memory device

Also Published As

Publication number Publication date
KR880009371A (ko) 1988-09-14
US4896301A (en) 1990-01-23
EP0276110A2 (de) 1988-07-27
EP0276110A3 (de) 1991-08-21
EP0276110B1 (de) 1995-03-29
JPS63177235A (ja) 1988-07-21
KR910000151B1 (ko) 1991-01-21
DE3853437D1 (de) 1995-05-04

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee