DE3787616T2 - Halbleiterspeicheranordnung. - Google Patents

Halbleiterspeicheranordnung.

Info

Publication number
DE3787616T2
DE3787616T2 DE87117482T DE3787616T DE3787616T2 DE 3787616 T2 DE3787616 T2 DE 3787616T2 DE 87117482 T DE87117482 T DE 87117482T DE 3787616 T DE3787616 T DE 3787616T DE 3787616 T2 DE3787616 T2 DE 3787616T2
Authority
DE
Germany
Prior art keywords
memory device
semiconductor memory
semiconductor
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE87117482T
Other languages
English (en)
Other versions
DE3787616D1 (de
Inventor
Takashi C O Patent Divi Ohsawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Publication of DE3787616D1 publication Critical patent/DE3787616D1/de
Application granted granted Critical
Publication of DE3787616T2 publication Critical patent/DE3787616T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/103—Read-write modes for single port memories, i.e. having either a random port or a serial port using serially addressed read-write data registers
    • G11C7/1033—Read-write modes for single port memories, i.e. having either a random port or a serial port using serially addressed read-write data registers using data registers of which only one stage is addressed for sequentially outputting data from a predetermined number of stages, e.g. nibble read-write mode
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising
DE87117482T 1986-11-27 1987-11-26 Halbleiterspeicheranordnung. Expired - Fee Related DE3787616T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61280595A JPS63239675A (ja) 1986-11-27 1986-11-27 半導体記憶装置

Publications (2)

Publication Number Publication Date
DE3787616D1 DE3787616D1 (de) 1993-11-04
DE3787616T2 true DE3787616T2 (de) 1994-03-10

Family

ID=17627222

Family Applications (1)

Application Number Title Priority Date Filing Date
DE87117482T Expired - Fee Related DE3787616T2 (de) 1986-11-27 1987-11-26 Halbleiterspeicheranordnung.

Country Status (4)

Country Link
US (1) US4802132A (de)
EP (1) EP0269106B1 (de)
JP (1) JPS63239675A (de)
DE (1) DE3787616T2 (de)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01130240A (ja) * 1987-11-16 1989-05-23 Yokogawa Hewlett Packard Ltd データ列発生装置
US4935901A (en) * 1987-02-23 1990-06-19 Hitachi, Ltd. Semiconductor memory with divided bit load and data bus lines
US5172335A (en) * 1987-02-23 1992-12-15 Hitachi, Ltd. Semiconductor memory with divided bit load and data bus lines
US5274596A (en) * 1987-09-16 1993-12-28 Kabushiki Kaisha Toshiba Dynamic semiconductor memory device having simultaneous operation of adjacent blocks
US5329489A (en) * 1988-03-31 1994-07-12 Texas Instruments Incorporated DRAM having exclusively enabled column buffer blocks
JP2628194B2 (ja) * 1988-07-28 1997-07-09 株式会社日立製作所 データ処理装置
KR930007185B1 (ko) * 1989-01-13 1993-07-31 가부시키가이샤 도시바 레지스터뱅크회로
JPH0814985B2 (ja) * 1989-06-06 1996-02-14 富士通株式会社 半導体記憶装置
JP2820462B2 (ja) * 1989-10-31 1998-11-05 日本ヒューレット・パッカード株式会社 データ列発生装置
US5105105A (en) * 1990-03-21 1992-04-14 Thunderbird Technologies, Inc. High speed logic and memory family using ring segment buffer
US5030853A (en) * 1990-03-21 1991-07-09 Thunderbird Technologies, Inc. High speed logic and memory family using ring segment buffer
US5454115A (en) * 1991-12-25 1995-09-26 Sharp Kabushiki Kaisha Data driven type processor having data flow program divided into plurality of simultaneously executable program groups for an N:1 read-out to memory-access ratio
US5270964A (en) * 1992-05-19 1993-12-14 Sun Microsystems, Inc. Single in-line memory module
US5305281A (en) * 1992-08-06 1994-04-19 National Semiconductor Corporation Multiple array memory device with staggered read/write for high speed data access
JP2825401B2 (ja) * 1992-08-28 1998-11-18 株式会社東芝 半導体記憶装置
US5539696A (en) * 1994-01-31 1996-07-23 Patel; Vipul C. Method and apparatus for writing data in a synchronous memory having column independent sections and a method and apparatus for performing write mask operations
KR0141665B1 (ko) * 1994-03-31 1998-07-15 김광호 비디오램 및 시리얼데이타 출력방법
US5953411A (en) * 1996-12-18 1999-09-14 Intel Corporation Method and apparatus for maintaining audio sample correlation
DE19961727A1 (de) 1999-12-21 2001-07-05 Micronas Gmbh Schaltungsanordnung mit einer Datenübertragungsvorrichtung
KR102455427B1 (ko) * 2017-12-20 2022-10-17 삼성전자주식회사 반도체 패키지 및 이의 제조 방법

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57150190A (en) * 1981-02-27 1982-09-16 Hitachi Ltd Monolithic storage device
JPS5956284A (ja) * 1982-09-24 1984-03-31 Hitachi Micro Comput Eng Ltd 半導体記憶装置
EP0125699A3 (de) * 1983-05-17 1986-10-08 Kabushiki Kaisha Toshiba Datenausgabeanordnung für einen dynamischen Speicher
US4630240A (en) * 1984-07-02 1986-12-16 Texas Instruments Incorporated Dynamic memory with intermediate column derode
US4658377A (en) * 1984-07-26 1987-04-14 Texas Instruments Incorporated Dynamic memory array with segmented bit lines
US4608670A (en) * 1984-08-02 1986-08-26 Texas Instruments Incorporated CMOS sense amplifier with N-channel sensing
US4685088A (en) * 1985-04-15 1987-08-04 International Business Machines Corporation High performance memory system utilizing pipelining techniques

Also Published As

Publication number Publication date
JPH0524590B2 (de) 1993-04-08
EP0269106A2 (de) 1988-06-01
EP0269106A3 (en) 1990-07-04
JPS63239675A (ja) 1988-10-05
DE3787616D1 (de) 1993-11-04
EP0269106B1 (de) 1993-09-29
US4802132A (en) 1989-01-31

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee