DE69023258T2 - Halbleiter-Speichereinrichtung. - Google Patents

Halbleiter-Speichereinrichtung.

Info

Publication number
DE69023258T2
DE69023258T2 DE69023258T DE69023258T DE69023258T2 DE 69023258 T2 DE69023258 T2 DE 69023258T2 DE 69023258 T DE69023258 T DE 69023258T DE 69023258 T DE69023258 T DE 69023258T DE 69023258 T2 DE69023258 T2 DE 69023258T2
Authority
DE
Germany
Prior art keywords
storage device
semiconductor storage
semiconductor
storage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69023258T
Other languages
English (en)
Other versions
DE69023258D1 (de
Inventor
Michiharu Shikata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Application granted granted Critical
Publication of DE69023258D1 publication Critical patent/DE69023258D1/de
Publication of DE69023258T2 publication Critical patent/DE69023258T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/109—Control signal input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/103—Read-write modes for single port memories, i.e. having either a random port or a serial port using serially addressed read-write data registers
    • G11C7/1033—Read-write modes for single port memories, i.e. having either a random port or a serial port using serially addressed read-write data registers using data registers of which only one stage is addressed for sequentially outputting data from a predetermined number of stages, e.g. nibble read-write mode
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1087—Data input latches
DE69023258T 1989-03-15 1990-03-14 Halbleiter-Speichereinrichtung. Expired - Fee Related DE69023258T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6253489 1989-03-15

Publications (2)

Publication Number Publication Date
DE69023258D1 DE69023258D1 (de) 1995-12-07
DE69023258T2 true DE69023258T2 (de) 1996-05-15

Family

ID=13202972

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69023258T Expired - Fee Related DE69023258T2 (de) 1989-03-15 1990-03-14 Halbleiter-Speichereinrichtung.

Country Status (3)

Country Link
US (1) US5088062A (de)
EP (1) EP0388175B1 (de)
DE (1) DE69023258T2 (de)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2891504B2 (ja) * 1990-03-13 1999-05-17 三菱電機株式会社 マルチポートメモリ
JP2604276B2 (ja) * 1990-11-20 1997-04-30 三菱電機株式会社 半導体記憶装置
US5530955A (en) * 1991-04-01 1996-06-25 Matsushita Electric Industrial Co., Ltd. Page memory device capable of short cycle access of different pages by a plurality of data processors
US5355335A (en) * 1991-06-25 1994-10-11 Fujitsu Limited Semiconductor memory device having a plurality of writing and reading ports for decreasing hardware amount
US5587964A (en) * 1991-06-28 1996-12-24 Digital Equipment Corporation Page mode and nibble mode DRAM
JP2696026B2 (ja) * 1991-11-21 1998-01-14 株式会社東芝 半導体記憶装置
SG49816A1 (en) * 1992-07-02 1998-06-15 Rafael C Camarota Non-disruptive randomly addressable memory system
KR960001790B1 (ko) * 1993-04-09 1996-02-05 현대전자산업주식회사 데이타 출력버퍼
JPH07312100A (ja) * 1994-05-17 1995-11-28 Seiko Instr Inc 半導体メモリ集積回路
US6005811A (en) * 1994-08-17 1999-12-21 Oak Technology, Incorporated Method for operating a memory
US5500819A (en) * 1994-09-30 1996-03-19 Cirrus Logic, Inc. Circuits, systems and methods for improving page accesses and block transfers in a memory system
US5734620A (en) * 1995-04-05 1998-03-31 Micron Technology, Inc. Hierarchical memory array structure with redundant components having electrically isolated bit lines
US5600602A (en) * 1995-04-05 1997-02-04 Micron Technology, Inc. Hierarchical memory array structure having electrically isolated bit lines for temporary data storage
US6209071B1 (en) 1996-05-07 2001-03-27 Rambus Inc. Asynchronous request/synchronous data dynamic random access memory
US6263448B1 (en) 1997-10-10 2001-07-17 Rambus Inc. Power control system for synchronous memory device
JP3090104B2 (ja) * 1997-10-27 2000-09-18 日本電気株式会社 半導体メモリ装置
US5963482A (en) * 1998-07-14 1999-10-05 Winbond Electronics Corp. Memory integrated circuit with shared read/write line
US7715377B2 (en) * 2002-01-03 2010-05-11 Integrated Device Technology, Inc. Apparatus and method for matrix memory switching element

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4344156A (en) * 1980-10-10 1982-08-10 Inmos Corporation High speed data transfer for a semiconductor memory
JPS57167186A (en) * 1981-04-08 1982-10-14 Nec Corp Memory circuit
US4633429A (en) * 1982-12-27 1986-12-30 Motorola, Inc. Partial memory selection using a programmable decoder
JPH069114B2 (ja) * 1983-06-24 1994-02-02 株式会社東芝 半導体メモリ
US4719602A (en) * 1985-02-07 1988-01-12 Visic, Inc. Memory with improved column access
JPS62139198A (ja) * 1985-12-11 1987-06-22 Mitsubishi Electric Corp 半導体記憶装置
JPS63184987A (ja) * 1987-01-28 1988-07-30 Nec Corp 半導体記憶装置
US4789960A (en) * 1987-01-30 1988-12-06 Rca Licensing Corporation Dual port video memory system having semi-synchronous data input and data output
JPH0760594B2 (ja) * 1987-06-25 1995-06-28 富士通株式会社 半導体記憶装置
JP2545416B2 (ja) * 1987-11-21 1996-10-16 株式会社日立製作所 半導体メモリ
US5003475A (en) * 1988-11-25 1991-03-26 Picker International, Inc. Medical imaging system including means to increase data transfer speeds by simultaneously transferring data from latches to registers and from registers to latches
US4954987A (en) * 1989-07-17 1990-09-04 Advanced Micro Devices, Inc. Interleaved sensing system for FIFO and burst-mode memories

Also Published As

Publication number Publication date
EP0388175B1 (de) 1995-11-02
EP0388175A3 (de) 1993-02-03
DE69023258D1 (de) 1995-12-07
EP0388175A2 (de) 1990-09-19
US5088062A (en) 1992-02-11

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee