DE69015746D1 - Halbleiterspeicheranordnung. - Google Patents

Halbleiterspeicheranordnung.

Info

Publication number
DE69015746D1
DE69015746D1 DE69015746T DE69015746T DE69015746D1 DE 69015746 D1 DE69015746 D1 DE 69015746D1 DE 69015746 T DE69015746 T DE 69015746T DE 69015746 T DE69015746 T DE 69015746T DE 69015746 D1 DE69015746 D1 DE 69015746D1
Authority
DE
Germany
Prior art keywords
memory device
semiconductor memory
semiconductor
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69015746T
Other languages
English (en)
Other versions
DE69015746T2 (de
Inventor
Yoshiaki Takeuchi
Masaru Koyanagi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE69015746D1 publication Critical patent/DE69015746D1/de
Publication of DE69015746T2 publication Critical patent/DE69015746T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/485—Bit line contacts
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/18—Bit line organisation; Bit line lay-out
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/315—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Dram (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)
DE69015746T 1989-09-21 1990-09-21 Halbleiterspeicheranordnung. Expired - Fee Related DE69015746T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1245566A JP2609727B2 (ja) 1989-09-21 1989-09-21 半導体集積回路

Publications (2)

Publication Number Publication Date
DE69015746D1 true DE69015746D1 (de) 1995-02-16
DE69015746T2 DE69015746T2 (de) 1995-06-01

Family

ID=17135618

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69015746T Expired - Fee Related DE69015746T2 (de) 1989-09-21 1990-09-21 Halbleiterspeicheranordnung.

Country Status (5)

Country Link
US (1) US5168462A (de)
EP (1) EP0418911B1 (de)
JP (1) JP2609727B2 (de)
KR (1) KR940005800B1 (de)
DE (1) DE69015746T2 (de)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100271788B1 (ko) * 1997-10-30 2000-11-15 김영환 디램의비트라인프리차지회로의레이아웃
US5963494A (en) * 1998-07-31 1999-10-05 Lg Semicon Co., Ltd. Semiconductor memory having bitline precharge circuit
KR100482486B1 (ko) * 2001-12-06 2005-04-14 기아자동차주식회사 차량의 윈도우 레귤레이터

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3942164A (en) * 1975-01-30 1976-03-02 Semi, Inc. Sense line coupling reduction system
JPH0666442B2 (ja) * 1985-03-08 1994-08-24 三菱電機株式会社 半導体メモリ装置
JPS63897A (ja) * 1986-06-19 1988-01-05 Fujitsu Ltd 半導体記憶装置
JPS63133394A (ja) * 1986-11-21 1988-06-06 Nec Ic Microcomput Syst Ltd 半導体記憶装置

Also Published As

Publication number Publication date
DE69015746T2 (de) 1995-06-01
JPH03108184A (ja) 1991-05-08
EP0418911B1 (de) 1995-01-04
JP2609727B2 (ja) 1997-05-14
EP0418911A3 (en) 1991-08-21
EP0418911A2 (de) 1991-03-27
KR940005800B1 (ko) 1994-06-23
KR910007123A (ko) 1991-04-30
US5168462A (en) 1992-12-01

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8320 Willingness to grant licences declared (paragraph 23)
8339 Ceased/non-payment of the annual fee