JPS57200988A - Storage device - Google Patents

Storage device

Info

Publication number
JPS57200988A
JPS57200988A JP56085392A JP8539281A JPS57200988A JP S57200988 A JPS57200988 A JP S57200988A JP 56085392 A JP56085392 A JP 56085392A JP 8539281 A JP8539281 A JP 8539281A JP S57200988 A JPS57200988 A JP S57200988A
Authority
JP
Japan
Prior art keywords
drain
source
fet
word lines
lines
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56085392A
Other languages
Japanese (ja)
Inventor
Nobuyuki Yasuoka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP56085392A priority Critical patent/JPS57200988A/en
Publication of JPS57200988A publication Critical patent/JPS57200988A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/16—Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Dram (AREA)

Abstract

PURPOSE:To shorten a processing time, by connecting the drain and the source of 2 FETs, grounding them through a capacitive load, and connecting the gate and other terminal of each FET to the first and second word lines and digit lines. CONSTITUTION:The drain or the source of the first FET 113 is connected to the source or the drain of the second FET 115, is grounded through a capacitive load 114, also each gate, and the source and the drain are connected to the first and second word lines 111, 121, and the first and second digit lines 112, 122, respectively, of which a storage unit B is constituted. This storage unit B is placed like an array, the first and second word lines and the digit lines are connected in common, and a storage array is constituted. In this way, a line circuit and a row circuit of the storage array can be read and written directly, and conversion of the line and the row can be processed at a high speed.
JP56085392A 1981-06-03 1981-06-03 Storage device Pending JPS57200988A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56085392A JPS57200988A (en) 1981-06-03 1981-06-03 Storage device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56085392A JPS57200988A (en) 1981-06-03 1981-06-03 Storage device

Publications (1)

Publication Number Publication Date
JPS57200988A true JPS57200988A (en) 1982-12-09

Family

ID=13857484

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56085392A Pending JPS57200988A (en) 1981-06-03 1981-06-03 Storage device

Country Status (1)

Country Link
JP (1) JPS57200988A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63269396A (en) * 1987-04-27 1988-11-07 Nec Corp Input/output memory
JPH01151095A (en) * 1987-12-09 1989-06-13 Toshiba Corp Semiconductor memory

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5429532A (en) * 1977-08-08 1979-03-05 Fujitsu Ltd Dynamic mosic memory

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5429532A (en) * 1977-08-08 1979-03-05 Fujitsu Ltd Dynamic mosic memory

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63269396A (en) * 1987-04-27 1988-11-07 Nec Corp Input/output memory
JPH01151095A (en) * 1987-12-09 1989-06-13 Toshiba Corp Semiconductor memory

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