CN1258814C - 半导体器件的制造方法 - Google Patents
半导体器件的制造方法 Download PDFInfo
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- CN1258814C CN1258814C CNB02105097XA CN02105097A CN1258814C CN 1258814 C CN1258814 C CN 1258814C CN B02105097X A CNB02105097X A CN B02105097XA CN 02105097 A CN02105097 A CN 02105097A CN 1258814 C CN1258814 C CN 1258814C
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- Prior art keywords
- copper
- containing film
- film
- carried out
- semiconductor device
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Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
- H01L21/02074—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers the processing being a planarization of conductive layers
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- H—ELECTRICITY
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76883—Post-treatment or after-treatment of the conductive material
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Power Engineering (AREA)
- Plasma & Fusion (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Cleaning Or Drying Semiconductors (AREA)
- Weting (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Description
Claims (8)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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JP2001044949A JP4535629B2 (ja) | 2001-02-21 | 2001-02-21 | 半導体装置の製造方法 |
JP044949/2001 | 2001-02-21 |
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CN1372313A CN1372313A (zh) | 2002-10-02 |
CN1258814C true CN1258814C (zh) | 2006-06-07 |
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CNB02105097XA Expired - Fee Related CN1258814C (zh) | 2001-02-21 | 2002-02-21 | 半导体器件的制造方法 |
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US (2) | US6787480B2 (zh) |
JP (1) | JP4535629B2 (zh) |
KR (1) | KR20020068470A (zh) |
CN (1) | CN1258814C (zh) |
GB (1) | GB2375888A (zh) |
TW (1) | TW522520B (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
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CN101211818B (zh) * | 2006-12-26 | 2010-04-07 | 中芯国际集成电路制造(上海)有限公司 | 半导体集成电路的互连结构填隙铜镀的方法与结构 |
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JP4554011B2 (ja) * | 1999-08-10 | 2010-09-29 | ルネサスエレクトロニクス株式会社 | 半導体集積回路装置の製造方法 |
SG125881A1 (en) * | 1999-12-03 | 2006-10-30 | Lytle Steven Alan | Define via in dual damascene process |
JP4535629B2 (ja) * | 2001-02-21 | 2010-09-01 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
KR101005434B1 (ko) * | 2002-04-26 | 2011-01-05 | 에이저 시스템즈 인크 | 신뢰성 개선을 위한 규화 구리 패시베이션 |
US7687917B2 (en) * | 2002-05-08 | 2010-03-30 | Nec Electronics Corporation | Single damascene structure semiconductor device having silicon-diffused metal wiring layer |
JP2003347299A (ja) * | 2002-05-24 | 2003-12-05 | Renesas Technology Corp | 半導体集積回路装置の製造方法 |
JP4087172B2 (ja) * | 2002-07-11 | 2008-05-21 | セイコーインスツル株式会社 | 半導体装置の製造方法 |
JP2004095865A (ja) * | 2002-08-30 | 2004-03-25 | Nec Electronics Corp | 半導体装置およびその製造方法 |
JP4209212B2 (ja) * | 2003-01-30 | 2009-01-14 | Necエレクトロニクス株式会社 | 半導体装置の製造方法 |
JP4499365B2 (ja) * | 2003-02-21 | 2010-07-07 | スピードファム株式会社 | 半導体処理方法 |
CN1802744A (zh) * | 2003-04-09 | 2006-07-12 | 库利克-索法投资公司 | 集成电路的电交互连接结构及其制造方法 |
JP3694512B2 (ja) * | 2003-04-18 | 2005-09-14 | 沖電気工業株式会社 | 半導体装置の製造方法 |
JP3722813B2 (ja) * | 2003-07-08 | 2005-11-30 | 沖電気工業株式会社 | 埋め込み配線構造の形成方法 |
US7291568B2 (en) * | 2003-08-26 | 2007-11-06 | International Business Machines Corporation | Method for fabricating a nitrided silicon-oxide gate dielectric |
KR20050022292A (ko) * | 2003-08-27 | 2005-03-07 | 마츠시타 덴끼 산교 가부시키가이샤 | 반도체장치의 제조방법 |
US7056648B2 (en) * | 2003-09-17 | 2006-06-06 | International Business Machines Corporation | Method for isotropic etching of copper |
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US20020155702A1 (en) | 2002-10-24 |
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US20040266171A1 (en) | 2004-12-30 |
US7268087B2 (en) | 2007-09-11 |
JP4535629B2 (ja) | 2010-09-01 |
KR20020068470A (ko) | 2002-08-27 |
US6787480B2 (en) | 2004-09-07 |
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GB0203784D0 (en) | 2002-04-03 |
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