FR3096830B1 - Elément d'interconnexion et son procédé de fabrication - Google Patents

Elément d'interconnexion et son procédé de fabrication Download PDF

Info

Publication number
FR3096830B1
FR3096830B1 FR1905576A FR1905576A FR3096830B1 FR 3096830 B1 FR3096830 B1 FR 3096830B1 FR 1905576 A FR1905576 A FR 1905576A FR 1905576 A FR1905576 A FR 1905576A FR 3096830 B1 FR3096830 B1 FR 3096830B1
Authority
FR
France
Prior art keywords
layer
interconnection element
cavity
copper
manufacturing process
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
FR1905576A
Other languages
English (en)
Other versions
FR3096830A1 (fr
Inventor
Magali Gregoire
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics Crolles 2 SAS
Original Assignee
STMicroelectronics Crolles 2 SAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics Crolles 2 SAS filed Critical STMicroelectronics Crolles 2 SAS
Priority to FR1905576A priority Critical patent/FR3096830B1/fr
Priority to US16/881,689 priority patent/US11152259B2/en
Publication of FR3096830A1 publication Critical patent/FR3096830A1/fr
Application granted granted Critical
Publication of FR3096830B1 publication Critical patent/FR3096830B1/fr
Priority to US17/488,714 priority patent/US11610813B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76855—After-treatment introducing at least one additional element into the layer
    • H01L21/76858—After-treatment introducing at least one additional element into the layer by diffusing alloying elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76846—Layer combinations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76849—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned on top of the main fill metal
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Geometry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

Elément d'interconnexion et son procédé de fabrication La présente description concerne un procédé de fabrication d'un élément d'interconnexion d'une structure d'interconnexion d'un circuit intégré, le procédé comprenant les étapes suivantes : a) graver une cavité (200) dans une première couche (202) isolante ; b) déposer une deuxième couche (204) en nitrure de silicium sur les parois et le fond de la cavité (200), la concentration en atomes d'azote dans la deuxième couche augmentant en s'éloignant d'une surface exposée (2041) de la deuxième couche (204) ; c) déposer une troisième couche (206) en cuivre sur la deuxième couche (204) ; d) chauffer pour former une quatrième couche (208) de siliciure de cuivre à partir des deuxième et troisième couches (204, 206) ; et e) remplir la cavité de cuivre (210). Figure pour l'abrégé : Fig. 2
FR1905576A 2019-05-27 2019-05-27 Elément d'interconnexion et son procédé de fabrication Active FR3096830B1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
FR1905576A FR3096830B1 (fr) 2019-05-27 2019-05-27 Elément d'interconnexion et son procédé de fabrication
US16/881,689 US11152259B2 (en) 2019-05-27 2020-05-22 Interconnection element and method of manufacturing the same
US17/488,714 US11610813B2 (en) 2019-05-27 2021-09-29 Interconnection element and method of manufacturing the same

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1905576 2019-05-27
FR1905576A FR3096830B1 (fr) 2019-05-27 2019-05-27 Elément d'interconnexion et son procédé de fabrication

Publications (2)

Publication Number Publication Date
FR3096830A1 FR3096830A1 (fr) 2020-12-04
FR3096830B1 true FR3096830B1 (fr) 2021-06-18

Family

ID=68987741

Family Applications (1)

Application Number Title Priority Date Filing Date
FR1905576A Active FR3096830B1 (fr) 2019-05-27 2019-05-27 Elément d'interconnexion et son procédé de fabrication

Country Status (2)

Country Link
US (2) US11152259B2 (fr)
FR (1) FR3096830B1 (fr)

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69226411T2 (de) 1991-09-30 1998-12-24 At & T Corp Herstellung eines leitenden Gebietes in elektronischen Vorrichtungen
US5391517A (en) 1993-09-13 1995-02-21 Motorola Inc. Process for forming copper interconnect structure
US6303505B1 (en) 1998-07-09 2001-10-16 Advanced Micro Devices, Inc. Copper interconnect with improved electromigration resistance
US6251775B1 (en) 1999-04-23 2001-06-26 International Business Machines Corporation Self-aligned copper silicide formation for improved adhesion/electromigration
US6046108A (en) 1999-06-25 2000-04-04 Taiwan Semiconductor Manufacturing Company Method for selective growth of Cu3 Ge or Cu5 Si for passivation of damascene copper structures and device manufactured thereby
SG125881A1 (en) 1999-12-03 2006-10-30 Lytle Steven Alan Define via in dual damascene process
JP4535629B2 (ja) * 2001-02-21 2010-09-01 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US6693356B2 (en) * 2002-03-27 2004-02-17 Texas Instruments Incorporated Copper transition layer for improving copper interconnection reliability
JP2003332426A (ja) * 2002-05-17 2003-11-21 Renesas Technology Corp 半導体装置の製造方法および半導体装置
ATE553223T1 (de) * 2006-02-28 2012-04-15 Advanced Interconnect Materials Llc Halbleitervorrichtung, herstellungsverfahren dafür und sputtern von zielmaterial zur verwendung für das verfahren
JP4741965B2 (ja) * 2006-03-23 2011-08-10 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
US8258057B2 (en) * 2006-03-30 2012-09-04 Intel Corporation Copper-filled trench contact for transistor performance improvement
KR20130092884A (ko) * 2012-02-13 2013-08-21 에스케이하이닉스 주식회사 반도체 소자의 배선 구조체 및 제조 방법
US8981564B2 (en) * 2013-05-20 2015-03-17 Invensas Corporation Metal PVD-free conducting structures
US9673091B2 (en) * 2015-06-25 2017-06-06 Globalfoundries Inc. Structure for BEOL metal levels with multiple dielectric layers for improved dielectric to metal adhesion

Also Published As

Publication number Publication date
FR3096830A1 (fr) 2020-12-04
US20200381297A1 (en) 2020-12-03
US11610813B2 (en) 2023-03-21
US11152259B2 (en) 2021-10-19
US20220020640A1 (en) 2022-01-20

Similar Documents

Publication Publication Date Title
US7164188B2 (en) Buried conductor patterns formed by surface transformation of empty spaces in solid state materials
FR2595165A1 (fr) Dispositif a semi-conducteurs du type tridimensionnel et procede pour sa production
KR950034672A (ko) 반도체 집적회로장치의 제조방법
JPH03220751A (ja) インターレベル・コンタクトを製造する方法、および半導体構造
EP1296368A3 (fr) Dispositif semiconducteur avec matériau isolant poreux et méthode de fabrication
KR940016580A (ko) 반도체 장치의 제조 방법
JP2003086695A (ja) 半導体装置及びその製造方法
WO2012071986A1 (fr) Procédé de production de dispositifs à semi-conducteurs à oxyde de grille double
Wang et al. Silicon micromachining of high aspect ratio, high-density through-wafer electrical interconnects for 3-D multichip packaging
KR20000012027A (ko) 반도체장치의제조방법
JPH02206175A (ja) Ｍｏｓ型半導体装置
FR3096830B1 (fr) Elément d'interconnexion et son procédé de fabrication
KR20080047541A (ko) 반도체 장치 상에 캐핑 레이어를 형성하는 방법
TW473922B (en) Semiconductor device and method of manufacturing the same
GB1558514A (en) Manufacturing process for the simultaneous production of semiconductor devices
FR2514559A1 (fr) Dispositif a semi-conducteurs, notamment transistor planar comportant une isolation dielectrique formee par un polyimide et procede de fabrication d'un tel dispositif
FR3103315B1 (fr) Procédé de fabrication de puces électroniques
JP2002270509A5 (fr)
KR930008885B1 (ko) 씨모스 인버터 구조 및 그 제조방법
TW478094B (en) Dual-polysilicon structures in integrated circuits and a method for making them
KR0171016B1 (ko) 반도체 소자의 금속배선방법
TW473974B (en) Manufacture method of copper interconnect with flat surface
JPH0244142B2 (ja) Handotaisochinoseizohoho
KR100187688B1 (ko) 반도체 소자의 금속층 형성방법
TW473999B (en) Semiconductor device and method for manufacturing same

Legal Events

Date Code Title Description
PLFP Fee payment

Year of fee payment: 2

PLSC Publication of the preliminary search report

Effective date: 20201204

PLFP Fee payment

Year of fee payment: 3

PLFP Fee payment

Year of fee payment: 4

PLFP Fee payment

Year of fee payment: 5

PLFP Fee payment

Year of fee payment: 6