CN102456730B - 半导体器件及其制造方法 - Google Patents
半导体器件及其制造方法 Download PDFInfo
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Abstract
本发明提供一种半导体器件及其制造方法,该半导体器件包括:第一半导体层,形成在衬底上;第二半导体层,形成在所述第一半导体层上;源电极和漏电极,形成在所述第二半导体层上;绝缘膜,形成在所述第二半导体层上;栅电极,形成在所述绝缘膜上;以及保护膜,覆盖所述绝缘膜,所述保护膜是通过热CVD、热ALD或真空气相沉积形成的。利用本发明,在于栅电极与半导体层之间插入了绝缘膜、并且覆盖有绝缘保护膜的半导体器件中,能够维持足够程度的绝缘强度。
Description
技术领域
本文讨论的实施例涉及一种半导体器件及其制造方法。
背景技术
已知使用GaN层作为电子渡越层(electrontransitlayer)的AlGaN/GaN异质结场效应晶体管。GaN是宽带隙材料,具有高击穿电压和高饱和电子速度。GaN是一种可以实现高电流、高电压及低导通电阻半导体器件的有前途的材料。因此,对于作为下一代高性能开关器件的基于GaN的半导体器件已经进行了许多调查研究。
通常来讲,在诸如场效应晶体管的半导体器件中,绝缘膜形成在器件(例如场效应晶体管)的整个表面上,其目的是为了在制造完栅电极或漏电极之后进行钝化。
为了实现使用功率晶体管的高性能开关器件,期望在实现开关器件的常关动作(normally-offbehavior)和高击穿电压的同时降低导通电阻。可以通过改善GaN晶体质量(crystalquality)和/或改善晶体管中使用的材料的晶体质量来实现低导通电阻和常关动作。另一方面,通常来讲,由于根据应用而需要几百伏到几千伏的绝缘强度(dielectricstrength),因而使用肖特基(Schottky)栅结构的开关器件难以实现高击穿电压。为了解决这一问题,提出在栅电极与半导体层之间插入绝缘膜来减小栅极泄漏(leakage)电流并强化绝缘强度。
对于栅电极与半导体层之间插入了绝缘膜的晶体管,还设置有绝缘材料的保护膜或钝化膜。然而,保护膜可能降低晶体管的绝缘强度,并从而可能无法达到足够程度的绝缘强度。
因此,对于在栅电极与半导体层之间设置了绝缘膜的半导体器件(例如晶体管),期望达到足够的绝缘强度。
现有技术文献:
专利文献1:日本特许专利公开号2008-103408
专利文献2:美国专利公开号2006/0019435A1
发明内容
根据本公开文件的一个方面,一种半导体器件包括:第一半导体层,形成在衬底上;第二半导体层,形成在所述第一半导体层上;源电极和漏电极,形成在所述第二半导体层上;绝缘膜,形成在所述第二半导体层上;栅电极,形成在所述绝缘膜上;以及保护膜,覆盖所述绝缘膜,所述保护膜是通过热CVD、热ALD或真空气相沉积形成的。
根据本公开文件的另一个方面,一种半导体器件包括:第一半导体层,形成在衬底上;第二半导体层,形成在所述第一半导体层上;源电极和漏电极,形成在所述第二半导体层上;凹陷(recess),形成在所述第二半导体层中,或形成在所述第二半导体层和部分所述第一半导体层中;绝缘膜,形成在所述第二半导体层上和所述凹陷中;栅电极,形成在所述凹陷内的所述绝缘膜上;以及保护膜,覆盖所述绝缘膜,所述保护膜是通过热CVD、热ALD或真空气相沉积形成的。
根据本公开文件的又一个方面,提供了一种半导体器件制造方法。该方法包括:
在衬底上依序形成第一半导体层和第二半导体层;
在所述第二半导体层上形成源电极和漏电极;
在所述第二半导体层上形成绝缘膜;
在所述绝缘膜上形成栅电极;以及
通过热CVD、热ALD或真空气相沉积形成保护膜,以覆盖所述绝缘膜。
根据本公开文件的再一个方面,一种半导体器件制造方法包括:
在衬底上依序形成第一半导体层和第二半导体层;
在所述第二半导体层上形成源电极和漏电极;
在所述第二半导体层中形成凹陷;
在所述第二半导体层上和所述凹陷中形成绝缘膜;
在所述凹陷内的所述绝缘膜上形成栅电极;以及
通过热CVD、热ALD或真空气相沉积形成保护膜,以覆盖所述绝缘膜。
采用前述结构和方法,在于栅电极与半导体层之间具有绝缘膜的晶体管中,能够维持足够程度的绝缘强度。
附图说明
图1是示出了覆盖有保护膜的高电子迁移率晶体管(HEMT)的剖面结构的示意图;
图2是示出了具有通过等离子体CVD方法形成的保护膜的HEMT的栅极电流特性的曲线图;
图3是示出了没有保护膜的HEMT的栅极电流特性的曲线图;
图4是示出了通过等离子体CVD方式形成保护膜的示意图;
图5A示出了根据实施例一的半导体器件制造方法中的剖视图;
图5B示出了根据实施例一的半导体器件制造方法中的剖视图;
图5C示出了根据实施例一的半导体器件制造方法中的剖视图;
图5D示出了根据实施例一的半导体器件制造方法中的剖视图;
图5E示出了根据实施例一的半导体器件制造方法中的剖视图;
图5F示出了根据实施例一的半导体器件制造方法中的剖视图;
图6A示出了根据实施例二的半导体器件制造方法中的剖视图;
图6B示出了根据实施例二的半导体器件制造方法中的剖视图;
图6C示出了根据实施例二的半导体器件制造方法中的剖视图;
图6D示出了根据实施例二的半导体器件制造方法中的剖视图;
图6E示出了根据实施例二的半导体器件制造方法中的剖视图;
图6F示出了根据实施例二的半导体器件制造方法中的剖视图;
图6G示出了根据实施例二的半导体器件制造方法中的剖视图;
图7是示出了根据实施例三的半导体器件制造方法的流程图;
图8示出了通过热CVD形成的氧化铝膜B的XPS测量结果;
图9示出了通过图7所示的方法形成的氧化铝膜A的XPS测量结果;
图10是示出了温度与水的脱附(desorption)之间的关系的图;
图11是示出了保护膜的绝缘强度测试结果的图;以及
图12是示出了保护膜的绝缘强度测量的示意图。
具体实施方式
现在参照附图描述实施例。相同的元件或组件用相同的符号标记,并省略其赘述。
【实施例一】
首先,说明在栅电极与半导体层之间设置了绝缘膜的晶体管的结构,该晶体管被绝缘材料制成的保护膜覆盖,参见图1。这种类型的晶体管称作高电子迁移率晶体管(HEMT),其中,电子渡越层12、阻挡层13和覆盖层14依序在衬底11上外延生长。源电极15和漏电极16连接到阻挡层13。绝缘膜17形成在覆盖层14上,栅电极18形成在绝缘膜17上。保护膜19设置为覆盖包括绝缘膜17的整个表面。
衬底11例如是SiC衬底、蓝宝石(Al2O3)衬底或任意其他合适的衬底。电子渡越层12是本征GaN(i-GaN)层。阻挡层13由n型AlGaN(n-AlGaN)形成。覆盖层14由n型GaN(n-GaN)形成。绝缘膜17是通过等离子体ALD(原子层沉积)形成的氧化铝(Al2O3)层。保护膜19是由例如氮化硅(SiN)、氧化硅(SiO2)或氧化铝(Al2O3)形成的。为了形成保护膜19,从提高生产量的角度考虑,由于令人满意的膜形成速率,典型地采用等离子体CVD(化学气相沉积)。
图2示出了形成上述保护膜19之后的晶体管的栅-源电压(Vgs)与栅-源电流(Igs)之间的关系以及栅-漏电压(Vgd)与栅-漏电流(Igd)之间的关系。图3示出了设置保护膜19之前的晶体管的栅-源电压(Vgs)与栅-源电流(Igs)之间的关系以及栅-漏电压(Vgd)与栅-漏电流(Igd)之间的关系。
从图2和图3清楚地看出,在没有保护膜19的情况下,栅-源电流(Igs)和栅-漏电流(Igd)足够低,它们被抑制为小于10nA/mm。与没有保护膜19的晶体管相比,在其中形成了保护膜19的晶体管中,栅极泄漏电流显著增大。换句话说,保护膜19的形成导致栅极泄漏电流增大且降低了晶体管的特性。即使是由HfO2形成绝缘膜17,也可以观察到相同的现象。
发明人对于为什么设置了保护膜19时栅极泄漏电流显著增大的原因进行了深入的研究,并发现:栅极泄漏电流的增大是由保护膜19的膜形成方法造成的。
表一示出了通过几种技术形成的氧化铝保护膜19的源-漏绝缘强度。
表一
如表一所示,当通过等离子体CVD的方式为绝缘强度390V的晶体管设置氧化铝保护膜19时,在形成保护膜19后,绝缘强度显著降低到150V。当在绝缘强度400V的晶体管中通过等离子体ALD形成氧化铝保护膜19时,在形成保护膜19后,绝缘强度降低到200V。如果在绝缘强度380V的晶体管中通过溅射形成氧化铝保护膜19,则在形成保护膜19后,绝缘强度降低到140V。相反,当在绝缘强度400V的晶体管中采用热ALD形成氧化铝保护膜19时,即使在形成保护膜19后,绝缘强度仍然保持在400V。热ALD是一种通过向加热后的衬底上交替地供应源气体而不产生等离子体来形成膜的膜沉积技术。
从上述实验结果,可以推测出:具有保护膜19的晶体管中栅极泄漏电流的增大是由于形成氧化铝膜时所采用的等离子体CVD工艺造成的。
等离子体CVD、等离子体ALD以及溅射均是使用等离子体工艺的膜沉积技术,而热ALD是非等离子体工艺。
从上述假设可以得出结论,由于形成氧化铝保护膜19的等离子体工艺,绝缘强度下降并导致栅极泄漏电流增大。当使用热ALD形成氧化铝保护膜19时,绝缘强度得以保持。因此,通过采用非等离子体工艺(例如热ALD工艺)来形成氧化铝保护膜19,可以防止栅极泄漏电流增大。非等离子体工艺的例子包括热ALD、热CVD、真空气相沉积(包括电阻加热和电子束蒸发)。
接下来,说明当通过诸如等离子体CVD的等离子体工艺形成氧化铝保护膜19时栅极泄漏电流增大的机制。图4示出了通过使用等离子体工艺的膜沉积方法在布置了绝缘膜17和栅电极18的结构上形成保护膜19。在等离子体工艺中,由等离子体30生成的充电粒子经过栅电极18进入绝缘膜17。可以推测充电粒子导致绝缘膜17中的缺陷并导致栅极泄漏电流增大。由于绝缘膜17的表面暴露于等离子体中,因此还可以推测,在绝缘膜17的表面区域中由于等离子体破坏而产生了缺陷。基于这些推测,认为只要是通过等离子体工艺(例如,等离子体CVD)形成保护膜19,那么即使使用金属氧化物、氮氧化物或氮化物来形成绝缘膜17,绝缘膜17的绝缘强度也会降低。
尽管当通过诸如等离子体CVD的等离子体工艺形成保护膜19时通常可能已经发生了相同的现象,但是晶体管的绝缘强度的下降还没有被带有怀疑地察觉到。为什么这一现象还没有被察觉的原因是因为传统的半导体材料(例如硅或GaAs)与GaN相比带隙较窄。对于窄带隙材料而言,实际使用的电压范围低于绝缘强度降低成为问题的电压范围,因而,到目前为止由于通过诸如等离子体CVD的等离子体工艺来形成保护膜19而导致的绝缘强度降低还没有成为实际的问题。换句话说,当使用诸如GaN的宽带隙半导体材料时,由于使用等离子体工艺形成保护膜19而导致的绝缘强度下降的问题才会显现出来。
当通过等离子体ALD形成氧化铝膜时,三甲基铝(TMA:(CH3)3Al))和氧气作为源材料被供应从而生成等离子体。可替代地,在等离子体ALD中,TMA和氧气等离子体可以交替供应。当通过溅射工艺形成氧化铝膜时,氧化铝用作标靶,氩气(Ar)和氧气作为溅射气体被供应。可替代地,铝(Al)可以用作标靶,氩气(Ar)和氧气用作溅射气体来进行溅射。当通过热ALD形成氧化铝膜时,衬底被加热,TMA和水作为源材料被交替供应。在热ALD工艺期间,在沉积室内没有产生等离子体。
在通过等离子体CVD形成的绝缘膜中,包含5*1020/cm3或更多的氢分子。在通过等离子体ALD形成的绝缘膜中,其中包含的氢分子的量等于或少于1*1020/cm3,其中包含的水分子的量等于或少于1*1020/cm3。在通过热ALD形成的绝缘膜中,其中包含的氢分子的量等于或少于1*1020/cm3,而其中包含的水分子的量为1*1020/cm3或大于1*1020/cm3。因此,通过测量绝缘膜中氢分子和水分子的量可以识别膜沉积方法。
(半导体器件制造方法)
接下来,结合图5A到图5F说明根据实施例的半导体器件制造方法。
如图5A所示,在衬底11上形成成核层(nucleationlayer)(未示出)。包括电子渡越层12、阻挡层13和覆盖层14的半导体层通过金属有机气相外延法(MOVPE)依序外延生长。
衬底11例如是SiC衬底或蓝宝石(Al2O3)衬底。形成在衬底11上的成核层(未示出)例如是厚度为0.1μm的非掺杂的本征AlN(i-AlN)层。作为第一半导体层的电子渡越层12是厚度为3.0μm的非掺杂的本征GaN(i-GaN)层。作为第二半导体层的阻挡层13是厚度为20nm的非掺杂的本征Al0.25Ga0.75N层。作为第三半导体层的覆盖层14是厚度为5nm的n-GaN层。利用这种层叠结构,二维电子气(2DEG)通道12a在电子渡越层12中靠近阻挡层13处生成。
为了形成半导体层12-14,使用诸如三甲基铝(TMA)、三甲基镓(TMG)或氨气(NH3)之类的源气体。根据待形成的半导体层的成分来调整源气体的供应量。用于形成半导体层的氨气的流速是100sccm到10slm,用于半导体层的晶体生长的室内压强是6.68-40.05kPa(50-300Torr),生长温度是1000-1200℃。阻挡层13可以是杂质掺杂的n型Al0.25Ga0.75N层。可以通过借助分子束外延(MBE)的晶体生长来形成半导体层。除了AlGaN之外,阻挡层13可以由InGaN、InAlN或InAlGaN形成。
然后,如图5B所示,形成器件隔离区21。更具体而言,将光致抗蚀剂涂覆于覆盖层14的表面,并使用曝光系统通过曝光和显影将光致抗蚀剂图案化为规定的抗蚀剂图案。抗蚀剂图案具有与待形成器件隔离区21的区域相对应的开口。然后,使用抗蚀剂图案作为掩模进行离子注入,以将杂质引入进而到达电子渡越层13内部。杂质引入区变为器件隔离区21。然后移除抗蚀剂图案。作为替代方式,使用抗蚀剂图案作为掩模,经掩模的开口通过干蚀刻移除覆盖层14、阻挡层13和部分电子渡越层12。可以在半导体层已被移除的区域中埋入氧化物膜。
然后,如图5C所示,形成源电极15和漏电极16。更具体而言,将光致抗蚀剂涂覆于覆盖层14的表面,并通过曝光系统中的曝光和显影将光致抗蚀剂图案化为规定的抗蚀剂图案。抗蚀剂图案具有与待形成源电极15和漏电极16的区域相对应的开口。然后,使用抗蚀剂图案作为掩模,经掩模的开口通过干蚀刻(例如使用氯气的反应离子蚀刻(RIE))移除覆盖层14和部分阻挡层13。在干蚀刻工艺中,以30sccm的流速向室(chamber)内引入氯气作为蚀刻气体。室内的压强设置为大约2Pa,施加20W的RF功率。然后,通过真空气相沉积或其他合适的方法形成诸如Ta/Al层叠膜的金属膜。然后,通过剥离法(lift-offmethod)移除金属膜的不必要的部分以及抗蚀剂图案。这样,就形成了源电极15和漏电极16。在剥离工艺之后,以580℃进行热处理以形成欧姆接触(ohmiccontact)。
然后,如图5D所示,在覆盖层14、源电极15和漏电极16上形成绝缘膜17。绝缘膜17包含从如下材料中选择出的一种或多种材料:氧化硅、氧化铝、氧化铪、氧化钽、氧化锆、氧化钇、氧化镧、氧化钽、氮化硅、氮化铝和氮氧化硅。优选的是,绝缘膜17具有高的相对介电常数(relativepermittivity)。从实用的角度来看,优选使用SiO2、SiN、Al2O3、SiON、HfO2。绝缘膜17的厚度是2nm到200nm。通过等离子体ALD、等离子体CVD或溅射形成绝缘膜17。如果通过等离子体CVD形成氧化铝绝缘膜17,则供应三甲基铝(TMA)和氧气作为源气体以生成等离子体。
然后,如图5E所示,形成栅电极18。更具体而言,将光致抗蚀剂涂覆于绝缘膜17的表面,并通过曝光系统中的曝光和显影将光致抗蚀剂图案化为规定的抗蚀剂图案。该抗蚀剂图案在待形成栅电极18的位置具有开口。然后,通过真空气相沉积或其他合适的方法形成诸如Ni/Au层叠膜的金属膜。然后,通过剥离法移除金属膜的不必要部分以及抗蚀剂图案。这样就形成了栅电极18。
然后,如图5F所示,形成保护膜20。保护膜20包含从如下材料中选择的一种或多种材料:氧化硅、氧化铝、氧化铪、氧化钽、氧化锆、氧化钇、氧化镧、氧化钽、氮化硅、氮化铝以及氮氧化硅。保护膜20是通过不使用等离子体的工艺形成的,例如热ALD、热CVD或真空气相沉积。当通过热ALD形成氧化铝保护膜20时,在将衬底加热到200-400℃的同时交替供应三甲基铝和水。
这样,就制成了根据实施例一的半导体器件。由于保护膜20是使用不产生等离子体的工艺形成的,因而即使在形成保护膜之后,具有保护膜的晶体管的绝缘强度也能够得以保持。
【实施例二】
以下描述实施例二。图6A到图6G示出了根据实施例二的半导体器件制造工艺。
首先,如图6A所示,在衬底11上形成成核层(未示出)。包括电子渡越层12、阻挡层13和覆盖层14的半导体层通过金属有机气相外延法(MOVPE)依序外延生长。
衬底11例如是SiC衬底或蓝宝石(Al2O3)衬底。形成在衬底11上的成核层(未示出)例如是厚度为0.1μm的非掺杂的本征AlN(i-AlN)层。电子渡越层12是厚度为3.0μm的非掺杂的本征GaN(i-GaN)层。阻挡层13是厚度为20nm的非掺杂的本征Al0.25Ga0.75N层。覆盖层14是厚度为5nm的n-GaN层。二维电子气(2DEG)通道12a在电子渡越层12中靠近阻挡层13处生成。
然后,如图6B所示,形成器件隔离区21。更具体而言,将光致抗蚀剂涂覆于覆盖层14的表面,并使用曝光系统通过曝光和显影将光致抗蚀剂图案化为规定的抗蚀剂图案。抗蚀剂图案具有与待形成器件隔离区21的区域相对应的开口。然后,使用抗蚀剂图案作为掩模进行离子注入,以将杂质引入进而到达电子渡越层13内部。杂质引入区变为器件隔离区21。然后移除抗蚀剂图案。
然后,如图6C所示,形成源电极15和漏电极16。更具体而言,将光致抗蚀剂涂覆于覆盖层14的表面,并通过曝光系统中的曝光和显影将光致抗蚀剂图案化为规定的抗蚀剂图案。抗蚀剂图案具有与待形成源电极15和漏电极16的区域相对应的开口。然后,使用抗蚀剂图案作为掩模,经掩模的开口通过干蚀刻(例如使用氯气的反应离子蚀刻(RIE))移除覆盖层14和部分阻挡层13。然后,通过真空气相沉积或其他合适的方法形成诸如Ta/Al层叠膜的金属膜。然后,通过剥离法移除金属膜的不必要部分以及抗蚀剂图案。这样,就形成了源电极15和漏电极16。在剥离工艺之后,在580℃的温度下进行热处理以形成欧姆接触。
然后,如图6D所示,形成凹陷31。更具体而言,将光致抗蚀剂涂覆于覆盖层14的表面上,并通过曝光系统中的曝光和显影将光致抗蚀剂图案化为抗蚀剂图案。抗蚀剂图案具有与待形成凹陷31的区域相对应的开口。然后,使用抗蚀剂图案作为掩模,经掩模的开口通过干蚀刻(例如使用氯气的反应离子蚀刻(RIE))移除覆盖层14以及部分阻挡层13。然后,移除抗蚀剂图案。在干蚀刻工艺期间,可以在蚀刻气体中混入氧或氟。可以通过蚀刻部分覆盖层而将凹陷31只形成在覆盖层14中。可替代地,通过移除覆盖层14、阻挡层13和部分电子渡越层12,凹陷31可以到达电子渡越层12。
然后,如图6E所示,在凹陷31的内表面上、覆盖层14、源电极15以及漏电极16上形成绝缘膜32。绝缘膜32包含从如下材料中选择的一种或多种材料:氧化硅、氧化铝、氧化铪、氧化钽、氧化锆、氧化钇、氧化镧、氧化钽、氮化硅、氮化铝和氮氧化硅。
优选的是,绝缘膜32具有高的相对介电常数。从实用的角度来看,优选使用SiO2、SiN、Al2O3、SiON、HfO2。绝缘膜32的厚度是2nm到200nm。绝缘膜32是通过等离子体ALD、等离子体CVD或溅射形成的。当通过等离子体CVD形成氧化铝绝缘膜32时,供应三甲基铝(TMA)和氧气作为源气体以生成等离子体。
然后,如图6F所示,形成栅电极33。更具体而言,将光致抗蚀剂涂覆于绝缘膜32的表面,并在曝光系统中通过曝光和显影将光致抗蚀剂图案化为规定的抗蚀剂图案。抗蚀剂图案具有与凹陷31所位于的区域相对应的开口。然后,通过真空气相沉积或其他合适的方法形成诸如Ni/Au层叠膜的金属膜。然后,通过剥离法移除金属膜的不必要部分以及抗蚀剂图案。这样就形成了栅电极33。
然后,如图6G所示,形成保护膜34。保护膜34由绝缘材料形成,优选使用氧化铝。保护膜34是通过不使用等离子体的工艺形成的,这种工艺包括热ALD、热CVD以及真空气相沉积。当通过热ALD形成氧化铝保护膜34时,在将衬底加热到200-400℃的同时交替供应三甲基铝(TMA)和水。
这样,就制成了根据实施例二的半导体器件。
实施例二的除了上述工艺和结构之外的细节与实施例一的相同。
【实施例三】
接下来,说明实施例三。当在绝缘膜上形成了保护膜时,半导体器件的绝缘强度下降。这种绝缘强度的下降可能是由于绝缘膜与保护膜之间的热膨胀系数差、在保护膜形成期间产生的应力、或者绝缘膜与保护膜之间剩余的残留水分造成的。
从这个角度而言,通过使用金属氧化物材料形成绝缘膜和保护膜这两者,绝缘膜与保护膜之间的热膨胀系数差可以减少到2ppm或更小。如果绝缘膜和保护膜是由相同的金属氧化物材料形成的,则绝缘膜与保护膜之间的差可以基本上减小为0。金属氧化物材料可以包含从如下元素中选择的一种或多种元素:硅、铝、铪、钽、锆、钇、镧和钽。为了增强绝缘强度,优选的是绝缘膜和保护膜处于非结晶态(amorphousstate)。
图7是示出了根据实施例三的半导体器件制造方法的流程图。实施例三的制造方法与实施例二的不同之处在于保护膜34的膜形成工艺。该工艺的细节描述如下。
首先,在步骤S102中,通过热ALD或热CVD形成氧化铝膜,使其厚度达到50nm。优选地,氧化铝膜的厚度处于从10nm到50nm的范围内。如果氧化铝膜的厚度小于10nm,则从生产率的角度来看该器件不适合于实际使用。如果氧化铝膜的厚度大于50nm,则在以下描述的热处理期间产生孔隙(pore)。可以推测,孔隙是由于脱附水的影响而产生的。膜的厚度越大,则产生的孔隙越多。已发现,如果膜厚在50nm或低于50nm,则产生的孔隙很少。因此,优选的是,一次形成的氧化铝膜的厚度为50nm或小于50nm。
然后,在步骤S104中,在700℃下进行热处理。热处理的温度是在从500℃到800℃的范围内,更优选的是从650℃到800℃。如果温度超过800℃,则保护膜的相可能从非结晶态变为结晶态。因此,优选的是在800℃或低于800℃的温度下进行热处理。
然后,在步骤S106中,确定正在形成的氧化铝膜的厚度是否达到预定厚度。如果氧化铝膜已经达到预定厚度,则结束保护膜34的膜形成工艺。如果氧化铝膜的厚度还没有达到预定值,则该工艺返回到步骤S102,重复执行膜沉积和热处理直到膜厚度达到预定值为止。
使用该方法,形成了包括两层或更多层金属氧化物的多层保护膜34。
接下来,在下文中说明用作保护膜34的氧化铝膜的XPS(X射线光电子光谱学)分析结果。使用AXIS-His(由Shimadzu公司制造和销售)作为测量设备来进行XPS分析。
图8示出了氧化铝膜B的XPS测量结果,该膜是通过热CVD连续沉积的。图9示出了氧化铝膜A的XPS测量结果,该膜是通过图7所示的工艺形成的。在各范例中,均使用硅衬底,在硅衬底上形成了厚度为200nm的氧化铝膜。氧化铝膜B、即连续形成的热CVD膜包含32%的羟基(AlOH)。相对照地,通过实施例三的工艺形成的氧化铝膜A包含18%的羟基(AlOH)。可以理解,根据实施例三的氧化铝膜的膜形成方法能够极大地减少膜中所含的羟基。如果金属氧化物膜中包含羟基(-OH),则水容易被氢键(hydrogen-bonding)吸附,并且由于膜形成工艺的受热历程,通过羟基之间的脱水缩合(dehydratingcondensation)而使水被脱附出来。因此,期望减少氧化铝膜中的羟基含量。
图10示出了氧化铝膜中的温度与脱附水之间的关系。使用ESCO有限公司制造销售的加热和除气系统“EMD1000”,通过热脱附谱(TDS)来进行测量。如该曲线图所示,当通过热CVD连续形成的氧化铝膜B被加热到500℃或更高时,观察到了由于羟基之间的脱水缩合而导致的水脱附。相反,对于通过实施例三的工艺形成的氧化铝膜A,只检测到少许水脱附。在氧化铝膜B中,检测到脱附水是开始于500℃或高于500℃,并且在650℃处达到峰值水平。因此,优选的是,选择热处理的温度范围是从500℃到800℃,更优选的是,从650℃到800℃。
图11示出了保护膜的绝缘强度测试结果。为了进行绝缘强度测试,制造了图12所示的样本,并依照图12示出的方式进行测量。在每一样本中,氧化铝膜111形成在衬底110上,电极112和113布置在氧化铝膜111上。然后,在氧化铝膜111上以及电极112与113之间设置不同类型的保护膜114,该不同类型的保护膜114变为测量目标。电流-电压计(I-Vmeter)115连接到电极112和113。作为保护膜114,第一类型样本具有SiN膜,第二类型样本具有通过热CVD连续形成的氧化铝膜B,第三类型样本具有通过实施例三的工艺形成的氧化铝膜A。还制造了没有保护(绝缘)膜114的样本,在该样本中设置了氧化铝膜111以及电极112和113。从图11可以清楚地看出,根据实施例三形成的氧化铝膜A的绝缘强度最高,与没有保护(绝缘)膜114的样本的绝缘强度相似。
实施例三中的保护膜形成工艺可以应用于实施例一。除了上述说明之外的细节与实施例一或实施例二的相同。
采用实施例中公开的结构和方法,在于栅电极与半导体层之间插入了绝缘膜、并且覆盖有绝缘保护膜的半导体器件(例如晶体管)中,能够维持足够程度的绝缘强度。
此处叙述的全部实例和条件性语言都是作为教导目的,用于帮助读者理解本发明以及发明人为了促进技术而贡献的概念,并应解释为不受限于这些具体叙述的实例和条件,说明书中的这些实例的安排也不涉及显示本发明的优劣。尽管已经详细地描述了本发明的实施例,但是应当理解,在不脱离本发明的精神和范围的情况下,可对本发明进行各种变化、替代和更改。
Claims (10)
1.一种半导体器件,包括:
第一半导体层,形成在衬底上;
第二半导体层,形成在所述第一半导体层上;
源电极和漏电极,形成在所述第二半导体层上;
绝缘膜,形成在所述第二半导体层上;
栅电极,形成在所述绝缘膜上;以及
保护膜,覆盖所述绝缘膜,所述保护膜是通过热CVD、热ALD或真空气相沉积形成的;
其中,所述保护膜是金属氧化物的多层保护膜;
其中所述绝缘膜是由与所述保护膜相同材料制成的金属氧化膜,并且其中所述保护膜比所述绝缘膜包含更少的羟基。
2.一种半导体器件,包括:
第一半导体层,形成在衬底上;
第二半导体层,形成在所述第一半导体层上;
源电极和漏电极,形成在所述第二半导体层上;
凹陷,形成在所述第二半导体层中,或形成在所述第二半导体层和部分所述第一半导体层中;
绝缘膜,形成在所述第二半导体层上和所述凹陷中;
栅电极,形成在所述凹陷内的所述绝缘膜上;以及
保护膜,覆盖所述绝缘膜,所述保护膜是通过热CVD、热ALD或真空气相沉积形成的;
其中,所述保护膜是金属氧化物的多层保护膜;
其中所述绝缘膜是由与所述保护膜相同材料制成的金属氧化膜,并且其中所述保护膜比所述绝缘膜包含更少的羟基。
3.根据权利要求1或2所述的半导体器件,其中,所述保护膜包含从如下材料中选择的一种或多种材料:氧化硅、氧化铝、氧化铪、氧化钽、氧化锆、氧化钇、氧化镧、氧化钽、氮化硅、氮化铝和氮氧化硅。
4.根据权利要求1或2所述的半导体器件,其中,所述绝缘膜包含从如下材料中选择的一种或多种材料:氧化硅、氧化铝、氧化铪、氧化钽、氧化锆、氧化钇、氧化镧、氧化钽、氮化硅、氮化铝和氮氧化硅。
5.根据权利要求1或2所述的半导体器件,其中,所述绝缘膜是通过等离子体CVD、等离子体ALD或溅射形成的。
6.根据权利要求1或2所述的半导体器件,还包括:
第三半导体层,位于所述第二半导体层与所述绝缘膜之间。
7.一种半导体器件制造方法,包括如下步骤:
在衬底上依序形成第一半导体层和第二半导体层;
在所述第二半导体层上形成源电极和漏电极;
在所述第二半导体层上形成绝缘膜;
在所述绝缘膜上形成栅电极;以及
通过热CVD、热ALD或真空气相沉积形成保护膜,以覆盖所述绝缘膜;
其中,所述保护膜是金属氧化物的多层保护膜;
其中所述绝缘膜是由与所述保护膜相同材料制成的金属氧化膜,并且其中所述保护膜比所述绝缘膜包含更少的羟基。
8.一种半导体器件制造方法,包括如下步骤:
在衬底上依序形成第一半导体层和第二半导体层;
在所述第二半导体层上形成源电极和漏电极;
在所述第二半导体层中形成凹陷;
在所述第二半导体层上和所述凹陷中形成绝缘膜;
在所述凹陷内的所述绝缘膜上形成栅电极;以及
通过热CVD、热ALD或真空气相沉积形成保护膜,以覆盖所述绝缘膜;
其中,所述保护膜是金属氧化物的多层保护膜;
其中所述绝缘膜是由与所述保护膜相同材料制成的金属氧化膜,并且其中所述保护膜比所述绝缘膜包含更少的羟基。
9.根据权利要求7或8所述的半导体器件制造方法,其中,所述形成保护膜的步骤包括:
通过交替供应三甲基铝和水的热ALD来形成氧化铝膜。
10.根据权利要求7或8所述的半导体器件制造方法,其中,所述形成保护膜的步骤包括:
形成厚度范围是从10nm到50nm的金属氧化物膜;
在范围是从500℃到800℃的温度下对所述金属氧化物膜进行热处理;以及
重复所述金属氧化物膜的形成和所述热处理。
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JP5636867B2 (ja) | 2014-12-10 |
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CN102456730A (zh) | 2012-05-16 |
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US9608083B2 (en) | 2017-03-28 |
TW201220502A (en) | 2012-05-16 |
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