US9934969B2 - Charged-particle-beam patterning without resist - Google Patents
Charged-particle-beam patterning without resist Download PDFInfo
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- US9934969B2 US9934969B2 US14/304,691 US201414304691A US9934969B2 US 9934969 B2 US9934969 B2 US 9934969B2 US 201414304691 A US201414304691 A US 201414304691A US 9934969 B2 US9934969 B2 US 9934969B2
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- hard mask
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0279—Ionlithographic processes
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/04—Coating on selected surface areas, e.g. using masks
- C23C16/047—Coating on selected surface areas, e.g. using masks using irradiation by energy or particles
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/0228—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
- H01L21/02345—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to radiation, e.g. visible light
- H01L21/02351—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to radiation, e.g. visible light treatment by exposure to corpuscular radiation, e.g. exposure to electrons, alpha-particles, protons or ions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0332—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their composition, e.g. multilayer masks, materials
Definitions
- the fundamental process mechanism involves using bond dissociation in positive resist or bond association in negative resist and resultant dissolution rate differences between the exposed and unexposed areas when developing the resist. This limits the selection of the resist materials, which are mostly polymer-based organic materials.
- FIGS. 1-3 illustrate a method of forming an integrated circuit using direct-write nano patterning in accordance with some embodiments.
- FIGS. 4-5 illustrate another method of forming an integrated circuit using direct-write nano patterning in accordance with some embodiments.
- FIG. 7 is a process for fabricating an integrated circuit in accordance with some embodiments.
- first and second features are formed in direct contact
- additional features may be formed between the first and second features, such that the first and second features may not be in direct contact
- present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
- IC integrated circuit
- processes used to make an integrated circuit fall into three categories, namely film deposition, semiconductor doping, and patterning.
- a beam carrying charged particles may be used to form a gap in a hard mask or, in the alternative, to form a structure upon the hard mask.
- a substrate 12 is provided.
- the substrate 12 may be made of a semiconductor material such as silicon, bulk silicon (doped or undoped), germanium, diamond, or the like.
- compound materials such as silicon germanium, silicon carbide, gallium arsenic, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenic phosphide, gallium indium phosphide, combinations of these, and the like, may also be used.
- the substrate 12 may be a silicon-on-insulator (SOI) substrate.
- an SOI substrate includes a layer of a semiconductor material such as epitaxial silicon, germanium, silicon germanium, SOI, silicon germanium on insulator (SGOI), or combinations thereof.
- a semiconductor material such as epitaxial silicon, germanium, silicon germanium, SOI, silicon germanium on insulator (SGOI), or combinations thereof.
- Other substrates that may be used include multi-layered substrates, gradient substrates, or hybrid orientation substrates.
- a hard mask 10 is deposited on the substrate 12 using an ALD or MLD process, which offers numerous benefits.
- ALD and MLD provide extreme thickness resolution, accurate thickness control with one monolayer accuracy, conformal step coverage, and excellent uniformity.
- a film thickness can be determined precisely by the number of applied ALD or MLD cycles. Accordingly, a critical dimension (CD) of a gap or trench can be adjusted precisely.
- CD critical dimension
- ALD and MLD allow for high conformality and excellent step coverage on high-aspect-ratio structures. Further, ALD and MLD permit excellent uniformity over a large area, which leads to large-area and large-batch capacity.
- the ALD and MLD processes also give accurate composition control, low defect density, good reproducibility, and a wider choice of materials (e.g., non-polymer-based) because the exposure mechanism in the conventional photoresist material is not required.
- a hard mask 10 formed using either the ALD process or the MLD process is much harder than, for example, the photoresist used in photolithography processes. Because the hard mask 10 is harder than a photoresist, the hard mask 10 is less likely to undesirably collapse or deform when either gaps are formed therein or structures are formed thereon, as will be more fully explained below. Other formation processes providing a hard mask 10 having the benefits, properties, and characteristics noted above may also be used.
- the hard mask 10 is prepared by an ALD or an MLD process and formed from Al 2 O 3 , AlN, AlP, AlAs, Al X Ti Y O Z , Al X Cr Y O Z , Al X Zr Y O Z , Al X Hf Y O Z , Al X Si Y O Z , B 2 O 3 , BN, B X P Y O Z , BiO X , Bi X Ti Y O Z , BaS, BaTiO 3 , CdS, CdSe, CdTe, CaO, CaS, CaF 2 , CuGaS 2 , CoO, CoO X , Co 3 O 4 , CrO X , CeO 2 , Cu 2 O, CuO, Cu X S, FeO, FeO X , GaN, GaAs, GaP, Ga 2 O 3 , GeO 2 , HfO 2 , Hf 3 N 4 , HgTe, InP, FeO
- a precursor gas 146 is provided.
- the precursor gas 146 is flowed over at least the hard mask 10 .
- the precursor gas 146 is, for example, XeF 2 .
- suitable precursors may also be employed such as SF 6 , nitrosyl chloride (NOCl), chlorine (Cl 2 ), chlorine trifluoride (ClF 3 ), oxygen (O 2 ), water (H 2 O), air, and a mixture therebetween.
- the hard mask 10 is exposed to the charged particles carried by a charged particle beam (represented by the arrows).
- the charged particles may be, for example, an electron, a proton, helium, neon, argon, silicon, beryllium, gold, and gallium.
- the charged-particle beam of FIG. 2 may be an electron beam, a proton beam, a helium beam, a neon beam, an argon beam, a silicon beam, a beryllium beam, a gold beam, and a gallium beam.
- one or more of the charged-particle beams has a beam diameter of less than one nanometer (1 nm). While a single charged-particle beam is depicted in FIG. 2 , it should be recognized that several of the charged-particle beams may be used in combination or simultaneously in some embodiments.
- the charged particles from the charged-particle beam encounter molecules from the precursor gas 146 that have absorbed on the hard mask 10 .
- precursor molecules are dissociated into volatile and non-volatile components.
- the volatile components etch the hard mask 10 only locally at or around the area subjected to the charged particles to form the gap 14 .
- a depth of the gap 14 is greater than or equal to about fifty percent (50%) of the thickness of the hard mask 10 . In an embodiment, the thickness of the hard mask 10 is less than about five nanometers (5 nm). While a single gap 14 is depicted in FIG. 3 , it should be recognized that several of the gaps 14 may be formed in practical applications.
- the hard mask 10 formed by ALD or MLD is harder than a photoresist, the hard mask 10 is less likely to undesirably collapse or deform when the gaps 14 are formed.
- the hard mask 10 will not undesirably collapse or deform when several of the gaps 14 are formed close to each other, the depth of the gaps 14 is large (e.g., about 10 nm), the width of the gaps 14 is small (e.g., about 1 nm), or the aspect ratio (i.e., the ratio of the depth to width of the gap 14 ) is high (e.g., about 10 to 1).
- a pattern transfer e.g., etching, deposition/lift off
- implantation may take place during fabrication of the integrated circuit.
- the pattern transfer process is applied using an etching process upon the substrate 12 .
- a wet etch or a plasma etch may be performed to transfer the pattern of the gap 14 into the substrate 12 .
- the pattern transfer process incorporates an ion implantation process.
- impurities e.g., p-doping with Boron, Indium, etc., or n-doping with Phosphorus, Arsenic, etc.
- impurities may be implanted into the substrate 12 through the gap 14 .
- charged particles are used to sputter (e.g., mill) the hard mask 10 to form the gap 14 .
- sputtering e.g., mill
- many of the techniques described above in connection with etching using charged particles are the same.
- the precursor gas 146 described above with reference to FIG. 2 is unneeded. Instead of relying on the precursor gas 146 , the energy of the charged particles is used to mill the surface of the hard mask 10 to form the gap 14 shown in FIG. 3 .
- charged particles are used to deposit material on the hard mask 10 to form the structure 16 as shown in FIGS. 4-5 .
- many of the techniques described above in connection with etching are the same.
- the precursor gas 156 is different than with etching.
- the precursor gas 156 may be TEOS, Styrene, TMCTS, Naphthalene, Al, Au, amorphous carbon, diamond, Co, Cr, Cu, Fe, GaAs, GaN, Ge, Mo, Nb, Ni, Os, Pd, CpPtMe 3 , MeCpPtMe 3 , a compound containing Pt (e.g., Pt(PF 3 ) 4 , Rh, Ru, Re, Si, Si 3 N 4 , SiOx, TiOx, W, and a mixture therebetween to form structure 16 .
- Pt e.g., Pt(PF 3 ) 4 , Rh, Ru, Re, Si, Si 3 N 4 , SiOx, TiOx, W, and a mixture therebetween to form structure 16 .
- the charged particles encounter molecules from the precursor gas 156 that have absorbed on the hard mask 10 . Under the influence of the charged particles, the precursor molecules are dissociated into volatile and non-volatile components. The volatile components adhere to the hard mask 10 only locally at or around the area subjected to the charged particles to form the structure 16 .
- the structure 16 is a top hard mask formed from, for example, platinum, Pt, Cobalt, Co, silicon dioxide, SiO 2 .
- a process 100 for forming an integrated circuit is provided in accordance with some embodiments.
- a substrate 12 is provided.
- a hard mask 10 is formed on the substrate 12 by one of atomic-layer deposition and molecular-layer deposition.
- the hard mask 10 is exposed to a charged particle to sputter a gap 14 in the hard mask 10 using an energy of the charged particle.
- a process 200 for forming an integrated circuit is provided.
- a substrate 12 is provided.
- a hard mask 10 is formed on the substrate 12 by one of atomic-layer deposition and molecular-layer deposition.
- a precursor gas 146 is flowed over the hard mask 10 .
- the hard mask 10 is exposed to a charged particle to etch a gap 14 in the hard mask 10 using the precursor gas 146 .
- a process 300 for forming an integrated circuit is provided.
- a substrate 12 is provided.
- a hard mask 10 is formed on the substrate 12 by one of atomic-layer deposition and molecular-layer deposition.
- a precursor gas 156 is flowed over the hard mask 10 .
- the hard mask 10 is exposed to a charged particle to deposit a structure 16 on the hard mask 10 using the precursor gas 156 .
- the nano patterning methods utilize (1) charged-particle beam induced etching; (2) charged-particle beam milling; or (3) charged-particle beam induced deposition along with atomic layer deposition (ALD) or molecular layer deposition (MLD) to eliminate the need for a resist.
- ALD atomic layer deposition
- MLD molecular layer deposition
- the hard mask 10 will not undesirably collapse or deform when several of the gaps 14 are formed close to each other, the depth of the gaps 14 is large (e.g., 10 nm), the width of the gaps 14 is small (e.g., 1 nm), or the aspect ratio (i.e., the ratio of the depth to width of the gap 14 ) is high (e.g., 10 to 1).
- the methods may be used to avoid the effects of forward and backward scattering within a resist. Further, with the methods disclosed herein there is no longer a need to develop the resist. As such, resist collapse for patterns with high aspect ratios is no longer an issue.
- a process for fabricating an integrated circuit in accordance with some embodiments includes providing a substrate, forming a hard mask upon the substrate by one of atomic-layer deposition and molecular-layer deposition, and exposing the hard mask to a charged particle from one or more charged particle beams to pattern a gap in the hard mask.
- a process for fabricating an integrated circuit in accordance with some embodiments includes providing a substrate, forming a hard mask upon the substrate by one of atomic-layer deposition and molecular-layer deposition, and directing on or more charged-particle beams at the hard mask to pattern the hard mask.
- a process for fabricating an integrated circuit in accordance with some embodiments includes providing a substrate, forming a hard mask on the substrate by one of atomic-layer deposition and molecular-layer deposition, flowing a precursor gas over an entire surface of the hard mask, and exposing a portion of the hard mask to one or more charged-particle beams carrying a charged particle, the charged particle patterning the hard mask.
Abstract
Description
Claims (20)
Priority Applications (8)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/304,691 US9934969B2 (en) | 2014-01-31 | 2014-06-13 | Charged-particle-beam patterning without resist |
KR1020140151488A KR20150091214A (en) | 2014-01-31 | 2014-11-03 | Charged particle beam patterning without resist |
TW103145304A TWI541860B (en) | 2014-01-31 | 2014-12-24 | Process for fabricating integrated circuit |
CN201510047961.2A CN104821274B (en) | 2014-01-31 | 2015-01-29 | Charged particle beam without photoresist patterns |
KR1020170034915A KR20170034851A (en) | 2014-01-31 | 2017-03-20 | Charged particle beam patterning without resist |
KR1020170185087A KR20180018470A (en) | 2014-01-31 | 2017-12-29 | Charged particle beam patterning without resist |
US15/938,550 US10615036B2 (en) | 2014-01-31 | 2018-03-28 | Charged-particle-beam patterning without resist |
KR1020190170009A KR20190143430A (en) | 2014-01-31 | 2019-12-18 | Charged particle beam patterning without resist |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201461934418P | 2014-01-31 | 2014-01-31 | |
US14/304,691 US9934969B2 (en) | 2014-01-31 | 2014-06-13 | Charged-particle-beam patterning without resist |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
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US15/938,550 Division US10615036B2 (en) | 2014-01-31 | 2018-03-28 | Charged-particle-beam patterning without resist |
Publications (2)
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US20150221514A1 US20150221514A1 (en) | 2015-08-06 |
US9934969B2 true US9934969B2 (en) | 2018-04-03 |
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US14/304,691 Active 2035-03-16 US9934969B2 (en) | 2014-01-31 | 2014-06-13 | Charged-particle-beam patterning without resist |
US15/938,550 Active 2034-06-29 US10615036B2 (en) | 2014-01-31 | 2018-03-28 | Charged-particle-beam patterning without resist |
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US15/938,550 Active 2034-06-29 US10615036B2 (en) | 2014-01-31 | 2018-03-28 | Charged-particle-beam patterning without resist |
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US (2) | US9934969B2 (en) |
KR (4) | KR20150091214A (en) |
TW (1) | TWI541860B (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
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US11131398B2 (en) | 2018-08-14 | 2021-09-28 | Automatic Switch Company | Smart pinch valve |
US11221078B2 (en) | 2018-08-14 | 2022-01-11 | Automatic Switch Company | Pinch valve guard |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2022252707A1 (en) * | 2022-02-24 | 2022-12-08 | 袁元 | Method and apparatus for processing and controlling semiconductor device, and high-energy particle beam photolithography device |
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- 2014-12-24 TW TW103145304A patent/TWI541860B/en active
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2018
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US20150221514A1 (en) | 2015-08-06 |
KR20180018470A (en) | 2018-02-21 |
US20180218903A1 (en) | 2018-08-02 |
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KR20170034851A (en) | 2017-03-29 |
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KR20190143430A (en) | 2019-12-30 |
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