KR20050000187A - Method for forming patterns in semiconductor device using insulating-mask - Google Patents

Method for forming patterns in semiconductor device using insulating-mask Download PDF

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Publication number
KR20050000187A
KR20050000187A KR1020030040783A KR20030040783A KR20050000187A KR 20050000187 A KR20050000187 A KR 20050000187A KR 1020030040783 A KR1020030040783 A KR 1020030040783A KR 20030040783 A KR20030040783 A KR 20030040783A KR 20050000187 A KR20050000187 A KR 20050000187A
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South Korea
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insulating film
low temperature
mask
layer
film
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KR1020030040783A
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Korean (ko)
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임관용
조흥재
이정호
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주식회사 하이닉스반도체
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Priority to KR1020030040783A priority Critical patent/KR20050000187A/en
Publication of KR20050000187A publication Critical patent/KR20050000187A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/0228—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/0214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
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  • Power Engineering (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Inorganic Chemistry (AREA)
  • General Chemical & Material Sciences (AREA)
  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: A method for forming a pattern of a semiconductor device is provided to reduce manufacturing costs without forming a thick polymer photoresist layer by using a cured insulating layer as a mask pattern. CONSTITUTION: A low-temperature insulating layer(110) is formed on an etch target layer(100) by ALD(Atomic Layer Deposition) or CVD(Chemical Vapor Deposition). By using a reticle(120), the low-temperature insulating layer is selectively exposed. A cured insulating layer(110a) is formed by removing selectively the non-exposed insulating layer. The etch target layer is etched by using the cured insulating layer as a mask pattern.

Description

절연막 마스크를 이용한 반도체 소자의 패턴 형성방법{Method for forming patterns in semiconductor device using insulating-mask}Method for forming patterns in semiconductor device using insulating-mask

본 발명은 반도체 소자의 패턴 형성방법에 관한 것으로, 보다 구체적으로는 절연막을 마스크로 이용한 반도체 소자의 패턴 형성방법에 관한 것이다.The present invention relates to a method of forming a pattern of a semiconductor device, and more particularly to a method of forming a pattern of a semiconductor device using an insulating film as a mask.

반도체 소자 또는 나노 박막등의 극미세 패터닝 공정에 있어서, 일반적으로감광제(photo resist)로서 고분자 폴리머를 사용한다. 이러한 고분자 폴리머는 빛, 레이저, 전자빔등에 의하여 그 특성 및 분자 결합 상태가 바뀌어 선택적인 제거가 용이하다.In ultrafine patterning processes such as semiconductor devices or nano thin films, a polymer polymer is generally used as a photoresist. Such a polymer polymer is easily removed selectively because its properties and molecular bonding state are changed by light, laser, electron beam, and the like.

여기서, 도 1a 내지 도 1e를 참조하여, 종래의 고분자 폴리머를 이용하여 반도체 소자의 패턴을 형성하는 방법을 설명하기로 한다.1A to 1E, a method of forming a pattern of a semiconductor device using a conventional polymer will be described.

도 1a를 참조하여, 피식각층(10)이 형성된 반도체 기판(도시되지 않음)을 준비한다. 피식각층(10) 상부에 고분자 폴리머로 구성된 감광층(15)을 도포한다. 대개, 감광층(15)은 저온에서 스핀 코팅(spin coating) 방식으로 형성한다.Referring to FIG. 1A, a semiconductor substrate (not shown) on which an etched layer 10 is formed is prepared. The photosensitive layer 15 made of a polymer is coated on the etched layer 10. Usually, the photosensitive layer 15 is formed by spin coating at a low temperature.

그후, 도 1b에 도시된 바와 같이, 감광층(15) 상부에 소정의 패턴 형상이 그려진 레티클(20)을 얼라인(align)시킨다음, 광(25)을 조사한다.Thereafter, as shown in FIG. 1B, the reticle 20 having a predetermined pattern shape on the photosensitive layer 15 is aligned, and then light 25 is irradiated.

이렇게 광이 조사된 감광층(15)은 그 결합 구조가 변경되어지고, 이러한 감광층(15)을 현상액에 담그게 되면, 광(25)이 조사된 부분이 현상액에 의해 제거된다. 이에따라, 도 1c에 도시된 바와 같이, 감광 패턴(15a)이 형성된다.The bonding structure of the photosensitive layer 15 irradiated with light is changed, and when the photosensitive layer 15 is immersed in the developer, the portion irradiated with light 25 is removed by the developer. Accordingly, as shown in FIG. 1C, the photosensitive pattern 15a is formed.

그리고 나서, 도 1d에서와 같이, 감광 패턴(15a)을 마스크로 하여, 하부의 피식각층(10)을 소정 두께만큼 식각한다. 이때, 감광 패턴(15a)은 일부 제거될 수도 있다. 그후, 도 1e에서와 같이, 잔류하는 감광 패턴(15a)을 플라즈마 에슁(plasma ashing) 또는 습식 식각에 의하여 제거한다. 이에따라, 반도체 기판상에 소정의 패턴을 형성한다.Then, as shown in FIG. 1D, the lower etching target layer 10 is etched by a predetermined thickness using the photosensitive pattern 15a as a mask. In this case, the photosensitive pattern 15a may be partially removed. Thereafter, as shown in FIG. 1E, the remaining photosensitive pattern 15a is removed by plasma ashing or wet etching. As a result, a predetermined pattern is formed on the semiconductor substrate.

그러나, 상기한 고분자 폴리머로 된 감광층은 열 안정성이 열악하고, 시간이 지나면 저절로 분자 결합이 열화되는 문제점이 있다.However, the photosensitive layer made of the above polymer has a poor thermal stability, and there is a problem in that molecular bonds deteriorate by itself over time.

또한, 피식각층의 매우 단단한 물질이거나, 높이가 클 경우, 상당히 두꺼운 감광층을 사용하여야 하므로, 제조 비용이 증대될 수 있다.In addition, if the material is very hard or the height of the layer to be etched, it is necessary to use a fairly thick photosensitive layer, the manufacturing cost can be increased.

특히, 최근 서브 마이크론 이하 크기의 초극미세 패터닝 기술이 요구되는데, 이러한 경우 얇은 감광층이 요구되고, 이로 인해 하드 마스크 공정을 이용해야하므로 공정이 증대되는 문제가 있으며, 감광층의 측벽면이 매우 거칠어진다는 문제가 있다.In particular, the ultra-fine patterning technology of the sub-micron size is required recently, in this case, a thin photosensitive layer is required, due to the need to use a hard mask process, there is a problem that the process is increased, the sidewall surface of the photosensitive layer is very rough There is a problem.

따라서, 본 발명의 목적은 고분자 폴리머 감광층으로 인해 발생되는 문제를 해결할 수 있는 반도체 소자의 패턴 형성방법을 제공하는 것이다.Accordingly, an object of the present invention is to provide a method of forming a pattern of a semiconductor device that can solve the problems caused by the polymer polymer photosensitive layer.

도 1a 내지 도 1e는 종래의 반도체 소자의 패턴 형성방법을 설명하기 위한 각 공정별 단면도이다.1A to 1E are cross-sectional views of respective processes for explaining a method of forming a pattern of a conventional semiconductor device.

도 2a 내지 도 2e는 본 발명에 따른 반도체 소자의 패턴 형성방법을 설명하기 위한 공정별 단면도이다.2A through 2E are cross-sectional views illustrating processes for forming a pattern of a semiconductor device according to the present invention.

(도면의 주요 부분에 대한 부호의 설명)(Explanation of symbols for the main parts of the drawing)

100 : 피식각층 110 : 저온 절연막100: etching target layer 110: low temperature insulating film

110a : 경화된 절연막 100a : 패턴110a: cured insulating film 100a: pattern

상기한 본 발명의 목적을 달성하기 위하여, 본 발명은, 피식각층 상부에 저온 절연막을 형성하는 단계, 상기 저온 절연막상에 레티클을 배치시키고, 노광시키는 단계, 상기 노광되지 않은 저온 절연막을 선택적으로 제거하여, 절연 마스크를 형성하는 단계, 및 상기 절연 마스크의 형태로 피식각층을 식각하는 단계를 포함한다.In order to achieve the above object of the present invention, the present invention, forming a low temperature insulating film on the etched layer, placing a reticle on the low temperature insulating film, exposing, and selectively removing the unexposed low temperature insulating film Forming an insulating mask, and etching the etching target layer in the form of the insulating mask.

상기 저온 절연막은 0 내지 350℃의 온도에서 증착하는 것이 바람직하다. 이러한 상기 저온 절연막은 ALD 방식 또는 CVD 방식으로 증착할 수 있다. 상기 저온 절연막은 실리콘 산화막, 실리콘 질화막, 실리콘 질산화막 및 고유전막 중 선택되는 하나가 이용될 수 있고, 약 50 내지 10000℃의 두께로 형성된다.The low temperature insulating film is preferably deposited at a temperature of 0 to 350 ℃. The low temperature insulating film may be deposited by ALD method or CVD method. The low temperature insulating film may be one selected from a silicon oxide film, a silicon nitride film, a silicon nitride oxide film and a high dielectric film, and is formed to a thickness of about 50 to 10000 ° C.

상기 노광하는 단계는, 상기 저온 절연막에 레이저, X-레이, 이온 빔 또는 전자 빔을 조사하는 것이다.The exposing step is irradiating a laser, an X-ray, an ion beam, or an electron beam to the low temperature insulating film.

상기 노광되지 않은 저온 절연막은 F, Cl, Br 및 I와 같은 할로겐 원소를 포함하는 기체 또는 액체, 또는 플라즈마에 의하여 제거할수 있다.The unexposed low temperature insulating film may be removed by a gas or liquid containing a halogen element such as F, Cl, Br, and I, or a plasma.

상기 절연 마스크를 형성하는 단계와, 상기 절연 마스크의 형태로 피식각층을 식각하는 단계 사이에, N2 또는 H2 가스를 포함한 기체 또는 진공 분위기에서 500 내지 1000℃의 온도로 10 초 내지 1 시간동안 상기 절연 마스크를 추가로 경화시키는 단계를 더 포함할 수 있다.Between the step of forming the insulating mask and etching the etched layer in the form of the insulating mask, the insulation for 10 seconds to 1 hour at a temperature of 500 to 1000 ℃ in a gas or vacuum atmosphere containing N2 or H2 gas The method may further include curing the mask.

(실시예)(Example)

이하 첨부한 도면을 참조하여 본 발명의 양호한 실시예를 설명하도록 한다.Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

첨부한 도면 도 2a 내지 도 2d는 본 발명에 따른 반도체 소자의 패턴 형성방법을 설명하기 위한 각 공정별 단면도이다.2A to 2D are cross-sectional views of respective processes for explaining a method of forming a pattern of a semiconductor device according to the present invention.

도 2a를 참조하여, 피식각층(100)이 형성된 반도체 기판을 준비한다. 본 도면에서는 피식각층(100)을 도시한다. 피식각층(100) 상부에 저온 절연막(110)을 증착한다. 저온 절연막(110)은 0 내지 350℃의 저온에서 ALD(atomic layer deposition) 또는 CVD(chemical vapor deposition) 방식으로 형성한다. 이때, 저온에서 증착되는 절연막은 그 막질이 치밀하지 못하고 분자 결합이 매우 약하기 때문에, 추가로 열처리를 해주지 않는 한 식각이 잘되는 특징이 있으며, 열처리가 진행된 막은 그 막질이 매우 치밀해져서 600℃ 이상의 고온에서 형성된 절연막과 거의동일한 특징을 갖게 된다. 이러한 절연막(110)으로는 실리콘 산화막이 이용될 수 있다. 이때, 실리콘 산화막은 실리콘 소스 및 산소 소스를 이용하여 증착될 수 있다. 실리콘 소스로는 SiCl6, SiCl4, SiCl2H2, SiH4, SiF4, SiF6가 이용될 수 있고, 산소 소스로는 O2, O3, H2O, D2O, No, N2O등이 이용될 수 있다. 또한, 절연막(110)으로는 실리콘 산화막 외에, 실리콘 질화막(SiN), 실리콘 질산화막(SiON)막 또는 HfO2, ZrO2, Ta2O5, Al2O3, La2O3, Y2O3 및 CeO2와 같은 고유전막이 이용될 수 있다. 이러한 저온 절연막(110)은 예를 들어 50 내지 1000Å 두께로 증착한다.Referring to FIG. 2A, a semiconductor substrate on which an etched layer 100 is formed is prepared. In this figure, the etching target layer 100 is illustrated. The low temperature insulating layer 110 is deposited on the etched layer 100. The low temperature insulating film 110 is formed by atomic layer deposition (ALD) or chemical vapor deposition (CVD) at a low temperature of 0 to 350 ° C. At this time, since the insulating film deposited at a low temperature is not dense and the molecular bonding is very weak, there is a feature that the etching is good unless additional heat treatment, the film is heat treatment is very dense the film quality is very high at 600 ℃ or higher It has almost the same characteristics as the formed insulating film. As the insulating film 110, a silicon oxide film may be used. In this case, the silicon oxide film may be deposited using a silicon source and an oxygen source. SiCl 6, SiCl 4, SiCl 2 H 2, SiH 4, SiF 4, SiF 6 may be used as the silicon source, and O 2, O 3, H 2 O, D 2 O, No, N 2 O, or the like may be used as the oxygen source. In addition to the silicon oxide film, a silicon nitride film (SiN), a silicon nitride oxide (SiON) film, or a high dielectric film such as HfO 2, ZrO 2, Ta 2 O 5, Al 2 O 3, La 2 O 3, Y 2 O 3, and CeO 2 may be used as the insulating layer 110. The low temperature insulating film 110 is deposited to have a thickness of, for example, 50 to 1000 mW.

도 2b에 도시된 바와 같이, 저온 절연막(110) 상부에 소정의 패턴이 그려진 레티클(120)을 배치시킨다음, 광(130), 예를 들어 레이저, X-레이, 이온 빔 또는 전자 빔을 조사한다. 이때, 광이 조사된 저온 절연막(110)은 광(130)에 의하여 경화되어, 막질이 치밀해진 상태가 된다. 이때, 미설명 도면 부호 110a는 경화된 저온 절연막 부분을 나타낸다.As shown in FIG. 2B, the reticle 120 having a predetermined pattern is disposed on the low temperature insulating layer 110 and then irradiated with light 130, for example, a laser, an X-ray, an ion beam, or an electron beam. do. At this time, the low-temperature insulating film 110 to which light is irradiated is cured by the light 130, and the film quality becomes dense. In this case, reference numeral 110a denotes a hardened low temperature insulating film portion.

그후, 도 2c에 도시된 바와 같이, 레티클(120)에 의하여 선택적으로 광이 조사된 저온 절연막(110)을 현상한다. 이때, 현상 공정은 F, Cl, Br 및 I와 같은 할로겐 원소를 포함하는 기체 또는 액체, 또는 플라즈마 의하여 진행된다. 이러한 현상 공정으로, 광이 조사되지 않은 절연막(110) 부분은 상기 현상 공정에 의하여 제거되고, 광이 조사된 절연막(110)은 경화되어 잔류된다. 이에따라, 절연 마스크(110a)가 형성된다. 그후, 절연 마스크(110a)의 치밀도를 보다 향상시키기 위하여, N2 또는 H2가 포함된 기체 또는 진공 분위기에서 500 내지 1000℃의 온도로 10초 내지 1시간동안 열처리를 진행할 수 있다.Thereafter, as shown in FIG. 2C, the low temperature insulating film 110 to which light is selectively irradiated by the reticle 120 is developed. At this time, the developing process is performed by a gas or liquid containing a halogen element such as F, Cl, Br and I, or a plasma. In this development process, the portion of the insulating film 110 to which light is not irradiated is removed by the developing process, and the insulating film 110 to which light is irradiated is cured and remains. Accordingly, the insulating mask 110a is formed. Thereafter, in order to further improve the density of the insulating mask 110a, heat treatment may be performed for 10 seconds to 1 hour at a temperature of 500 to 1000 ° C. in a gas or vacuum atmosphere containing N 2 or H 2.

도 2d를 참조하여, 절연 마스크(110a)의 형태로 노출된 피식각층(100)을 식각한다. 이때, 절연 마스크(110a)는 그 치밀도가 탁월하므로, 피식각층(100)만을 선택적으로 식각할 수 있다.Referring to FIG. 2D, the etched layer 100 exposed in the form of the insulating mask 110a is etched. In this case, since the insulating mask 110a has an excellent density, only the etching target layer 100 may be selectively etched.

그후, 도 2e에 도시된 바와 같이, 절연 마스크(110a)를 공지의 방식으로 제거하여, 패턴(100a)을 형성한다.Thereafter, as shown in FIG. 2E, the insulating mask 110a is removed in a known manner to form the pattern 100a.

이상에서 자세히 설명한 바와 같이, 본 발명에 의하면, 저온 절연막을 도포하고, 노광에 의하여 상기 저온 절연막을 선택적으로 경화시켜, 경화된 절연막 부분을 마스크 패턴으로 이용한다. 이에 따라, 두꺼운 고분자 폴리머 감광층을 형성할 필요가 없으므로 제조 비용을 줄일 수 있고, 극미세 패터닝시 하드 마스크막을 형성하는 공정을 배제할 수 있다.As described in detail above, according to the present invention, a low temperature insulating film is coated, the low temperature insulating film is selectively cured by exposure, and the cured insulating film portion is used as a mask pattern. As a result, it is not necessary to form a thick polymer polymer photosensitive layer, thereby reducing manufacturing costs and eliminating a process of forming a hard mask film during ultrafine patterning.

기타 본 발명의 요지를 벗어나지 않는 범위에서 다양하게 변경 실시할 수 있다.Other changes can be made without departing from the spirit of the invention.

Claims (9)

피식각층 상부에 저온 절연막을 형성하는 단계;Forming a low temperature insulating film on the etched layer; 상기 저온 절연막상에 레티클을 배치시키고, 노광시키는 단계;Placing a reticle on the low temperature insulating film and exposing the reticle; 상기 노광되지 않은 저온 절연막을 선택적으로 제거하여, 절연 마스크를 형성하는 단계; 및Selectively removing the unexposed low temperature insulating film to form an insulating mask; And 상기 절연 마스크의 형태로 피식각층을 식각하는 단계를 포함하는 반도체 소자의 패턴 형성방법.And etching the etched layer in the form of the insulating mask. 제 1 항에 있어서, 상기 저온 절연막은 0 내지 350℃의 온도에서 증착하는 것을 특징으로 하는 반도체 소자의 패턴 형성방법.The method of claim 1, wherein the low temperature insulating film is deposited at a temperature of 0 to 350 ° C. 6. 제 1 항 또는 제 2 항에 있어서, 상기 저온 절연막은 ALD 방식으로 증착하는 것을 특징으로 하는 반도체 소자의 패턴 형성방법.The method of claim 1, wherein the low temperature insulating film is deposited by an ALD method. 제 1 항 또는 제 2 항에 있어서, 상기 저온 절연막은 CVD 방식으로 증착하는 것을 특징으로 하는 반도체 소자의 패턴 형성방법.The method of claim 1, wherein the low temperature insulating film is deposited by a CVD method. 제 1 항 또는 제 2 항에 있어서, 상기 저온 절연막은 실리콘 산화막, 실리콘 질화막, 실리콘 질산화막 및 고유전막 중 선택되는 하나인 것을 특징으로 하는 반도체 소자의 패턴 형성방법.The method of claim 1, wherein the low temperature insulating film is one selected from a silicon oxide film, a silicon nitride film, a silicon nitride oxide film, and a high dielectric film. 제 1 항 또는 제 2 항에 있어서, 상기 저온 절연막의 두께는 50 내지 10000Å인 것을 특징으로 하는 반도체 소자의 패턴 형성방법.The pattern forming method of a semiconductor device according to claim 1 or 2, wherein the low-temperature insulating film has a thickness of 50 to 10000 GPa. 제 1 항에 있어서, 상기 노광하는 단계는, 레이저, X-레이, 이온 빔 또는 전자 빔을 조사하는 것을 특징으로 하는 반도체 소자의 패턴 형성방법.The method of claim 1, wherein the exposing comprises irradiating a laser, an X-ray, an ion beam, or an electron beam. 제 1 항에 있어서, 상기 노광되지 않은 저온 절연막을 선택적으로 제거하는 단계는, F, Cl, Br 및 I와 같은 할로겐 원소를 포함하는 기체 또는 액체, 또는 플라즈마에 의하여 제거하는 것을 특징으로 하는 반도체 소자의 패턴 형성방법.The semiconductor device of claim 1, wherein the removing of the unexposed low-temperature insulating layer is performed by a gas, a liquid, or a plasma containing a halogen element such as F, Cl, Br, and I. 3. Pattern formation method. 제 1 항에 있어서, 상기 절연 마스크를 형성하는 단계와, 상기 절연 마스크의 형태로 피식각층을 식각하는 단계 사이에, N2 또는 H2 가스를 포함한 기체 또는 진공 분위기에서 500 내지 1000℃의 온도로 10 초 내지 1 시간동안 상기 절연 마스크를 추가로 경화시키는 단계를 더 포함하는 것을 특징으로 하는 반도체 소자의 패턴 형성방법.10. The method of claim 1, wherein between the forming of the insulating mask and etching the etched layer in the form of the insulating mask, at a temperature of 500 to 1000 ° C. in a gas or vacuum atmosphere containing N 2 or H 2 gas. And further curing the insulating mask for 1 to 1 hour.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10615036B2 (en) 2014-01-31 2020-04-07 Taiwan Semiconductor Manufacturing Company, Ltd. Charged-particle-beam patterning without resist

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10615036B2 (en) 2014-01-31 2020-04-07 Taiwan Semiconductor Manufacturing Company, Ltd. Charged-particle-beam patterning without resist

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