CN102027572A - 使用共形等离子体增强化学气相沉积(pecvd)膜来缩减关键尺寸的方法 - Google Patents
使用共形等离子体增强化学气相沉积(pecvd)膜来缩减关键尺寸的方法 Download PDFInfo
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- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
- IGELFKKMDLGCJO-UHFFFAOYSA-N xenon difluoride Chemical compound F[Xe]F IGELFKKMDLGCJO-UHFFFAOYSA-N 0.000 description 1
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Abstract
在此提出用于在基板中形成狭窄通孔的方法和设备。利用传统微影技术将图案凹部蚀入基板内。薄共形层形成在基板表面上,包括图案凹部的侧壁和底部上。共形层厚度缩减了图案凹部的有效宽度。利用非等向性蚀刻移除图案凹部底部的共形层而露出下面的基板。接着使用覆盖住图案凹部侧壁的共形层做为罩幕来蚀刻基板。然后使用湿蚀刻剂移除共形层。
Description
技术领域
本发明实施例是有关半导体制造方法。更具体而言,本发明实施例是关于缩减半导体组件的关键尺寸的方法。
背景技术
半导体产业已遵循摩耳定律(Moore’s Law)超过半个世纪,摩耳定律是指集成电路上的晶体管密度约每两年会增加一倍。半导体产业依此规则持续发展,将需要在基板上图案化更小的特征结构。目前生产的堆栈晶体管尺寸为50至100纳米(nm)。现已能生产尺寸为45nm的组件,并致力于设计尺寸为20nm或更小的组件。
随着组件缩减成如此小的尺寸,现有的微影工艺面临难以制造出所需关键尺寸(critical dimension,CD)图案的困境。用于制造100nm或更宽通孔的图案化工具通常不能制造更小的通孔。
为了避免重新设计现有微影工具,需要缩减蚀入基板的通孔关键尺寸的方法。
发明内容
本发明实施例提出缩减凹部的关键尺寸的方法,凹部形成在具有场区的基板中并且具有侧壁和底部,方法包括涂覆共形层至场区、侧壁和底部上;利用方向性蚀刻工艺移除在底部处的共形层而露出基板;蚀刻在底部露出的基板;以及利用湿蚀刻工艺移除共形层。共形层具有良好的阶梯覆盖,并可利用任何用来沉积共形层的手段来沉积,且共形层对于用来蚀刻在共形层底下各膜层的蚀刻剂具高选择性。
其它实施例提出在基板的场区中形成通孔的方法,包含图案化形成在基板表面上的膜层,以形成具有侧壁和底部的凹部;经由涂覆共形膜至该膜层上而缩减凹部的宽度;移除在凹部底部的共形膜而露出部分基板,以形成关键尺寸缩减区域;以及蚀刻关键尺寸缩减区域而形成通孔。
其它实施例提出图案化一形成在基板上的介电层的方法,包含形成图案转移层至介电层上;借着涂覆光阻、图案化该光阻及将图案蚀刻入图案转移层中来图案化该图案转移层,以形成具底部的凹部;沉积第一共形层至图案转移层上;移除在凹部底部的第一共形层而露出介电层;蚀刻介电层的露出部分而形成狭窄凹部;移除图案转移层和共形层;沉积第二共形层至基板上;以及移除在该狭窄凹部的底部处的第二共形层。一些实施例提出在图案形成期间加倍缩减关键尺寸(CD)的方法。
附图说明
为更详细了解本发明的上述特征,可参阅数个实施例对本发明做更具体说明,部分实施例绘示于附图中。须注意的是,所附图式揭露的仅是本发明的代表性实施例,但其并非用以限定本发明的精神与范围,本发明可能具有其它等效实施例。
图1A为根据本发明一实施例的工艺流程图。
图1B-1F为图1A工艺的不同阶段的基板示意图。
图2A为根据本发明另一实施例的工艺流程图。
图2B-2H为图2A工艺的不同阶段的基板示意图。
图3A为根据本发明又一实施例的工艺流程图。
图3B-3D为图3A工艺的不同阶段的基板示意图。
图4A为根据本发明再一实施例的工艺流程图。
图4B-4G为图4A工艺的不同阶段的基板示意图。
图5A为根据本发明另一实施例的工艺流程图。
图5B-5H为图5A工艺的不同阶段的基板示意图。
为助于了解,尽可能地使用相同的组件符号代表各图中相同的组件。应理解某一实施例揭露的组件当可有利地应用于其它实施例中,在此不另外详述。
具体实施方式
本发明大体上是关于处理基板的方法。本发明的实施例提出在基板内形成凹部或通孔的方法,其中凹部或通孔的关键尺寸比利用传统微影工艺所得到的关键尺寸要小。
图1A为根据本发明一实施例的方法100的流程图。图1B-1F为基板150于方法100的不同阶段的示意图。将基板放到处理腔室内,例如在基板中形成有一凹部的基板150。图1B绘示基板150具有待蚀刻的特征结构层152和形成在位于特征结构层152上的图案转移层154中的凹部或开口156。特征结构层152可为任何期望蚀刻种类的介电或半导体层。图案转移层154可为硬罩幕层(hard mask layer)、抗反射层、介电层或上述膜层的任意组合。凹部156具有侧壁和露出特征结构层152的底部,并可做为后续图案化阶段的蚀刻图案。
在方法100的步骤102中,涂覆一共形层至基板表面。图1C绘示共形层158覆盖住图案转移层154的场区和凹部156的侧壁与底部。共形层158较佳是由对用来蚀刻特征结构层152的任何蚀刻剂具有低蚀刻速度的材料组成。例如,在特征结构层152是将要使用氟化学剂来蚀刻的氧化物层的实施例中,共形层158可为含氮层,例如氮化物层。在一些实施例中,共形层158为氮化硅层、氮化硼层、氮化硼硅层、掺杂硅的氮化硼层或掺杂硼的氮化硅层。此外,共形层158较佳能轻易地从基板上移除,例如利用灰化或湿蚀刻。
在一些实施例中,共形层是将于后续处理阶段中移除的牺牲层。如下所述,在其它实施例中,共形层可能是将会变成部分结构并且贡献其最终性质的介电层。在一些实施例中,共形层为密封层(hemetic layer.)。在其它实施例中,共形层为阻障层或抗反射层。共形层的阶梯覆盖较佳介于约80%至约120%之间。
如下所述,在步骤102中,共形层158将当作蚀刻罩幕,且共形层158的厚度将界定蚀入特征结构层152中的图案关键尺寸。例如,凹部156宽度为500埃时,宽度的共形层158将会使凹部156的宽度缩减成使得后续蚀刻程序将于特征结构层152内产生宽度的图案。此工艺有助于形成关键尺寸比使用特殊微影设备所能形成的关键尺寸还要小的图案。
可使用任何已知用于沉积共形层至基板上的方法来沉积共形层(如共形层158)。此类方法的例子包括化学气相沉积(CVD)、等离子体增强CVD(PECVD)、原子层外延(ALE)、原子层沉积(ALD)和等离子体增强ALD(PEALD),但不以此为限。氮化硅共形层可使用ALD或PEALD工艺来沉积,其中前体可为脉冲供应到含基板的反应器中的任何硅烷寡聚物(例如甲硅烷或二硅烷)、低级烷基硅烷(如甲基或二甲基硅烷)或低级烷氧硅烷、硅醇(silanol)或硅氮烷(silazane),且交替流入含氮化合物,例如氮气(N2)、氨气(NH3)、一氧化二氮(N2O,又名氧化亚氮或笑气)或联氨(N2H2)。载气常用来协助提供前体及净化反应器。在适当条件下,前体与基板表面反应形成沉积产物层,沉积产物层会均匀地成长在整个基板表面。可依需求重复进行工艺以达期望厚度。同样地,可利用ALD或PEALD工艺使用硼烷寡聚物(如甲硼烷或二硼烷)且交替流入含氮前体(例如N2、NH3、N2O或N2H2)来制作氮化硼层。可使用硼前体与硅前体的混合气体按照近似预期掺杂量的比例来达成掺杂。
在方法100的步骤104中,蚀刻掉覆盖在凹部底部处的共形层部分而露出底下的部分特征结构层152。图1D绘示已移除位在凹部156底部160处的共形层158的基板。可利用选择性蚀刻工艺移除在凹部156的底部160上的共形层158,在一些实施例中,选择性蚀刻工艺为方向性或非等向性(anisotropic)蚀刻工艺,用以只蚀刻基板水平表面的材料。此工艺较佳使用等离子体蚀刻剂及施加电偏压至基板来促使等离子体中的离子加速朝向基板表面。在此工艺中,加速的离子在转向侧壁之前,通常会更深入凹部156,导致大多数的反应物种撞击凹部156的底部160。同时,此工艺还可实质移除在图案转移层154的场区处的共形层158。用于本发明实施例的选择性蚀刻工艺一范例为使用氟与氧离子的反应离子蚀刻。也可实行其它蚀刻方法,例如非反应性离子蚀刻。
露出共形层158底下的部分特征结构层152后,在步骤106中,蚀刻该特征结构层152。图1E绘示处于方法100的此阶段中的基板。仍保留在凹部156侧壁上的部分共形层158缩减了凹部156宽度,并且该部分特征结构层152暴露至蚀刻剂。若共形层158是由对于用来蚀刻特征结构层152的蚀刻剂具有高蚀刻选择性的材料所组成,则在步骤106中,将缓慢或不蚀刻共形层158,而留下蚀入特征结构层152内且关键尺寸(CD)被缩减的通孔162。可利用任何已知用于蚀刻特征结构层152的材料的方法来蚀刻特征结构层152,但较佳是使用不会蚀刻共形层158的工艺。同时亦部分蚀去图案转移层154而留下厚度缩减层154。方向性蚀刻(例如在偏压下使用反应性或非反应性离子的蚀刻方法)有利于在蚀刻介电层152时保留共形层158的留存部分。
在步骤108中,如图1F所示,移除共形层158而留下具有CD缩减通孔的基板供后续处理。一般亦利用蚀刻或氧化手段来移除图案转移层154。CD缩减通孔162比传统微影技术所制得的通孔更窄。
本发明的其它实施例提出于基板的场区中形成通孔的方法。图2A为根据本发明一实施例的方法200的流程图。将待蚀刻的基板放到处理腔室内。图2B为将依据方法200进行处理的基板250示意图。示范的基板(例如基板250)具有底层252、堆栈结构254、保护层256和绝缘或介电层258。
在步骤202中,将图案转移层涂覆至基板。图案转移层将当作后续蚀刻程序的蚀刻罩幕。图案转移层可为介电层、抗反射层或阻障层,并可具备一种以上的这类性质。包含sp3(钻石状)、sp2(石墨状)与sp1(热解碳状)混成的碳原子混合物的无定形碳层可做为图案转移层,其是利用碳氢化合物前体进行CVD工艺而得。无定形碳层的其中一范例为PRODUCERSE和GT PECVD平台制造的APFAdvanced Patterning FilmTM,PRODUCERSE和GT PECVD平台可购自美国加州圣克拉拉的应用材料公司(Applied Materials,Inc.)。待蚀刻的基板一般放在处理腔室内来形成图案转移层。基板可置于基板支撑件上,基板支撑件当作用于产生电容耦合等离子体的电极,并控制基板温度。在另一实施例中,基板支撑件用来施加电偏压至基板,以进行等离子体的方向性沉积。经由配置除了基板支撑件以外的电极,例如侧边极板、喷头电极、扩散板等,也可在处理腔室内产生电容耦合等离子体。腔室侧壁可做为等离子体产生电极。在又一实施例中,可透过设在腔室顶部且安装有感应线圈的回流管(re-entrant tube)来诱导耦合产生等离子体。最后,在一些实施例中,可远程产生等离子体并且供给至腔室。用于形成图案转移层的示范等离子体腔室细节可参见美国专利5,855,681和6,495,233。
无定形碳为一示范的图案转移层。为区别一般用于建立图案的「软」光阻,无定形碳又称为「硬罩幕」,此将进一步说明于后,经由提供碳源至内部放置有基板的处理腔室,可形成无定形碳图案转移层。在一些实施例中,碳源为丙烯或乙炔(acetylene),但较佳为具有适合蒸气压和游离能(ionization potential)而可轻易活化的前体。通常施加RF功率以将碳前体离子化成反应性等离子体。在一些实施例中,电压施加至基板,使反应性离子加速朝向基板表面,进而促进沉积于基板表面上。
在步骤204中,形成光阻层至图案转移层上。光阻一般为对某一种电磁辐射波长敏感的聚合物材料,并可以旋涂工艺或CVD工艺涂覆而得。在一些实施例中,光阻为对于紫外光敏感的碳基聚合物,例如酚醛树脂(phenolic resin)、环氧树脂或偶氮环烷树脂(azo napthenic resin)。光阻层可为正型或负型光阻。较佳的正型光阻选自于由248纳米(nm)光阻、193nm光阻、157nm光阻和具有重氮萘酚醌(diazonapthoquinone)感光剂的酚醛树脂基质组成的群组中。较佳的负型光阻选自于由聚顺异戊二烯(poly-cis-isoprene)和聚乙烯醇肉桂酸酯(poly-vinylcinnamate)组成的群组中。在一些实施例中,光阻层更包含底部抗反射涂层(BARC层),BARC层和光阻层可利用旋涂工艺沉积而得。
在步骤204中,图案化光阻层及显影图案。图2C绘示处于此工艺阶段中的基板250。图案转移层260已形成在介电层258上。光阻层262位于图案转移层260上,并具有图案开口264而露出底下的图案转移层260。
在图2B-2H的实施例中,蚀刻光阻而得的图案呈现多个开口264。开口264最终用来形成组件254的栅极堆栈结构和源极与汲极接合面的接触通孔。使用CD缩减图案来形成接触通孔有利于减少接触点之间的电容互相作用或交叉干扰。缩减通孔的CD可加大彼此之间的距离,进而减少通孔内的接触点发生电容耦合。
在步骤208中,将图案转移到图案转移层中。可利用任何适合的工艺将图案蚀入图案转移层中。在图案转移层为无定形碳层的示范性实施例中,利用包含氧气(O2)与氮气(N2)组合物、或含甲烷(CH4)、氮气(N2)与氧气(O2)组合物的等离子体蚀刻工艺来蚀刻该图案。图2D绘示处于方法200的此阶段中的基板250。图案转移层260已蚀刻而形成有开口或凹部266。写入光阻层262中的图案开口264的宽度决定了开口266宽度。在此阶段中亦已移除光阻层。在一些实施例中,光阻和图案转移层主要为碳原子,故可使用实质相同的蚀刻化学剂来移除光阻和转移该蚀刻图案。
在步骤210中,共形层形成在基板上。图2E绘示处于此工艺阶段中的基板250。共形层268位于基板上而形成宽度缩减的凹部270。共形膜可使用任何适用于形成共形膜的工艺来形成。共形膜均匀地缩减了开口266的宽度。共形膜的阶梯覆盖较佳为介于约80%至约120%,并且是由对于用来蚀刻下方介电层258的蚀刻剂具有低蚀刻速度的材料所组成。在介电层258为氧化物层的示范实施例中,例如多孔碳氧化硅低k或超低k介电层,共形膜可为含氮膜。氮化硅、氮化硼和氮化硼硅为适合此方法的示范膜层。沉积共形膜的工艺例如为原子层外延(ALE)、原子层沉积(ALD)和化学气相沉积(CVD)。这些工艺可用等离子体增强。
一般来说,氮化硅沉积层或膜的实验式或化学式为SiNx。完全氮化的氮化硅化学式为Si3N4,此时N∶Si原子比值为约1.33。氮化程度较低的氮化硅材料的N∶Si比值可低至约0.7。因此,氮化硅材料的N∶Si比值为约0.7至约1.33,较佳约0.8至约1.3。除了硅和氮外,氮化硅材料还可含有其它元素,例如氢、碳、氧及/或硼。在一些实施例中,氮化硅材料的氢浓度为约8重量%(wt%)或更高。氮化硅材料的碳浓度为约3原子%(at%)至约5at%。氮化硅材料包括氮化硅(SiNx)、氮氧化硅(SiOxNy)、氮化碳硅(SiCxNy)和氮氧化碳硅(SiCxOyNz)。经由控制工艺条件可改变氮化硅材料的化学计量和组成。
也可形成化学计量比约1∶1的氮化硼膜。可使用本文中所述的工艺来形成含有BxNy组成的膜层,其中x∶y比值为介于约0.9至约1.1。经由控制工艺条件可调整氮化硼膜的组成。
某些膜含有硅、硼和氮。在一些实施例中,形成掺杂硼的氮化硅膜。在其它实施例中,形成掺杂硅的氮化硼膜。在又一实施例中,形成硅、硼与氮化学计量比相近(即1∶1∶1)的氮化硼硅膜。在其它实施例中,任一上述膜亦可掺杂或含有氢、碳、卤素(如氯或氟)、氧或其它掺质。
在ALE或ALD工艺中,依序提供数种化学前体至处理腔室,并于各步骤之间净化腔室。在用于沉积氮化硼共形层的示范工艺中,提供硼前体至处理腔室,例如硼烷(BH3)、其它硼烷寡聚物(如二硼烷(B2H6))、氮硼苯(borazine,B3N3H6)、烷基氮硼苯、三甲基硼(B(CH3)3)或三氯化硼(BCl3)。载气有助于脉冲输入前体至处理腔室。载气可为非反应性气体,例如氦气(He)、氩气(Ar)、氮气(N2)或氙气(Xe)。载气可持续流动,前体则脉冲供应至载气气流中;或者载气可间歇流动并脉冲输入前体。硼前体沉积后,利用净化气体脉冲或连续流动非反应性载气来净化腔室。第二含氮前体,例如氮气(N2)、氨气(NH3)、一氧化二氮(N2O)或联氨(N2H2)接着脉冲供应至腔室以进行反应。氮步骤之后跟着净化步骤。反复进行此循环,直到沉积膜达预定厚度为止。沉积氮化硅膜时,使用硅前体来代替硼前体,例如低级硅烷、硅氧烷、硅醇或硅氮烷、或上述硅前体的烷基、苯基与氨基衍生物。甲硅烷(SiH4)和甲基硅烷(MeSiH3)为例子。此外,也可采用环状衍生物(例如经取代的环硅氧烷与环硅氮烷)和卤素衍生物。在一些实施例中,共形层可额外掺杂选自于由碳(C)、氟(F)、氮(N)、氧(O)、硅(Si)、氯(Cl)和氢(H)所组成的群组中的原子。
在一些实施例中,使用超过两种的前体。以沉积氮化硼硅共形层为例,可提供例如上列的含硅前体至处理腔室以沉积含硅物种。进行净化步骤后,提供上述硼前体以将硼加入该层中,接着提供上述氮前体以将氮加入该层中。可依需求反复进行此三阶段式的循环,而建构出具有预定化学组成和厚度的共形层。
在用于沉积如本文所述共形膜的ALD工艺中,开始进行ALD工艺之前,基板先经过预洗工艺和表面预理处理。这些初步处理移除了基板上表面上的任何原生氧化物,并使表面具有设计用来促进ALD工艺的官能基末端。附接或形成于基板表面上的官能基包括羟基(OH)、烷氧基(OR,其中R=Me、Et、Pr或Bu)、卤氧基(OX,其中X=F、Cl、Br或I)、卤素(F、Cl、Br或I)、氧自由基,和酰胺基(NR或NR2,其中R=H、Me、Et、Pr或Bu)。预洗工艺可使基板接触一试剂,例如氨气(NH3)、二硼烷(B2H6)、甲硅烷(SiH4)、二硅烷(Si2H6)、水(H2O)、氢氟酸(HF)、盐酸(HCl)、氧气(O2)、臭氧(O3)、过氧化氢(H2O2)、氢气(H2)、H原子、N原子、O原子、醇、胺或上述试剂的等离子体、衍生物或组合物。官能基提供基底而让导入的化学前体连接至基板上表面。在一些实施例中,预洗工艺使基板上表面接触试剂的时间为约1秒至约2分钟。在一些实施例中,接触时间为约5秒至约60秒。预洗工艺还可包括使基板表面接触RCA溶液(SC1/SC2)、HF最终液、过氧化物溶液、酸性溶液、碱性溶液或上述物质的等离子体、衍生物或组合物。在一些实施例中,基板浸泡在氢氟酸浴中约2-15分钟。在一实施例中,基板浸泡在2%的氢氟酸浴中约2分钟。在一些实施例中,预洗工艺可在批式清洁系统或单一基板清洁系统中完成。单一基板清洁系统的其中一范例为OASIS CLEAN系统,其可购自美国加州圣克拉拉的应用材料公司。
施加RF功率来产生等离子体可促进ALE或ALD工艺。RF功率可在整个脉冲输入及净化步骤过程中连续施加或选择性施加。一般最好为诱导耦合(inductively coupled)或弱电容耦合等离子体,以免造成高方向性沉积。
在用于沉积氮化硼膜的热CVD工艺中,提供硼前体和氮前体至处理腔室,其流速分别为约每分钟5标准立方厘米(sccm)至约每分钟50标准升(slm),例如约10sccm至约1slm。在一实施例中,还可提供非反应性气体(如载气),其流速为介于约5sccm至约50slm之间,例如约10sccm至约1slm。腔室压力维持呈约10毫托耳至约760托耳,例如约2托耳至约20托耳,基板温度为介于约100℃至约1000℃,例如介于约300℃至约500℃。
在用于沉积氮化硼膜的PECVD工艺中,施加RF功率来活化前体。RF功率可以介于约2瓦(W)至约5000W(例如约30W至约1000W)的功率大小与约100kHz至约1MHz(如约300kHz至约400kHz)的单一低频来提供,或可以约2W至约5000W(如约30W至约1000W)的功率大小与大于约1MHz(如大于约1MHz至约60MHz,例如13.6MHz)的单一高频提供。或者,可使用混合频率来提供RF功率,包括以介于约100kHz至约1MHz(如约300kHz至约400kHz)的第一频率与约2W至约5000W(如约30W至约1000W)的功率大小,以及大于约1MHz(如大于约1MHz至约60MHz,例如13.6MHz)的第二频率与约2W至约5000W(如约30W至约1000W)的功率大小来提供。
在另一实施例中,含硼前体和含氮前体为同时引入,含硅前体亦可伴随含硼前体和含氮前体引入腔室而形成SiBN层。沉积SiBN层的范例处理条件包括引进流速60sccm的甲硅烷(SiH4)、流速600sccm的氨气(NH3)、流速1000sccm的氮气(N2)、流速100-1000sccm的二硼烷(B2H6),并以100W RF功率、13.6MHz产生等离子体,同时将腔室条件维持成腔室压力为6托耳、间距为480密尔。视情况而定,SiBN层可在400℃下使用紫外线(UV)固化10分钟。
在用于沉积氮化硼层的ALD工艺中,使用约4∶1至约6∶1(如约5∶1)的二硼烷和氮气做为前体,并以每循环的沉积速度来沉积氮化硼层。例如,在腔室压力6托耳、间距480密尔下,提供400sccm的二硼烷和2000sccm的氮气,历时5秒/循环,以及利用等离子体工艺处理所产生的膜层而将氮并入膜层内而形成氮化硼层,其中等离子体工艺包含使用100sccm的氨气和2000sccm的氮气,以300W的RF功率、13.6MHz的频率施行10秒/循环。
根据不同工艺可共形沉积含硅与氮层。在一些工艺中,基板表面被暴露至硅前体和无氨反应物。硅前体包括烷氨基硅烷,例如双叔丁基氨基硅烷(bis(tertiaryamino)silane,BTBAS),无氨反应物则例如氢、硅烷、硼烷、锗烷、烷烃、胺或联氨等化合物。其可在热CVD工艺、脉冲式CVD工艺或ALD工艺中暴露至反应物,并活化成等离子体。
在一工艺中,硅前体和反应物相继脉冲输入至内含基板的处理腔室中,以完成ALD工艺。硅前体供给至处理腔室的流速为约1sccm至约300sccm,较佳约10sccm至约100sccm。例如,BTBAS的流速为约13sccm至约130sccm,根据BTBAS分压和露出表面积,此相当于约0.1克/分钟至约1.0克/分钟的流率。反应物供给至处理腔室的流速为约100sccm至约3000sccm或更高,较佳大于约500sccm,例如约500sccm至约3000sccm,更佳约1000sccm至约2000sccm。硅前体、反应物或净化气体的脉冲持续时间各自独立为约0.05秒至约10秒,较佳约0.1秒至约1秒,例如约0.5秒。脉冲之后通常会有一段延迟时间,让脉冲的前体黏附于基板,并且在延迟时间之后,净化气体(如氮气或氩气)可持续流过或脉冲地流过该反应区。
用于形成共形氮化硅层的硅前体一般含有氮,例如氨基硅烷。可做为硅前体的具体氨基硅烷为具有化学式(RR’N)4-nSiHn的烷氨基硅烷,其中R、R’个别为氢基、甲基、乙基、丙基、丁基、戊基或芳基,且n=0、1、2或3。在一实施例中,R为氢基,R’为烷基(如甲基、乙基、丙基、丁基或戊基),例如R’为丁基(例如,叔丁基),且n=2。在另一实施例中,R、R’个别为烷基,例如甲基、乙基、丙基、丁基、戊基或芳基。可用于本文中所述沉积工艺的硅前体包括(tBu(H)N)3SiH、(tBu(H)N)2SiH2、(tBu(H)N)SiH3、(iPr(H)N)3SiH、(iPr(H)N)2SiH2、(iPr(H)N)SiH3、和其衍生物。较佳地,硅前体为双叔丁基氨基硅烷((tBu(H)N)2SiH2或BTBAS)。在其它实施例中,硅前体为具有化学式(RR’N)4-nSiR”的烷氨基硅烷,其中R、R’个别为氢基、甲基、乙基、丙基、丁基、戊基或芳基,R”个别为氢基、烷基(如甲基、乙基、丙基、丁基或戊基)、芳基或卤素(如F、Cl、Br或I),且n=0、1、2或3。
在单一晶圆处理腔室中使用BTBAS做为硅前体以形成共形含硅与氮层的工艺中,BTBAS与反应物的比值一般至少为约10,较佳介于约10至约100之间,例如介于约30至约50之间。用于批式处理腔室的比值可能较低。基板温度维持在约500℃至约800℃之间,腔室压力维持在约10毫托耳至约760托耳之间,例如约250托耳。在另一实施例中,硅前体和反应物相继脉冲输入至腔室中,以完成ALD工艺。
在一些实施例中,于预处理期间以出自UV源的能量束来曝照基板,并于沉积工艺期间使基板接触含氨基硅烷的沉积气体与能量束,有助于沉积含硅与氮的共形层。能量束可由准分子激光产生,例如氙(Xe)准分子激光。Xe准分子激光其中一范例为XERADEX20,其可购自位于美国麻萨诸塞州Danvers的Osram Sylvania。
预处理工艺中利用能量束曝照基板,以移除基板表面的原生氧化物。在沉积氮化硅材料之前,使用直接光激发系统产生的能量束预处理基板,以移除基板表面的原生氧化物。预处理时,使处理气体接触基板。处理气体包含氩气、氮气、氦气、氢气、组成气体(forming gas)、或其组合物。预处理工艺可持续进行约2分钟至约10分钟,以助于在光激发过程移除原生氧化物。又,光激发时,基板可加热至约100℃至约800℃之间的温度,较佳约200℃至约600℃,更佳约300℃至约500℃,以利于在工艺100中移除原生氧化物。能量束可为具约2电子伏特(eV)至约10eV的光子能的光子射束,且可产生波长约126nm至约351nm的UV辐射。
在一些实施例中,光激发过程提供能量输送气体。能量输送气体可为氖气、氩气、氪气、氙气、溴化氩、氯化氩、溴化氪、氯化氪、氟化氪、氟化氙(如XeF2)、氯化氙、溴化氙、氟、氯、溴或上述气体的准分子、自由基、衍生物或组合物。在一些实施例中,除了至少一种能量输送气体的外,处理气体还包含氮气(N2)、氢气(H2)、组成气体(如N2/H2或Ar/H2)。在其它实施例中,处理气体包含环状芳香性碳氢化合物。可用于预处理工艺的单环芳香性碳氢化合物和多环芳香性碳氢化合物包括醌(quinone)、羟基醌(氢醌)、葱(anthracene)、萘(naphthalene)、菲(phenanthracene)、其衍生物或其组合物。在另一实施例中,基板接触含其它碳氢化合物的处理气体,例如不饱和碳氢化合物,包括乙烯、乙炔、丙烯及其烷基衍生物、卤化衍生物或组合物。在又一实施例中,预处理期间,有机蒸气含有烷烃化合物。
可利用UV辅助化学气相沉积并在低温下以够快的沉积速度制造氮化硅材料的硅前体包括具有一或多个Si-N键或Si-Cl键的化合物,例如双叔丁基氨基硅烷(BTBAS或(tBu(H)N)2SiH2)或六氯二硅烷(HCD或Si2Cl6)。具有较佳键结构的硅前体化学式为:R2NSi(R’2)Si(R’2)NR2(氨基二硅烷)、(I)R3SiN3(迭氮硅烷,silylazides)或(II)R’3SiNRNR2(联氨基硅烷,silylhydrazines),(III)R和R’为一或多个官能基,其个别选自于由卤素、具一或多个双键的有机基团、具一或多个三键的有机基团、脂肪族烷基、环烷基、芳基、有机硅烷基、烷氨基、或含N或Si的环状基、或其组合物所组成的群组中。硅前体上适合的官能基例子包括氯基(-Cl)、甲基(-CH3)、乙基(-CH2CH3)、异丙基(-CH(CH3)2)、叔丁基(-C(CH3)3)、三甲基硅烷基(-Si(CH3)3)、吡咯烷基(pyrrolidine)、或其组合物。成信所述许多硅前体或氮前体可在低温下分解或解离,例如约550℃或更低。
其它适合UV激发沉积工艺的硅前体例子包括迭氮硅烷(R3SiN3)和联氨基硅烷(R3SiNRNR2)类型、具任何R基组合的直链与环状前体。R基可为H或任何有机官能基,例如甲基、乙基、丙基、丁基等(CxHy)。连接在Si上的R基或可为其它氨基(NH2或NR2)。使用硅-氮前体的好处在于可同时送入硅和氮且避免氯存在,故相较于传统Si-N前体,所生成的膜层具良好阶梯覆盖与最少图案相依性(所谓图案负载效应),又不会有形成不想要的氯化铵微粒的问题。迭氮硅烷化合物的具体范例包括三甲基迭氮硅烷((CH3)3SiN3;可购自位于美国宾州Bristol的United Chemical Technologies公司)和三(二甲胺)迭氮硅烷(((CH3)2N)3SiN3)。联氨基硅烷化合物的具体范例为1,1-二甲基-2-二甲基联氨基硅烷((CH3)2HSiNHN(CH3)2)。在另一实施例中,硅-氮前体为(R3Si)3N、(R3Si)2NN(SiR3)2和(R3Si)NN(SiR3)的至少其中一种,其中R个别为氢基或烷基(如甲基、乙基、丙基、丁基、苯基)、或其组合物。适合的硅-氮前体例子包括三硅胺((H3Si)3N)、(H3Si)2NN(SiH3)2、(H3Si)NN(SiH3)、或其衍生物。
共形层268(亦可称为共形膜)因其膜厚而缩减了开口266的宽度。因此可由期望缩减的宽度来决定共形层268的厚度。例如,开口266宽度为时,形成厚度的共形层可使凹部宽度缩减成此种在宽度上的缩减可制造出比目前微影工具所能制得结构更小的特征结构。
继续进行图2A的方法200,在步骤212中,移除一部分的共形层。共形层可利用蚀刻工艺移除,较佳是进行非等向性蚀刻,以免蚀刻掉位在宽度缩减凹部侧壁上的膜。非等向性蚀刻工艺的其中一范例为反应性离子蚀刻。蚀刻剂供给至处理腔室,处理腔室可为与形成共形层相同的腔室、或为不同腔室。施加RF功率来活化蚀刻剂,进而形成包含反应性离子的气体混合物。电偏压施加至基板,使反应性离子加速朝向基板表面。穿过该宽度缩减凹部的离子在转向侧壁之前将更深入凹部。大多数的离子将撞击凹部270的底部而蚀刻在凹部270底部处的共形层。未穿入凹部270的离子会撞击基板的场区而蚀刻掉在场区上的共形层268。第2F图绘示处于方法200的此阶段中的基板。
就共形层为氮化硅层、氮化硼层或氮化硼硅层的实施例而言,提供含卤素之前体至内含基板的处理腔室中可形成反应性离子。各种碳、硫和氮的卤化物可用来蚀刻这些材料。例子包括四氟化碳(CF4)、六氟化硫(SF6)、三氟化氮(NF3)和三氟甲烷(CHF3)。含氯类似物也可以较慢的速度蚀刻这些层。
在一实施例中,例如提供SF6的蚀刻剂至内含基板的处理腔室中。蚀刻剂供给流速为约20sccm至约1000sccm,例如约100sccm至约500sccm(如约300sccm)。还可提供非反应性载气,例如氦气、氩气、氖气或氙气。基板温度维持为约50℃至约500℃,例如约200℃至约400℃(如约300℃)。腔室压力维持约1毫托耳(mTorr)至约10托耳(Torr),例如约1托耳至约5托耳(如约2托耳)。可以13.56MHz的单一高频或约100kHz至约600kHz(如约400kHz)的单一低频提供约200W至约5000W的RF功率,或可以包括约400kHz的第一频率与约13.56MHz的第二频率的混合频率来提供约200W至约5000W的RF功率。RF功率可经电容或诱导耦合。经由施加功率介于约100W至约1000W之间(例如约500W)的电压至基板支撑件或气体分配板,可施加电偏压至基板。RF功率将SF6分子解离成氟离子(F-),电偏压促使离子加速朝向基板表面。离子加速往场区移动以及进入凹部。穿过凹部的离子通常行进到底部并且蚀刻位在凹部底部处的共形层。
在另一实施例中,利用非反应性离子来蚀刻凹部270的底部。经由施加电压偏压至基板,可将诸如氩气、氦气、氖气或氙气等惰性气体(noble gas)离子化成等离子体,并使之加速朝向基板表面。产生的高能离子接着撞击基板场区和宽度缩减凹部的底部,并因高能撞击而蚀刻掉基板上的共形层。
在步骤214中,利用已知工艺及使用宽度缩减凹部做为蚀刻罩幕来蚀刻底下的介电层258。图2G绘示处于方法200的此阶段中的基板。用来蚀刻介电层258的蚀刻化学剂会缓慢蚀刻或不蚀刻保留的共形层268。共形层268界定出蚀刻开口的宽度。此方法可形成比目前微影工具所能制得结构更小的开口,例如宽度小于50nm。在电偏压下结合反应性或非反应性离子的方向性蚀刻方法可用来蚀刻介电层258,同时不会影响所保留的共形层268。
在步骤216中,移除图案转移层260。可使用任何用来移除具有层260的组成的工艺来达成此步骤。在图案转移层260为含碳层(如无定形碳层)的实施例中,利用氧化作用来移除图案转移层260。较佳的氧化法是使用氧等离子体来攻击该层。此法的优点在于能快速移除碳层。然而,也可实行其它氧化法,例如热氧化法。
移除图案转移层260后,在步骤218中,移除任何残余的共形层268。图2H绘示处于方法200的本阶段中的基板。可使用任何用来移除具有共形层268的组成的工艺来移除共形层268。在共形层268为含硼与氮层的示范实施例中,可方便地使用水溶液来移除共形层268,水溶液可为氧化溶液,例如此技艺领域中已知的硫酸-双氧水混合物(sulfuric peroxide mixture,SPM)。此冲洗本质上并不会蚀刻氧化物介电质。含硅与氮层可由酸性溶液移除,例如氢氟酸或磷酸溶液。
本发明的实施例还提出于基板场区中形成CD缩减通孔的方法。图3A为根据本发明又一实施例的工艺流程图。图3B-3D为图3A方法的不同工艺阶段的基板示意图。在步骤302中,将通孔蚀入基板的一膜层内。此层可为介电层,例如氧化物层或氮化物层。可使用任何已知用来蚀刻基板的通孔的工艺来蚀刻该通孔,实际工艺视待蚀刻膜层的组成而定。图3B显示已经蚀刻的基板350。下层352上配置有介电层354,通孔356则蚀入介电层354内。
在步骤304中,形成共形层于基板上。利用类似上述图1A-2H的工艺,使共形层覆盖住场区、侧壁和通孔底部并且具有为约80%至约120%的阶梯覆盖。上述任一工艺皆可用来沉积共形层。在此实施例中,共形层的组成类似该被蚀刻的介电层的组成。图3A-3D实施例预期让部分共形层残留在完成组件中而做为组件的一部分。故在一些实施例中,共形层的介电常数通常近似介电层的介电常数。
图3C绘示具有共形层358形成其上的基板。共形层358缩减了通孔356的宽度而形成CD缩减通孔360。如图1A-2H所述,通孔356宽度缩减了两倍的共形层358厚度。
在一实施例中,共形层为氧化物层。氧化硅共形层可在使用或不使用等离子体的情况下利用CVD或ALD工艺形成于氧化物介电层上,例如低k的含碳介电层。介电层还可具多孔性。共形氧化物层具有相当小的介电常数和厚度,以维持部分组件结构,又不会不当影响组件的电性。在一些实施例中,共形层可具有更多或更少的氧与硅化学计量比。共形层的氧与硅比值范围为约1.8至约2.2。
在其它实施例中,共形层为含氮层。某些实施例中含有氮是有利的,因硅膜含氮可增强膜层的硬度及提供阻障性质。在一些实施例中,共形层为氮化硅层或氮氧化硅层。另外,在一些实施例中,共形层为完全氮化的氮化硅层、或其氮含量少于化学计量比。例如,用于方法300中的氮化硅共形层的氮与硅比值为约0.7至约1.5。
在步骤306中,移除部份的共形层306,而留下介电层354的露出场区、CD缩减通孔360的露出底部,并留下覆盖在CD缩减通孔360的侧壁上共形层358。利用非等向性蚀刻工艺并依据共形层组成调整,可移除共形层的预定部分。在共形层为氧化物层或氮化物层的实施例中,可如上所述般,在电偏压下施行上述氟离子方向性蚀刻来选择性蚀刻掉覆盖在基板350水平表面上的部分共形层。
本发明的实施例提出于基板场区中形成通孔的另一方法。图4A为根据本发明再一实施例的方法400的流程图。图4B-4G为图4A方法的不同工艺阶段的基板示意图。将具有待蚀刻层的基板放到处理腔室内。在步骤402中,将图案转移层涂覆至基板上表面。图4B绘示基板450具有底层452、蚀刻层454和图案转移层456。图案转移层可由任何对于用来蚀刻该层454的蚀刻化学剂具有抗蚀性的成分组成。如参照图2A-2H所述般,常用的图案转移层为利用PECVD和碳氢化合物前体形成的无定形碳。
在步骤404中,将实质相似于上述光阻的光阻涂覆在基板上,以及在步骤406中,图案化该光阻。图4C绘示处于方法400的本阶段的基板450。已图案化的光阻458覆盖图案转移层456,形成在光阻458中的通孔460则露出底下的图案转移层456。
在步骤408中,将图案转移到图案转移层中,如图4D所示,通孔460延伸入图案转移层456中。以无定形碳图案转移层为例,可利用上述任一工艺来转移图案,例如灰化或氧化蚀刻。
在步骤410中,如图4E所示,接着将图案转移到基板中。使用图案转移层456当作蚀刻罩幕,使通孔460延伸入蚀刻层454内。碳层已由上述工艺移除。
在步骤412中,以实质相似于上述方式来涂覆共形层于基板450上。图4F绘示已涂覆共形层462的基板450。共形层462缩减通孔460宽度而形成CD缩减通孔464。在此实施例中,共形层最好与蚀刻层454兼容,如此在进行间隙填充之前,不需先从通孔460中移除共形层。故共形层可为兼容介电质,例如氧化物或氮化物材料,且可以本文中所述方法沉积而得。
在步骤414中,利用方向性或非等向性蚀刻来移除部分共形层462。图4G绘示所产生的结构,其中在CD缩减通孔464底部处的共形层462已被移除,但仍留下侧壁上的共形层以维持缩减宽度。
在一些实施例中,图案转移层为金属层或金属氮化物层。金属层或金属氮化物层常做为需要极精确对准蚀刻特征结构的镶嵌整合工艺中的蚀刻罩幕。在此实施例中,可利用本文中所述包含氧化物或氮化物的共形层来缩减CD。金属硬罩幕经蚀刻而形成图案,如上所述,形成共形氧化物或氮化物层于其上,以及移除覆盖在图案凹部的底部处的部分,并且完成缩减CD的蚀刻工艺。接着在与移除硬罩幕层相同或不同的阶段中,移除共形层,随后进行间隙填充。
本发明的一些实施例提出图案化基板上的介电质的方法。图5A为根据本发明另一实施例的方法500的流程图。图5B-5H为在图5A方法的不同阶段时的基板示意图。在步骤502中,将待蚀刻的基板放到处理腔室内并且沉积内含图案的图案转移层至基板上。如上所述经由沉积光阻层、图案化及将图案转移到图案转移层,可达成此步骤。图5B绘示处于此工艺阶段中的基板550,其具有底层552、将被蚀刻的介电层554,以及其中形成有图案凹部558的图案转移层556。
在步骤504中,形成共形层于基板上。可以任何本文中所述方法来形成共形层,且其组成类似上述共形层。共形层形成的厚度可加以选择,用以缩减图案凹部558的宽度。图5C绘示基板550具有共形层560形成其上而产生第一CD缩减图案凹部562。
在步骤506中,移除位在CD缩减图案凹部的底部处的共形层。图5D绘示已移除在CD缩减图案凹部562底部处的共形层560后的基板550。如上所述,可使用任何非等向性手段移除共形层,例如在偏压下进行反应或非反应性离子蚀刻而露出底下的介电层554以供进行蚀刻之用。
在步骤508中,利用已知的蚀刻工艺将CD缩减图案转移到介电层中。图5E绘示CD缩减图案凹部562伸入介电层554内的基板。接着在步骤510中,如图5F所示,移除图案转移层556和共形层560,而留下已图案化的介电层554。形成在介电层554中的CD缩减图案凹部562可为细窄凹部。
在步骤512中,形成第二共形层于基板上,以进一步缩减CD。如上所述且如图5G所示,第二共形层564覆盖住介电层554的场区和CD缩减图案凹部562的侧壁与底部。CD因共形层的厚度而进一步缩减,而产生CD缩减通孔566。如上所述,在蚀刻后,用来缩减CD的共形层较佳是由与介电层554兼容的材料所组成,并可为具有低介电常数的氧化物或氮化物层。
在步骤514中,如图5H所示,移除在CD缩减通孔566底部处的第二共形层564。如图3A-3D所述,在完成的组件中,沉积在CD缩减通孔566侧壁上的第二共形层将在完成的装置中保留住部分的介电层554。由于第二共形层564与介电层554兼容,因此其具有大体上适合让组件适当运作的电性。因此,在蚀刻之前和之后均可涂覆共形层来缩减CD。
虽然本发明已以较佳实施例揭露如上,任何熟习此技艺者,在不脱离本发明的基本范围内,当可作出其它或进一步的实施例,因此本发明的保护范围当视权利要求书所界定者为准。
Claims (15)
1.一种缩减一凹部的关键尺寸的方法,该凹部形成在一具有一场区的基板中并且具有多个侧壁和一底部,该方法包含以下步骤:
涂覆一共形层至该场区、该些侧壁和该底部上;
利用一方向性蚀刻工艺移除在该底部处的该共形层而露出该基板;
蚀刻在该底部处露出的该基板;以及
利用一湿蚀刻工艺移除该共形层。
2.如权利要求1所述的方法,其中该共形层为一阻障层。
3.如权利要求1所述的方法,其中该凹部是经由图案化该基板的一图案转移层而形成。
4.如权利要求1所述的方法,其中该方向性蚀刻工艺还移除在该场区处的该共形层。
5.如权利要求1所述的方法,其中该共形层为氮化物层。
6.如权利要求1所述的方法,其中该共形层是以一等离子体增强化学气相沉积(PECVD)工艺沉积而得。
7.如权利要求1所述的方法,其中,该共形层包含一材料,该材料在接触到选择用来蚀刻该基板的蚀刻剂时具有低蚀刻速度。
8.如权利要求1所述的方法,其中利用一湿蚀刻工艺移除该共形层的步骤包含使该共形层接触一水溶液。
9.如权利要求1所述的方法,其中该方向性蚀刻工艺包含由一蚀刻气体形成一等离子体,以及施加一电偏压于该基板。
10.一种于一基板的一场区中形成一通孔的方法,该方法包含以下步骤:
将形成于该基板一表面上的一膜层图案化,以形成具多个侧壁和一底部的一凹部;
经由涂覆一共形膜至该膜层上而缩减该凹部的宽度;
移除该凹部的该底部处的该共形膜而露出一部分的该基板,以形成一关键尺寸缩减区域;以及
蚀刻该关键尺寸缩减区域而形成该通孔。
11.如权利要求10所述的方法,其中移除该共形膜的步骤包含使该共形膜暴露于一蚀刻气体的等离子体以及施加一电偏压于该基板。
12.如权利要求10所述的方法,其中移除该共形膜的步骤包含使该共形膜暴露于一水溶液。
13.一种图案化一基板上的一介电层的方法,该方法包含以下步骤:
形成一图案转移层至该介电层上;
涂覆一光阻、图案化该光阻以及将图案蚀刻入该图案转移层中而图案化该图案转移层,以形成具有一底部的一凹部;
沉积一第一共形层至该图案转移层上;
移除该凹部的该底部的该第一共形层而露出该介电层;
蚀刻该介电层的露出部分而形成一狭窄凹部;
移除该图案转移层和该第一共形层;
沉积一第二共形层至该基板上;以及
移除该狭窄凹部的底部的该第二共形层。
14.如权利要求13所述的方法,其中该第一共形层为一含氮层。
15.如权利要求14所述的方法,其中该第二共形层为一含氧层。
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- 2009-05-04 CN CN2009801183331A patent/CN102027572A/zh active Pending
- 2009-05-04 JP JP2011509554A patent/JP2011521452A/ja not_active Withdrawn
- 2009-05-04 KR KR1020107027525A patent/KR20110016916A/ko not_active Application Discontinuation
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CN107735851B (zh) * | 2015-06-03 | 2021-11-05 | 应用材料公司 | 在先进图案化工艺中用于间隔物沉积与选择性移除的设备与方法 |
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CN107761069A (zh) * | 2016-08-19 | 2018-03-06 | 弗劳恩霍夫应用研究促进协会 | 制造具有多孔结构的腔体的方法 |
US10854223B2 (en) | 2016-08-19 | 2020-12-01 | Fraunhofer-Gesellschaft Zur Foerderung Der Angewandten Forschung E.V. | Method of producing a magnetic structure |
US11268122B2 (en) | 2016-08-19 | 2022-03-08 | Fraunhofer-Gesellschaft zur Foerderung der anaewandten Forschunq e.V. | Method of producing a cavity having a porous structure |
CN108231549A (zh) * | 2016-12-15 | 2018-06-29 | 台湾积体电路制造股份有限公司 | 半导体制造方法 |
CN108231549B (zh) * | 2016-12-15 | 2021-10-26 | 台湾积体电路制造股份有限公司 | 半导体制造方法 |
Also Published As
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KR20110016916A (ko) | 2011-02-18 |
TW201007832A (en) | 2010-02-16 |
JP2011521452A (ja) | 2011-07-21 |
WO2009140094A3 (en) | 2010-01-28 |
WO2009140094A2 (en) | 2009-11-19 |
US20090286402A1 (en) | 2009-11-19 |
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