CN101976651A - 堆栈式半导体封装件的制造方法 - Google Patents

堆栈式半导体封装件的制造方法 Download PDF

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CN101976651A
CN101976651A CN2010102763860A CN201010276386A CN101976651A CN 101976651 A CN101976651 A CN 101976651A CN 2010102763860 A CN2010102763860 A CN 2010102763860A CN 201010276386 A CN201010276386 A CN 201010276386A CN 101976651 A CN101976651 A CN 101976651A
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those
manufacture method
coupling assembling
sealing structure
base unit
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CN101976651B (zh
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翁承谊
朱吉植
曾健源
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Abstract

此处说明一种堆栈式半导体封装件和其相关的堆栈式封装组件及方法。在一实施例中，制造方式包括：(1)提供一包括有数个接触垫的基底，接触垫邻接于基底的上表面；(2)施加一导电材料以形成分别邻接于接触垫的数个导电凸块；(3)电性连接一半导体组件至基底的上表面；(4)施加一封胶材料以形成覆盖此些导电凸块及半导体组件的封胶结构；(5)形成一组切口，切口部份地延伸贯穿封胶结构与此些导电凸块，以形成数个截头导电凸块；以及(6)回焊此些截头导电凸块以形成数个回焊导电凸块。

Description

堆栈式半导体封装件的制造方法
技术领域
本发明是有关于一种半导体封装件，且特别是有关于一种堆栈式半导体封装件。
背景技术
电子产品至少在某种程度上受到增进功能及缩小尺寸的驱使而日益地趋于复杂。当增进功能及缩小尺寸的优点显而易见时，达成这些优点的同时可能也会产生问题。尤其，电子产品一般都需要在有限的空间内容纳高密度的半导体组件。举例来说，于手机、个人数字助理、手提电脑、与其它可携式消费产品中，用以容纳处理器、存储装置、及其它主动或被动装置的空间可能相当地局限。半导体组件一般经由封装的方式提供保护使其免于环境条件的伤害，并且提供输入和输出的电性连接。封装半导体组件于半导体封装件中可能占用电子产品内的额外可用的空间。在此情况下，有很强的驱使力朝向减少被半导体封装件占用的脚位区域。关于此方面的其中一种实施方式将半导体封装件彼此堆栈，以形成一个堆栈式封装组件，又叫做迭层封装(Package-on-Package，PoP)。
图1绘示依照传统方式实施的堆栈式封装组件100。上封装件102设置于下封装件104之上，且两者以电性连接。上封装件102包括基底单元106及半导体组件108，半导体组件108设置在基底单元106的上表面118。上封装件102也包括覆盖半导体组件108的封装主体110。同样地，下封装件104包括基底单元112、半导体组件114、以及封装主体116，半导体组件114设置于基底单元112的上表面120上，封装主体116覆盖半导体组件114。请参照图1，封装主体116的侧向长度短于基底单元112的侧向长度，使得上表面120的外围部位维持暴露在外。焊锡球延伸于此外围部位和基底单元106的下表面122之间，焊锡球包括原本是上封装件102的一部分的焊锡球124a及124b，且焊锡球124a及124b于堆栈操作中回焊以电性连接上封装件102于下封装件104。如图1所示，下封装件104包括焊锡球126a、126b、126c、以及126d，焊锡球126a-126d自基底单元112的下表面128延伸，并提供组件100的输入及输出的电性连接。
当在给定的脚位区域完成高密度的半导体组件108及114时，组件100可能具有许多缺点。尤其，例如是焊锡球124a及124b的相对较大的焊锡球，横跨上封装件102及下封装件104之间的距离而占据了基底单元112的上表面120上的可用空间，因而阻碍了减少相邻的焊锡球之间距的可能，也妨碍了增加焊锡球的总数的可能。并且，在回焊的时候，焊锡球124a及124b可能无法充分贴附于下封装件104的基底单元112，使得制造组件100时可能会面临不合意的低堆栈良率。在形成封装主体116的封胶操作时，不充分贴附的情况可能恶化，因为封胶材料可能有溢出到上表面120的周围的倾向，并污染上表面120的周围。此外，由于封装主体116的侧向长度的减少，组件100可能有弯曲或变形的倾向，组件100的弯曲或变形可能在焊锡球124a及124b上产生充分的应力而导致连接失败。
在这样的技术背景下，发展可堆栈式半导体封装件和相关堆栈封装组件及方法的需求产生，且将叙述于此。
发明内容
本发明的一方面有关于一种制造方法。在一实施例中，制造方法包括：(1)提供一包括有上表面及接触垫的基底，接触垫邻接于基底的上表面；(2)施加一导电材料于基底的上表面，以形成分别邻接于接触垫的导电凸块；(3)电性连接一半导体组件至基底的上表面；(4)施加一封胶材料至基底的上表面，以形成覆盖导电凸块及半导体组件的封胶结构，封胶结构包括第一上表面，导电凸块的上端设置于封胶结构的第一上表面的下方；(5)形成一组切口，切口部份地延伸贯穿封胶结构与导电凸块，以形成截头导电凸块，封胶结构包括第二上表面，第二上表面设置于封胶结构的第一上表面下方，截头导电凸块上端实质上对齐封胶结构的第二上表面；以及(6)回焊截头导电凸块以形成回焊导电凸块，回焊导电凸块的上端突出于封胶结构的第二上表面。
在另一实施例中，一种制造方法包括：(1)提供一第一半导体封装件，其包括(a)一个包括上表面的基板单元，(b)第一连接组件由基底单元的上表面向上延伸，至少一个第一连接组件具有一高度HC(c)半导体组件邻接于基底单元的上表面，且电性连接至基底单元，以及(d)封装主体邻接于基底单元的上表面且覆盖半导体组件，封装主体邻近半导体组件处具有第一厚度HP1，且封装主体邻近于第一连接组件处具有第二厚度HP2，使得HP2＜HP1且HC＞HP2；(2)提供一第二半导体封装件，其包括下表面及第二连接组件，第二连接组件由第二半导体封装件的下表面向下延伸；(3)相对于第一半导体封装件设置第二半导体封装件，使得第二连接组件分别相邻于第一连接组件；及(4)合并各别成对的第一连接组件与第二连接组件以形成堆栈组件，堆栈组件电性连接第一半导体封装件及第二半导体封装件。
本发明的其它方面及实施例亦被考虑在内。前述的总括与后面详细描述，仅是描述依据本发明的部份实施例，并非用以限定本发明至任何特定的实施例。
附图说明
图1绘示依照传统方式实施的一堆栈式封装组件。
图2绘示根据本发明一实施例的堆栈式半导体封装件的透视图。
图3绘示沿着图2中线A-A的半导体封装件200的剖面图。
图4绘示图2的封装件的局部剖面放大图。
图5绘示依照本发明一实施例且利用图2的封装件所形成的堆栈式封装组件的剖面图。
图6A到6D绘示图5的组件的局部剖面放大图。
图7A到7H绘示依照本发明一实施例以形成图2的封装件及图5的组件的制造方法。
主要组件符号说明
100、500：堆栈式封装组件
106、112、504：基底单元
108、114、208、516：半导体组件
110、116、214、520：封装主体
118、120、204、506、522：上表面
122、128、206、508、704：下表面
200、502：封装件
210a、210b、210c、210d、210e、218a、218b、218c、218d、528a、528b、528c、528d：连接组件
220、222、242、244、510、512、524、526：侧表面
224：中心上表面
225：外围上表面
226a、226b、226c、226d：凹口
246a、246b、246c、246d、514a、514b、514c、514d：接触垫
400a、400b：开口
402：侧墙
518：导线
530a、530b、530c、530d：堆栈组件
600：上部
602：中部
604：下部
706：导电材料
710：封胶材料
712：封胶结构
716a、716b、716c、716d：导电凸块
718：切割工具
720a、720b、720c、720d：切口
724：助焊剂材料
726：锯刀
G：间隔
P’：堆栈组件间距
具体实施方式
以下的定义适用于依据本发明的部份实施例的部份方面。定义同样地于此作详细说明。
除非内文明确指明，否则于此所用的单数词“a”、“an”以及“the”包括数个指示对象。因此，举例来说，除非内文明确指明，否则当提及一半导体组件时，此一半导体组件可包含数个半导体组件。
于此所用的词语“set”表示一个或多个组件的集合。因此，举例来说，一层组可以包括单一层或多层。一组的组件(components of a set)也可以解释为此组的一部分(members of the set)。一组的组件可以是相同或不同的。在某些例子中，一组的组件可以共享一个或多个共同的特征。
于此所用的词语“adjacent”表示邻近或邻接。邻近的数个组件可彼此互相分开或者彼此实质上或直接互相接触。在某些例子中，邻近的数个组件可彼此互相连接或是一体成形。
于此所用的相对词语，例如是“inner”、“interior”、“outer”、“exterior”、“top”、“bottom”、“upper”、“upwardly”、“lower”、“downwardly”、“vertical”、“vertically”、“lateral”、“laterally”、“above”以及“below”表示一组的组件彼此相对于另一组的组件的方向，例如是如图式所示，但此些组件在制造过程中或使用中不需局限在特定方向。
于此所用的词语“connect”、“connected”、“connecting”及“connection”表示操作上的耦合或连结。数个连接组件之间可彼此互相直接耦合，或是彼此之间互相间接耦合，例如经由另一组的组件来达成彼此相互间接耦合。
于此所用的词语“substantially”以及“substantial”表示相当的程度或范围。当上述词语与一事件或情况合在一起使用时，此些词语可表示事件或情况精确地发生的实例，亦可表示事件或情况在接近的状况下发生的实例，例如是说明在此所描述的一般制造操作时的容忍程度。
于此所用的词语“substantially uniform”表示沿着设定的方向时，实质上不会改变。在某些例子中，沿着设定的方向时，特性可以被认为实质上相同，如果沿着设定的方向所量测的特征质，显现出一个就平均值而言，不大于约为20％的标准差，例如是不大于约10％或者是不大于约5％。
于此所用的词语“electrically conductive”以及“electrically conductivity”表示一电流传输的能力。导电材料通常是那些显现出极小或者没有反抗电流流通的材料。每公尺数个西门子(Siemens per meter，“S·m-1”)为导电性的一种度量单位。一般来说，一导电材料具有大于104S·m-1的传导性，例如是最少约为105S·m-1或者至少约为106S·m-1。一材料的导电性有时可随温度而变化。除非另有明确说明，一材料的导电性是于室温下所定义。
请先参照图2及图3，图2及图3绘示依据本发明一实施例的堆栈式半导体封装件200的示意图。尤其，图2绘示半导体封装件200的透视图，图3绘示沿着图2中线A-A的半导体封装件200的剖面图。
请参照图2及图3，封装件200包括一基底单元202，基底单元202包括上表面204、下表面206、及数个侧表面，此些侧表面包括侧表面242及244，侧表面242及244邻接于基底单元202的侧边，且延伸于上表面204及下表面206之间。在上述的实施例中，侧表面242及244实质上为平面且具有实质上相对于上表面204或下表面206的正交方向，然而侧表面242及244在不同的实施例中，可有不同的形状和方向。在特定实施例中，基底单元202的厚度，亦即基底202的上表面204及下表面206之间的垂直距离，可以在大约为0.1毫米(mm)至大约为2毫米(mm)的范围内，例如是在从约为0.2mm至约为1.5mm的范围内，或者是在从约为0.4mm至约为0.6mm的范围内。
基底单元202可以有许多种实施方式，且包括电连接件以提供介于基底单元202的上表面204及下表面206之间的电路径。如图3所示，基底单元202包括接触垫246a、246b、246c、及246d，以及接触垫248a、248b、248c、248d、以及248e，接触垫246a-246d邻接于上表面204的周围，接触垫248a-248e邻接于下表面206。在上述实施例中，接触垫246a、246b、246c、及246d以及接触垫248a、248b、248c、248d、及248e作为设置导电球时的导电球垫，然而此些接触垫的实施方式可和图3中所示的实施方式不同。接触垫246a、246b、246c、及246d以排成列的方式沿着基底单元202的侧边延伸分布，而接触垫248a、248b、248c、248d、及248e则是以数组的方式分布。然而，接触垫246a、246b、246c、及246d以及接触垫248a、248b、248c、248d、及248e可在其它实施例可有不同的分布方式。接触垫246a、246b、246c、及246d以及接触垫248a、248b、248c、248d、及248e连接至包括于基底单元202内的其它电连接件，例如是包括于一组介电层中的一组导电层。导电层可经由内部通孔彼此连接，以夹置利用适当的树脂所形成的核心，树脂例如是以双马来酰亚胺树脂(bismaleimide)与三氮六环(triazine)为基底，或者以环氧树脂(epoxy)与聚苯醚(polyphenylene oxide)为基底。举例来说，基底单元202可包括一实质上为板状的核心，核心被一组邻接于核心的上表面的导电层与另一组邻接于核心的下表面的导电层所包夹。虽然图3并未绘示，然而，一阻焊层可以邻接于基底单元202的上表面204及下表面206其中之一，或者上表面204及下表面206两者。
如图3所绘示，封装件200亦包括邻接于上表面204的周围的连接组件218a、218b、218c、及218d。连接组件218a、218b、218c、及218d分别电性连接至接触垫246a、246b、246c、及246d，且从相对应的接触垫246a、246b、246c、及246d向上延伸，且相对应地以排成列的方式沿着基底单元202的侧边延伸分布。进一步描述如下，连接组件218a、218b、218c、及218d提供在堆栈式封装组件内的封装件200与另一封装件之间的电路径。于上述的实施例中，连接组件218a、218b、218c、及218d用作导电球，尤其，连接组件218a、218b、218c、及218d根据后面说明的制造操作过程的经过截头且回焊以形成导电凸块的导电球。连接组件218a、218b、218c、以及218d由金属、金属合金、具有金属或金属合金散布于其中的材料、或者其它适当的导电材料所制成。如图3所绘示，各个连接组件218a、218b、218c、以及218d的尺寸可以依照连接组件218a、218b、218c、以及218d的高度HC及宽度WC具体定义。连接组件218a、218b、218c、以及218d的高度HC亦即连接组件218a、218b、218c、以及218d的最大垂直延伸，且连接组件218a、218b、218c、以及218d的宽度WC亦即连接组件218a、218b、218c、以及218d的最大侧向延伸。在特定的实施例中，各个连接组件218a、218b、218c、以及218d的高度HC在大约为50微米(μm)到大约为420μm的范围内，例如是在从大约为70μm至大约为370μm的范围内，或者在从大约为120μm到大约为320μm的范围内，且各个连接组件218a、218b、218c、以及218d的宽度WC在大约为100μm到大约为500μm的范围内，例如是在从大约为150μm至大约为450μm的范围内，或者在从200μm到大约为400μm的范围内。
请参考图3，封装件200亦包括半导体组件208及连接组件210a、210b、210c、210d、及210e。半导体组件208邻接于基底单元202的上表面204，且连接组件210a、210b、210c、210d、及210e邻接于基底单元202的下表面206。于上述实施例中，半导体组件208一个半导体芯片，例如是一处理器或者一存储装置。半导体组件208透过一组导线212以打线接合至基底单元202，导线212由金、铜、或其它适当的导电材料所制成。在特定实施例中，当考虑导线212以缩减的直径形成时，至少部份的导线212由铜形成，由于铜和金比较之下，铜有较好的导电性及较低的成本。导线212可以被镀上适当的金属，例如是钯，以作为抗氧化及对外在环境条件的保护层。半导体组件208亦可以用其它的方式电性连接至基底单元202，例如是经由覆晶接合的方式。举例来说。半导体组件208可以经由一组导电凸块，覆晶接合至基底单元202，导电凸块由焊锡、铜、镍、或其它适当的导电材料所制成。在特定实施例中，至少一部分的导体凸块可为多层凸块结构，包括邻接于半导体组件208的铜柱，邻接于基底单元202的焊锡层，以及设置于铜柱与焊锡层之间且可以抑制铜的扩散以及流失的镍阻障层。此多层凸块结构的特点描述于同时申请中且共同拥有的美国专利申请公开号第2006/0094224号内，此处将美国专利申请公开号第2006/0094224号的揭露内容以引用的方式完整地并入本案中。虽然图3中绘示单一个半导体组件208，然而，在其它实施例中，可包括其它的半导体组件，且此些半导体组件一般来说可以是任何主动组件、被动组件、或者结合两者的组件。举例来说，数个半导体组件可以堆栈的形式被包括在封装件200内，以在一给定的脚位区域容纳更高密度的半导体组件。
请再参照图3，连接组件210a、210b、210c、210d、及210e提供封装件200的输入及输出的电性连接，连接组件210a、210b、210c、210d、及210e从对应的接触垫248a、248b、248c、248d、及248e向下延伸，并且电性连接至对应的接触垫248a、248b、248c、248d、及248e。在上述实施例中，连接组件210a、210b、210c、210d、及210e作为导电球，且更进一步来说，根据后面描述的制造操作过程经回焊以形成导电凸块的导电球。连接组件210a、210b、210c、210d、及210e，由金属、金属合金、具有金属或金属合金散布于其中的材料、或者其它适当的导电材料所制成。至少部份的连接组件210a、210b、210c、210d、及210e透过基底单元202内所包括的电连接件来电性连接至半导体组件208，且至少相同或不同部份的连接组件210a、210b、210c、210d、及210e经由基底单元202内所包括的电连接件来电性连接至连接组件218a、218b、218c、及218d。
请参照图2及图3，封装件200亦包括邻接于基底单元202上表面204的封装主体214。封装主体214与基底单元202共同实质地覆盖或包覆半导体组件208与导线212，提供结构刚性以及防护其免于氧化、受潮、以及受到其它环境条件的破坏。封装主体214延伸至基底单元202的侧边，且沿着上表面204的周围部份覆盖或包覆连接组件218a、218b、218c、及218d，以提供改善的结构刚性并且降低弯曲或变形的可能。封装主体214的实施方式至少部份地露出连接组件218a、218b、218c、及218d，以堆栈其它封装件于封装件200的顶部上。
封装主体214由封胶材料所形成，且包括一中心上表面224，一外围上表面225，以及包括侧表面220及222的侧表面，侧表面220及222邻接于封装主体214的侧边。于上述实施例中，各中心上表面224以及外围上表面225实质上为平面且具有实质上相对于基底单元202上表面204或下表面206的平行方向，然而在不同的实施例中，中心上表面224及外围上表面225可为曲面、倾斜、阶梯状、或者约略的不平坦。请参照图2及图3，封装主体214具有一缩减厚度，此缩减厚度邻近封装主体214的侧边，以至少部份暴露出连接组件218a、218b、218c、及218d。尤其，封装主体214之中心厚度HP1，即介于封装主体214之中心上表面224及基底单元202的上表面204之间的垂直距离，大于封装主体214的外围厚度HP2，即介于封装主体214的外围上表面225及基底单元202的上表面204之间的垂直距离，外围厚度HP2实质上等于或小于各连接组件218a、218b、218c、或218d的高度HC。尤其，中心厚度HP1可以大于高度HC，外围厚度HP2不可大于大约2/3的中心厚度HP1，例如是从大约1/10到大约2/3的HP1，或者是从大约1/4到大约1/2的HP1，然而外围厚度HP2可以大于大约2/3的HP1，例如是从大约2/3到大约9/10的HP1。在特定的实施例中，封装主体214之中心厚度HP1在大约100μm到600μm的范围内，例如是在从大约150μm到550μm的范围内或是从大约200μm到大约500μm的范围内，且封装主体214的外围厚度HP2在大约50μm到400μm的范围内，例如是在从大约50μm到350μm的范围内或者在从大约100μm到300μm的范围内。
邻接于外围上表面225且由外围上表面225向下延伸处形成有凹口，包括凹口226a、226b、226c、及226d，凹口226a、226b、226c、及226d定义出连接组件218a、218b、218c、及218d分别对应的孔洞或者开口。开口至少部份暴露出连接组件218a、218b、218c、及218d，以于封装件200的上方堆栈另一个封装件。例如像连接组件218a、218b、218c、及218d，开口以排成列的方式分布，每一列沿着实质上的矩形图案或者实质上的正方形图案的四侧边延伸。虽然如图2及图3中绘示两列开口，然而，在其它实施例中，可有较多或较少列的开口，且一般来说，开口可以任何一维或二维的形式分布。
请参考图2及图3，封装主体214的侧表面220及222实质上为平面，且实质上相对于基底单元202上表面204或下表面206具有正交方向，然而，在其它实施例中，侧表面220及222可为曲面、倾斜、阶梯状，或者约略的不平坦。此外，侧表面220及222与相对应的基底单元202的侧表面242及244实质上对准或共平面，使得侧表面220及222与相对应的侧表面242及244结合的时候界定出封装件200的侧面。尤其，完成此对位后，封装主体214的侧向长度实质上相等于基底单元202的侧向长度(尽管邻接于封装件200侧边的厚度减少)，因而使得封装主体214可以提供上表面204一个更均匀的覆盖范围，并且提高结构的刚性。在其它实施例中，当提供足够的结构刚性并至少部份显露出连接组件218a、218b、218c、及218d时，侧表面220及222与其对齐的侧表面242及244的形状可与图2及图3不同。
接着请参照图4，图4绘示如图2及图3的封装件200的局部剖面放大图。尤其，图4绘示封装主体214与连接组件218a、218b、218c、及218d的特定实施方法，且为了更简化表达，其它某些关于封装件200的细节在此省略。
如图4所绘示，封装主体214形成以具有凹口226a及226b，凹口226a及226b定义出开口400a与400b，开口400a与400b的大小调整，以暴露出连接组件218a及218b的连接表面Sa与Sb。在上述实施例中，各开口400a或400b的尺寸可以用开口400a或400b的宽度与深度作更精确的定义。经由适当选择及控制开口400a与400b的形状与尺寸，连接组件218a及218b的形状与尺寸，或者结合这些特点，皆可以达到许多优点。尤其，经由暴露出连接表面Sa与Sb，连接组件218a及218b实际上可以提供预焊，以利在堆栈其它封装件于封装件200的上的时候，加强黏贴并湿润其它堆栈在封装件200上的封装件的连接组件。并且，连接表面Sa与Sb具有相对较大的面积，可以提高电连通的可靠度与效率，因而提高堆栈的良率。在堆栈的操作过程中，开口400a与400b可以避免或减少导电材料在堆栈的操作时溢出的情况，使得堆栈组件彼此间可以以较小的距离形成。
在上述实施例中，例如是开口400a或400b的开口呈圆锥状或圆漏斗状，且包括实质上圆形截面，实质上圆形截面沿着垂直方向有些许不同的宽度变化。尤其，例如是由凹口226a及226b所界定的开口的侧边界，朝向例如是连接组件218a或218b的相对应的连接组件轻微且渐进地变成锥状，并且接触连接组件以界定出未被覆盖的连接组件的上部与被覆盖的连接组件的下部之间的边界。然而，开口的形状一般来说可以是任何一种形状。例如，开口可以具有另一种锥状、非锥状、或者另外的规则或不规则状。另一种锥状可例如是椭圆锥状、方形锥状、或者矩形锥状，非锥状可例如是圆形柱状、椭圆柱状、方形柱状、或者矩形柱状。开口的侧边界，例如是由凹口226a及226b所界定，亦可为凸状的曲面，凹状的曲面，或者粗略地不平整。
在某些实施例中，开口400a或400b的个别宽度WO，即邻接于开口400a或400b的上端以及封装主体214的外围上表面225的侧向宽度，在大约100μm到520μm的范围内，例如是在从大约150μm到大约470μm的范围内，或者是在从大约200μm到大约420μm的范围内。如果开口400a或400b具有一个不一致的剖面形状，则宽度WO可以定义为例如是沿着正交方向的侧向宽度的平均值。另外，连接组件218a或218b的宽度WC，相当于邻接连接组件218a或218b的有被覆盖与未被覆盖部份的边界的横向宽度，而开口400a或400b的个别宽度WO实质上等于或大于对应的连接组件218a或218b的宽度WC，宽度WO与WC的比例相当于成锥状的程度，且可表示如下：WO＝aWC≥WC，其中a大约在大约1到大约1.3的范围内，例如是在从大约1.02到大约1.2的范围内或者是在从大约1.05到大约1.1的范围内。择一或结合起来说，WO的上限可表示为：P≥WO，其中P最相邻的连接组件的中心距离，最相邻的连接组件例如是连接组件218a及218b，此距离有时候也可以是连接组件间距。在某些实施例中，连接组件间距P在大约300μm到800μm的范围内，例如是在从大约350μm到650μm的范围内或者是在从大约400μm到600μm的范围内。经由以此方式来设定宽度WO的上限，开口400a及400b可以充分地界定出大小，且固定并设置一侧墙于连接组件218a及218b之间，及其它侧墙于其它连接组件之间。侧墙402可以当作阻碍物，用以避免或减少在堆栈操作的过程中导电材料的溢出的情况，使得堆栈组件彼此间以较短的距离形成。
请再参照图4，连接组件例如是连接组件218a及218b相对于封装主体214的外围厚度HP2调整大小，使得连接组件的上端突出于封装主体214的外围上表面225，即使得连接组件的高度HC大于封装主体214的外围厚度HP2。更进一步来说，高度HC与外围厚度HP2的差值可表示如下：HC-HP2＝DC，其中DC在大约5μm到120μm的范围内，例如是在从大约为10μm到大约为100μm的范围内或者是在从大约为20μm到大约为70μm范围内。在说明外围厚度HP2的典型公差程度时，连接组件突出于外围上表面225的部分的优点为可确保连接组件至少部份暴露出，以提高堆栈良率。然而，连接组件的上端亦可实质上与外围上表面225对齐或共平面，或凹入于外围上表面225的下方。如图4所示，各开口400a或400b具有一深度DO，深度DO对应于封装主体214的外围上表面225与各连接组件218a或218b的被覆盖部份及未被覆盖部份的边界间的垂直距离。在某些实施例中，各开口400a或400b的深度DO在大约为5μm到大约为120μm的范围内，例如是在从大约为10μm到大约为100μm的范围内，或者是在从大约为20μm到大约为70μm的范围内。择一或者结合起来说，深度DO相对于封装主体214的外围厚度HP2可表示为：HP2≥DO≥bHP2，其中b界定出深度DO的下限，举例来说，可以是大约为0.05、大约为0.1、或者大约为0.2。
图5绘示依照本发明一实施例的堆栈式封装组件500的剖面图。尤其，图5绘示利用图2到图4的封装件200所形成的特定的组件500。
如图5所绘示，组件500包括一半导体封装件502，组件500相当于一上封装件，且设置于相当于下封装件的封装件200的上方且电性连接至封装件200。在上述实施例中，封装件502为球闸式数组封装件(Ball Grid Array Package，BGAPackage)，然而，封装件200亦可为其它形式的封装件，包括平面闸格数组封装件(Land Grid Array Package，LGA Package)、四方扁平无接脚封装件(Quad FlatNo-lead Package，QFN Package)、导线架封装件(aQFN Package)、以及其它形式的球闸式数组封装件，例如是窗形球闸式数组封装件。虽然图5中绘示两个堆栈式封装件200与502，然而在其它实施例中可包括额外的封装件。封装件502的部份特点可以用近似于前面所叙述的封装件200的实施方式实施，在此不再赘述。
请参考图5，封装件502包括基底单元504，基底单元504包括上表面506与下表面508，以及包括侧表面510及512的侧表面，侧表面邻接于基底单元504的侧边，且延伸于上表面506与下表面508之间。基底单元504亦包括接触垫514a、514b、514c、以及514d，接触垫514a-d邻接于下表面508。在上述实施例中，接触垫514a、514b、514c、以及514d当作排成列的导电球垫，然而在其它实施例中接触垫514a、514b、514c、以及514d可有不同于图5的实施与设置方式。封装件502亦包括半导体组件516，半导体组件516邻接于基底单元504的上表面506的半导体芯片。在上述实施例中，半导体组件516透过一组导线518以打线接合至基底单元504，然而半导体组件516可以使用其它形式电性连接至基底单元504，例如是经由覆晶接合。虽然上述仅阐明单一个半导体组件516位于封装件502中，然而在其它实施例中可包括额外的半导体组件。
封装主体520邻接于基底单元504的上表面506，封装主体520实质上覆盖或包覆半导体组件516与导线518，以提供结构刚性与对抗外在环境的保护。封装主体520包括上表面522与包括侧表面524与526的侧表面，侧表面524与526邻接于封装主体520的侧边。在上述实施例中，侧表面524与526分别实质上与相对应的基底单元504的侧表面510及512对齐或共平面，使得侧表面510及512与侧表面524与526共同界定出封装件502的侧边。请参照图5，封装件502的侧向长度实质上相等于封装件200的侧向长度，然而在不同的实施例中，封装件502可有相对于封装件200较大或较小的侧向长。
请参照图5，封装件502亦包括连接组件528a、528b、528c、与528d，连接组件528a-d邻接于基底单元504的下表面508。连接组件528a、528b、528c、与528d提供封装件502输入及输出的电性连接，且电性连接至彼此相对应的接触垫514a、514b、514c、与514d，且由彼此相对应的接触垫514a-d向下延伸。在上述实施例中，连接组件528a、528b、528c、与528d用作导电球，且更进一步地来说，用作经由回焊以形成导电凸块的导电球。如同连接组件218a、218b、218c、与218d，连接组件528a、528b、528c、与528d以排成列的方式分布，各列沿着实质上矩形图案或实质上方形图案的四侧边延伸。
在封装的操作过程中，回焊封装件502的连接组件528a、528b、528c、及528d，且冶金接合连接组件528a、528b、528c、及528d与封装件200的连接组件218a、218b、218c、及218d。尤其，连接组件528a、528b、528c、及528d分别融合或结合对应的连接组件218a、218b、218c、及218d，以形成堆栈组件530a、530b、530c、与530d，以提供介于封装件200与502之间的电路径。如图5所绘示，各堆栈组件例如是堆栈组件530a，横跨封装件200及502之间的距离延伸，例如是相当于介在封装件200的接触垫246a及封装件502的接触垫514a两者之间的垂直距离。在封装件200与封装件502连接的时候，堆栈组件530a、530b、530c、与530d保持封装件200与502彼此之间的间隙为间隔G，间隔G亦即介在封装件502的下表面508与封装件200之中心上表面224之间的垂直距离。在某些实施例中，间隔G在大约为10μm到大约为110μm的范围内，例如是在从大约为10μm到大约为100μm的范围内，在从大约为20μm到大约为80μm的范围内，或者是在从大约为30μm到大约为70μm的范围内。适当地选择并控制连接组件528a、528b、528c、及528d的尺寸与连接组件218a、218b、218c、及218d的尺寸，使得间隔G有不同大小，并且在一些实施例中，间隔G可以缩减以利封装件502的下表面508接触于封装件200之中心上表面224。
如图5所绘示的封装件200与502的堆栈的可以达到许多优点。尤其，由于成对的连接组件，例如是连接组件218a与528a，横跨封装件200及502之间的距离延伸，因此，相较于传统中以单一且相对较大的焊球横跨距离的方式，本实施例的成对的各个连接组件可以缩减尺寸。并且，例如是堆栈组件530a的形成的堆栈组件的侧向长度可减少，且可以占据较小的可用的面积，因此减少相邻的堆栈组件之间的间距，并且增加堆栈组件的总数。在上述实施例中，相邻的堆栈组件间的距离可以具体表示为堆栈组件间距P’，堆栈组件间距P’为最相邻的连接组件的中心距离，最相邻的连接组件例如是连接组件530a及530b。在某些实施例中，堆栈组件间距P’实质上相等于连接组件间距P，连接组件间距P的定义如前述参照图4的部份所描述。经由适当地选择并控制连接组件528a、528b、528c、及528d的尺寸与连接组件218a、218b、218c、及218d的尺寸，可使得堆栈组件间距P’相较传统的实施方式缩减，并且，在一些实施例中，堆栈组件间距P’(以及连接组件间距P)在大约为300μm至大约为800μm的范围内，例如是在从大约为300μm至大约为500μm的范围内或者是在从大约为300μm至大约为400μm的范围内。
图6A到6D绘示如图5所绘示的组件500的局部剖面放大图。请参照图6A到6D，以更进一步地了解堆栈组件的一些特点。尤其，图6A到6D绘示开口400a与堆栈组件530a的特别实施例，且省略组件500的某些其它细节以简化表达。
如图6A到6D所绘示，堆栈组件530a为伸长结构，且更进一步来说，堆栈组件530a经由融合或结合连接组件218a及528a而形成的导电柱。在某些实施例中，堆栈组件530a呈哑铃状，且包括上部600及下部604，上部600及下部604较设置于上部600及下部604之间的中部602大。然而，一般来说，堆栈组件530a的形状可以为任何一种形状。上部600实质上对应于连接组件528a或实质上是由连接组件528a所形成，下部604实质上对应于连接组件218a或实质上是由连接组件218a所形成，中部602实质上对应于连接组件528a与218a的分界面或实质上是由连接组件528a与218a的分界面所形成。如图6A到6D所示，下部604的侧边界实质上被封装主体214所覆盖或包覆，且中部602及上部600的侧边界，实质上未被封装主体214所覆盖或包覆，以保持暴露在外的状态。然而，在不同的实施例中，上部600、中部602及下部604的被覆盖范围可不同。
请参照图6A到6D，堆栈组件530a的大小可以用其高度HS、上部600的宽度WSU、中部602的宽度WSM及下部604的宽度WSL明确表示，高度HS即堆栈组件530a的垂直高度，宽度WSU即上部600的最大侧向宽，WSL即下部604的最大侧向宽，WSM即中部602的最小侧向宽。可以理解的是，堆栈组件530a的高度HS实质上为封装主体214之中心厚度HP1及封装件200与502之间的间隔G的总和，相关的描述请参照前述图3至5的说明，且如图6A到6D所示，堆栈组件530a突出于封装主体214的外围上表面225之上，堆栈组件530a突出的范围为高度HS与封装主体214的外围厚度HP2的差值。并且，下部604的宽度WSL实质上相等于连接组件218a的宽度WC，宽度WC可参照前述图3及4的说明。此外，中部602的宽度WSM相等于堆栈组件530a的最小侧向宽，而宽度WSM相对于宽度WSU或宽度WSL的比例相等于中部602对应于上部600或下部604的向内形成锥状的范围。在某些实施例中，宽度WSM可表示为宽度WSU及WSL中较小的一者，如下：WSM≥c×min(WSU，WSL)，其中，c设为向内形成锥状的范围的下限，且小于或等于1。
经由适当地选择并控制开口400a及连接组件218a及528a的形状和大小、有关于截头和回焊的制造操作过程、或者这些特点或操作手段的结合，可以控制堆栈组件530a的形状和大小。尤其，调整上部600及下部604的相对大小可以达到更好的结果，即上部600的宽度WSU及下部604WSL的宽度的比例，例如是经由选择并控制连接组件218a及528a相对的大小。并且，调整中部602的向内形成锥状的范围可以达到更好的结果，例如是调整并控制关于截头和回焊的制造操作过程。尤其，因为过度向内形成的锥状可能造成裂缝，减少向内形成锥状的长度可以提升堆栈组件530a的结构刚性，因此提高封装件200及502之间的电性连接效率以及可靠度。
依照图6A的第一实施例，宽度WSU大于宽度WSL，例如是控制连接组件528a的大小大于连接组件218a的大小。更进一步来说，宽度WSU及宽度WSL的比例可以表示如下：WSU＝dWSL，其中d在大约为1.05到大约为1.7的范围内，例如是在从大约为1.1到大约为1.6的范围内，或者在从大约为1.2到大约为1.5的范围内。尤其，适当控制回焊操作可以控制向内形成锥状的范围。尤其，宽度WSM可以表示如下：WSM≥c×min(WSU，WSL)＝cWSL，其中c可以例如是大约为0.7、0.8或0.9。宽度WSL亦可以大于宽度WSU，例如是控制连接组件218a的大小大于连接组件528a的大小，且宽度WSL及宽度WSU的比例可以表示如下：WSL＝eWSU，其中e在大约为1.05到大约为1.7的范围内，例如是在从大约为1.1到大约为1.6的范围内，或者是在从大约为1.2到1.5的范围内。在宽度WSL大于宽度WSU的情况下，宽度WSM可以表示如下：WSM≥c×min(WSU，WSL)＝cWSU，其中c可以例如是大约为0.7、0.8或0.9。
请参照图6B的第二实施例，宽度WSU实质上相等于宽度WSL，例如是经由控制连接组件218a与528a大小相同。此外，适当控制回焊操作可以控制向内形成锥状的范围。尤其，宽度WSM可以表示如下：WSM≥c×min(WSU，WSL)＝cWSU＝cWSL。如同第一实施例，根据第二实施例的c可以例如是大约为0.7、0.8或0.9。
图6C绘示如图6A所绘示的第一实施例的变型。宽度WSU大于宽度WSL，例如是经由控制连接组件528a大于连接组件218a。然而，经比较发现，中部602的向内形成锥状的范围减少，且堆栈组件530a的侧边界从顶部向底部呈锥状逐渐狭窄。如图6C绘示，堆栈组件530a的侧边界定义出一个锥度α，其中α的范围于大约为1°到大约为45°的范围内，例如是从大约为2°到大约为30°的范围内，或者是从大约为5°到大约为20°的范围内。堆栈组件530a的侧边界亦可以由顶部向底部呈锥状逐渐变宽。
图6D绘示如图6B所绘示的第二实施例的变型。宽度WSU实质上相等于宽度WSL，例如是经由控制连接组件528a与218a大小相同。然而，经比较发现，中部602的向内形成锥状的范围减少，使得宽度WSM实质上相等于宽度WSU及WSL，且堆栈组件530a的侧边界实质上为正交方向，且侧边长从顶部到底部实质上均匀分布。如图6D中所绘示，堆栈组件530a的侧边长度存在有相对于平均值不大于约为20％的标准差，例如是不大于约为10％或者是不大于约为5％。
图7A到图7H绘示依照本发明一实施例的形成堆栈式半导体封装件及堆栈式封装组件的制造方法。为了简化表示方式，以下制造操作参照图2到图4的封装件200，以及参照图5到图6D的组件500作说明。然而，相似的制造操作过程可形成其它的堆栈式半导体封装件以及其它的堆栈式封装组件。
请先参照图7A，提供一基底700。为了提升制造的产量，基底700包括多个基底单元，包括基底单元202及与其相邻的基底单元202’，因而使得某些制造操作过程可以同步或相继地执行。基底700可以为长条状或数组形式。在为长条状的基底700中，多个基底单元相继排列成一维形式。在为数组形式的基底700中，多个基底单元排列成二维的数组的形式。为了简化表示方式，以下制造操作的过程主要基底单元202及其相关组件的说明，然而相似的制造操作过程可形成其它基底单元及相关的组件。
如图7A所绘示，多个接触垫邻接于基底700的上表面702，且多个接触垫邻接于基底700的下表面704。尤其，接触垫246a、246b、246c、及246d邻接于上表面702，接触垫248a、248b、248c、248d、及248e邻接于下表面704。在上述实施例中，导电凸块接着实质上分别邻接于对应的接触垫246a、246b、246c、及246d，以及接触垫248a、248b、248c、248d、及248e，接触垫提供导电凸块及包括在基底700中的电连接件的电性连接。接触垫246a、246b、246c、及246d以及接触垫248a、248b、248c、248d、及248e可以任何方式并沿着开口以金属、金属合金、具有金属或金属合金散布于其中的材料、或者其它适当的导电材料作电镀来形成，此些方式例如是光微影法、化学蚀刻法、激剥离或钻孔法、或是机械钻孔法以形成开口。虽然图7A并未绘示出，然而，在随后的操作中，可以使用胶带牢固基底700的下表面704。胶带可以为单面黏胶胶带或者是双面黏胶胶带。
一旦提供基底700，导电材料706施加于基底700的上表面702，并且导电材料706邻接于接触垫246a、246b、246c、及246d。导电材料706包括金属、金属合金、具有金属或金属合金分布于其中的材料、或者其它适当的导电材料。举例来说，导电材料706可以包括焊料，焊料可以为任何具有熔点于大约90℃到450℃的范围内的可熔融金属合金。此种可熔融金属合金的例子包括锡铅合金、铜锌合金、铜银合金、锡银铜合金、含铋的合金、含铟的合金，以及含锑的合金。在另一个例子中，导电材料706可以包括焊料核心，焊料核心由金属、金属合金、或者树脂所形成，其中焊料核心可以覆盖着焊料。进一步地举例来说，导电材料706可以包括导电黏胶，导电黏胶可以由任何具有填充导电填充物的树脂所形成。适当的树脂的例子可包括有环氧基树脂以及硅基树脂，且适当的填充物的例子可包括有银填充物与碳填充物。
在上述实施例中，分配器708相对于基底700侧向地设置，并且用来施加导电材料706。尤其，分配器708实质上对齐接触垫246a、246b、246c、及246d，因而使得导电材料706可以选择性地施加于接触垫246a、246b、246c、及246d。虽然图7A中绘示单一个分配器708，然而，为了更提高产率可使用多个分配器。请再参照图7A，分配器708一个配置球状体的工具，其可以将导电材料706以导电球的形式设置。各导电球具有实质上球体的形状或者实质上近似于球体的形状，然而，在其它的实施例中，导电球可有不同的形状。
当施加的导电材料回焊，例如是提高温度至接近或者高于导电材料706熔点的温度。由于重力或其它因素的影响，造成导电材料706会朝接触垫246a、246b、246c、及246d向下拖曳，如图7B所示，因而提升接触垫246a、246b、246c、及246d电性连接的可靠度及效率。当施加的导电材料充分地回焊时，导电材料706固化或变得坚硬，例如是降低温度至低于导电材料706熔点的温度。如此固化的操作以形成导电凸块716a、716b、716c、及716d，导电凸块716a-d实质上维持其原本球体或近似于球体的形状，且邻接于彼此相对应的接触垫246a、246b、246c、及246d。
接着，请参照图7C，半导体组件208邻接于基底700的上表面702，且电性连接至基底单元202。尤其，半导体组件208透过导线212以打线接合至基底单元202。在不同实施例中，导电凸块716a、716b、716c、及716d、以及半导体组件208邻接于基底700的操作顺序可不同。举例来说，半导体单元208邻接于基底700，且随后施加导电材料706于基底700，以形成导电凸块716a、716b、716c、以及716d。
请参照图7D，封胶材料710施加于基底700的上表面702，以实质上覆盖或包覆导电凸块716a、716b、716c、716d、半导体组件208、以及导线212。尤其，封胶材料710的施加实质上遍及上表面702的整体区域，因而提供改善的结构刚性，且避免或减少传统实施中溢出及污染的问题。并且，简化封胶操作以及减少此些封胶操作的次数可以减少制造的成本。封胶材料710包括例如是酚醛基树脂、环氧基树脂、硅基树脂、或其它适当的封胶材料。封胶材料710亦可包括适当的填充物，例如是二氧化硅的粉末。封胶材料710可以用任何封胶技术施加，例如是压缩成型、射出成型、以及转注成型。一旦施加封胶材料710时，封胶材料710例如是经由降低温度至低于封胶材料710熔点的温度而固化或变得坚硬，因而形成封胶结构712。为了以后操作时，使基底700更容易设置在适当的位置，基准标记可形成于封胶结构712内，例如是利用激作标记。择一或者结合起来说，基准标记可以形成于邻接基底700的外围。
接着，参照图7D以及图7E，经由减少厚度的操作，例如是激剥离、机械切割、挖槽、研磨、化学蚀刻、或者其它移除的技术，邻接于导电凸块716a、716b、716c、以及716d的封胶结构712的厚度从HP1减少到HP2，而邻接于半导体组件208以及导线212的封胶结构712的厚度实质上维持在HP1。如图7D以及图7E所绘示，减少厚度的操作一种利用切割工具718作部份切除的操作，以形成切口或沟槽，包括切口720a、720b、以及720c。尤其，切口向下延伸且部份地贯穿封胶结构712与导电凸块716a、716b、716c、以及716d。在上述实施例中，使用切割工具718而形成或暴露出的表面，例如是外围上表面225，相较于未被切割工具718处理过的表面，例如是中心上表面224，具有较大程度的表面粗糙度以及不平坦的纹路。在厚度减少的操作过程中，切割工具718可经由基准标记的辅助对准，使得切割工具718在形成切口的时候，可以设置在适当的位置。经由适当的封胶技术与移除技术的替换或结合，封胶结构712的厚度可有不同的变化。
由于减少厚度操作，包括开口400a及400b的开口形成于封胶结构712内并且各导电凸块的特定体积或重量百分比移除，例如是重量或体积百分比从大约为10％到大约为90％，从大约为30％到大约为70％，或者是从大约为40％到大约为60％。以此种方式来说，截头导电凸块722a、722b、722c、以及722d形成以具有实质上为平面的上端，且实质上与外围上表面225对齐或共平面。请再参照图7E，各截头导电凸块722a、722b、722c、以及722d实质上为半球体，虽然考虑到在不同实施例中，截头导电凸块722a、722b、722c、以及722d可能有不同的形状。
接着，请参照图7E及图7F，助焊剂材料724经由形成于封胶结构712内的开口施加于截头导电凸块722a、722b、722c、以及722d的上端。助焊剂材料724可以是任何促进冶金接合且改善导电材料706的流动与湿润特性的焊接剂。此些焊接剂的例子例如是包括氯化铵、氯化钾、硼酸钠、氯化钠、氟化钠、以及氯化锌。助焊剂材料724可以例如是利用网版印刷技术选择性施加于截头导电凸块722a、722b、722c、以及722d的上端。然而，助焊剂材料724亦可更普遍地施加于暴露出的表面，并且利用清洁操作去除多余的材料。
一旦施加助焊剂材料724后，回焊截头导电凸块722a、722b、722c、以及722d，例如是经由提高温度至接近或高于导电材料706的熔点的温度。由于内聚力与表面张力的影响使助焊剂材料724适度地调整，截头导电凸块722a、722b、722c、以及722d由原本半球体改变为实质上圆顶的形状。一旦截头导电凸块充分地回焊时，导电材料706固化或变得坚硬，例如是经由降低温度至低于导电材料706的熔点的温度。于是，连接组件218a、218b、218c、及218d形成为回焊导电凸块，回焊导电凸块的上端为弧形或圆形且突出于外围上表面225。如图7F所绘示的连接组件218a、218b、218c、及218d的形成方式可以达到许多优点。尤其，在堆栈操作过程中，制成的连接组件，例如是连接组件218a，的高度HC可以增加，以提升与另一封装件的连接组件的接触及冶金接合。同时，相较于设置单一且相对较大的导电球以达到增加HC的高度的实施方式，制成的连接组件的宽度WC可以控制且减少。于此方法中，制成的连接组件具有较小的侧边长且占据较少的可用面积，因此可以减少相邻的连接组件的距离并且增加连接组件的总数。虽然连接组件218a、218b、218c、及218d变成圆形的程度以及突出的程度在缺乏助焊剂材料724的时候会较为不明显，然而，在其它实施例中，施加助焊剂材料724的操作过程可以省略。
接着，如图7G所示，切割封胶结构712。此种切割方式可以被称为「前侧」切割。然而，对应于基底700下表面704的分离，可以被称为「后侧」分离。参照图7G，「前侧」切割用锯刀726执行，以形成包括切口728的切口或沟槽。尤其，切口向下延伸并完全贯穿基底700及封胶结构712，因而分割基底700及封胶结构712以形成包括基底单元202以及封装主体214的分离的单元。锯刀726在「前侧」切割可经由基准标记对准，以便使得锯刀726可以在适当的位置形成切口。
请再参照图7G，连接组件210a、210b、210c、210d及210e邻接于基底单元202的下表面206。在此种方式下，封装件200形成。连接组件210a、210b、210c、210d及210e可以经由例如是施加导电材料及回焊并且固化此材料以形成导电凸块。连接组件210a、210b、210c、210d及210e邻接于基底单元202的下表面206可以先于或后于「前侧」切割步骤。
接着进行关于封装件502的堆栈以形成组件500，如图5及图7H所绘示。尤其，封装件502相对于封装件200设置，以便使封装件502的连接组件528a、528b、528c、及528d实质上对准且邻近于相对应的封装件200的连接组件218a、218b、218c、及218d。一旦封装件200及502以此方式设置时，回焊并固化连接组件218a、218b、218c、及218d、以及连接组件528a、528b、528c、及528d，以执行冶金接合来形成堆栈组件530a、530b、530c、及530d。
综上所述，虽然本发明已以较佳实施例揭露如上，然其并非用以限定本发明。本发明所属技术领域中具有通常知识者，在不脱离本发明权利要求书所界定的精神和范围内，当可作各种的更动与润饰。此外，更多的修正可被拿来实施，用以适应本发明的特殊情况、材料、物质组成、方法、或工艺目标、精神及范围。所有此类的修正皆涵盖于后面所附的申请专利范围所界定的范围内。尤其是在此揭露的方法已经依照特殊操作描述出来，这些操作以特定的顺序执行，并且在不脱离本发明的教导下，得知此些操作可以合并、细分开的、或重新安排以形成相同的方法。因此，除非在此特别指出，操作的顺序或分类并不限制本发明。

Claims (20)

1.一种制造方法，包括：
提供一基底，该基底包括一上表面及数个邻接于该基底的该上表面的接触垫；
施加一导电材料至该基底的该上表面，以形成数个分别邻接于该些接触垫的导电凸块；
电性连接一半导体组件至该基底的该上表面；
施加一封胶材料至该基底的该上表面，以形成一封胶结构，该封胶结构覆盖该些导电凸块及该半导体组件，该封胶结构包括一第一上表面，且该些导电凸块的数个上端低于该封胶结构的该第一上表面；
形成一组切口，该组切口部份地延伸贯穿该封胶结构与该些导电凸块，以形成数个截头导电凸块，该封胶结构包括一第二上表面，该第二上表面低于该封胶结构的该第一上表面，该些截头导电凸块的数个上端实质上对齐该封胶结构的该第二上表面；及
回焊该些截头导电凸块，以形成数个回焊导电凸块，该些回焊导电凸块的数个上端突出于该封胶结构的该第二上表面。
2.如权利要求1所述的制造方法，其中该封胶结构具有一对应于该封胶结构的该第一上表面的第一厚度HP1，及一对应于该封胶结构的该第二上表面的第二厚度HP2，且HP2＜HP1。
3.如权利要求2所述的制造方法，其中HP2在HP1的1/10至2/3的范围内。
4.如权利要求3所述的制造方法，其中HP2在HP1的1/4至1/2的范围内。
5.如权利要求2所述的制造方法，其中至少一个该回焊导电凸块具有一高度HC，且HC＞HP2。
6.如权利要求5所述的制造方法，其中HC-HP2＝DC，且DC在5微米至120微米的范围内。
7.如权利要求6所述的制造方法，其中DC在10微米至100微米的范围内。
8.如权利要求1所述的制造方法，更包括施加一助焊剂材料至该些截头导电凸块的该些上端。
9.如权利要求8所述的制造方法，其中施加该助焊剂材料的该步骤在回焊该些截头导电凸块的该步骤之前执行。
10.如权利要求1所述的制造方法，其中该组切口相当于一第一组切口，且该制造方法更包括形成一第二组切口，该第二组切口延伸贯穿该封胶结构及该基底，以形成一第一半导体封装件。
11.如权利要求10所述的制造方法，更包括迭设一第二半导体封装件于该第一半导体封装件上，以形成一堆栈式封装组件。
12.一种制造方法，包括：
提供一第一半导体封装件，该第一半导体封装件包括一基底单元、数个第一连接组件、一半导体组件及一封装主体，该基底单元包括一上表面，该些第一连接组件从该基底单元的该上表面向上延伸，至少一个该第一连接组件具有一高度HC，该半导体组件邻接于该基底单元的该上表面，且电性连接至该基底单元，该封装主体邻接于该基底单元的该上表面并且覆盖该半导体组件，该封装主体邻近该半导体组件处具有一第一厚度HP1，且该封装主体邻近于该些第一连接组件处具有一第二厚度HP2，使得HP2＜HP1且HC＞HP2；
提供一第二半导体封装件，该第二半导体封装件包括一下表面及数个第二连接组件，该些第二连接组件由该第二半导体封装件的该下表面向下延伸；
相对该第一半导体封装件设置该第二半导体封装件，使得该些第二连接组件各自相邻于该些第一连接组件；及
融合各别成对的该些第一连接组件与该些第二连接组件，以形成数个堆栈组件，该些堆栈组件电性连接该第一半导体封装件及该第二半导体封装件。
13.如权利要求12所述的制造方法，其中HP2＜HC＜HP1。
14.如权利要求12所述的制造方法，其中该封装主体具有一对应HP1的第一上表面，及一对应HP2的第二上表面，该封装主体界定出数个开口，该些开口邻近地设置于该封装主体的该第二上表面，且该些缺口分别至少部份地暴露该些第一连接组件。
15.如权利要求14所述的制造方法，其中至少一个该第一连接组件具有一宽度Wc，且邻近于该封装主体的该第二上表面的该些缺口中的至少一者具有一宽度Wo，使得Wo≥Wc。
16.如权利要求15所述的制造方法，其中Wo＞Wc。
17.如权利要求12所述的制造方法，其中该些堆栈组件中的至少一个包括：
一低部，邻近设置于该基底单元的该上表面，且具有一宽度WSL；
一高部，邻近设置于该第二半导体封装件的该下表面，且具有一宽度WSU；及
一中部，设置于该高部与该低部之间，且具有一宽度WSM。
18.如权利要求17所述的制造方法，其中WSU≥WSL。
19.如权利要求17所述的制造方法，其中WSL＝eWSU，且e在1.05到1.7的范围内。
20.如权利要求17所述的制造方法，其中WSM≥0.7×min(WSU，WSL)。
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