SG11201610172WA - Package-on-package stacked microelectronic structures - Google Patents

Package-on-package stacked microelectronic structures

Info

Publication number
SG11201610172WA
SG11201610172WA SG11201610172WA SG11201610172WA SG11201610172WA SG 11201610172W A SG11201610172W A SG 11201610172WA SG 11201610172W A SG11201610172W A SG 11201610172WA SG 11201610172W A SG11201610172W A SG 11201610172WA SG 11201610172W A SG11201610172W A SG 11201610172WA
Authority
SG
Singapore
Prior art keywords
package
stacked microelectronic
microelectronic structures
structures
package stacked
Prior art date
Application number
SG11201610172WA
Inventor
Thorsten Meyer
Gerald Ofner
Original Assignee
Intel Ip Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Ip Corp filed Critical Intel Ip Corp
Publication of SG11201610172WA publication Critical patent/SG11201610172WA/en

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    • H01L2225/1058Bump or bump-like electrical connections, e.g. balls, pillars, posts
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    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
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    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
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    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L2924/153Connection portion
    • H01L2924/1532Connection portion the connection portion being formed on the die mounting surface of the substrate
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    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/11Printed elements for providing electric connections to or between printed circuits
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    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10431Details of mounted components
    • H05K2201/10507Involving several components
    • H05K2201/10515Stacked components

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  • Engineering & Computer Science (AREA)
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  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
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