CN100347832C - 电子器件材料的制造方法 - Google Patents

电子器件材料的制造方法 Download PDF

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CN100347832C
CN100347832C CNB028041542A CN02804154A CN100347832C CN 100347832 C CN100347832 C CN 100347832C CN B028041542 A CNB028041542 A CN B028041542A CN 02804154 A CN02804154 A CN 02804154A CN 100347832 C CN100347832 C CN 100347832C
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electronic device
film
manufacture method
device material
sio
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CN1489784A (zh
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菅原卓也
中西敏雄
尾﨑成则
松山征嗣
村川惠美
多田吉秀
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Tokyo Electron Ltd
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Tokyo Electron Ltd
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Abstract

一种具有优良电气特性的绝缘层或半导体层的高质量MOS型半导体等的电子器件材料的制造方法。包括在以单晶硅为主要成分的被处理基体上实施CVD处理形成绝缘膜的工序，以及将所述被处理基体暴露在通过具有多个缝隙的平面天线部件(SPA)对处理气体辐射微波而生成的等离子体中，并使用此等离子体将所述绝缘膜改性的工序。

Description

电子器件材料的制造方法
技术领域
本发明涉及适合半导体或电子器件材料的制造方法。本发明的电子器件材料的制造方法例如可以适合用于形成MOS型半导体结构。
背景技术
一直以来，在形成构成半导体或半导体材料的多个层时，使用各种层形成技术。作为这些层形成技术代表技术，例如可以举出真空蒸镀、喷镀、以及CVD(化学气相淀积)方法。在这些层形成技术中，因为CVD方法具有层形成的成膜速度快、可以在较短时间内成膜的特征，所以在制造以MOS型半导体器件为主的各种半导体或半导体器件材料时，多道工序都使用它。
本发明的制造方法一般可以广泛使用于电子器件材料的制造，但是在这里为说明方便，将以称作闪存存储器的非易失性存储器的一种形式的EPROM为例子，作为本发明的背景技术来进行说明。
EPROM具有如图12所示的多层结构。
参考图12，在p型单晶硅所构成的被处理基体100上，由SiO2构成的绝缘层101和用多晶硅构成的半导体层102及103形成规定图案并相互层叠的层，以及在其上淀积的金属(铝、铜等)所构成的金属层104构成此EPROM多层结构。
在这样的半导体器件中，为形成由多晶硅构成的半导体层102、103或层间的SiO2层，广泛使用上述CVD方法。
但是，使用CVD方法成膜的层表面粗糙、膜中缺陷比较多，有向膜中形成的称为悬挂键的原子结合的能力的倾向。此悬挂键若向膜中形成，会影响该层中以及邻接层的电子流动，使作为层的电气特性恶化，进而有可能产生使电子器件自身质量降低的问题。
发明内容
本发明的一个目的是提供一种能够解决上述现有技术中的问题的电子器件材料的制造方法。
本发明的另一个目的是提供改善构成电子器件(例如半导体)的层的电气特性、能够制造优质的电子器件的制造方法。
本发明的再一个目的是提供具有电气特性优良的绝缘层和半导体层的高质量电子器件材料(例如MOS型半导体)的制造方法。
本发明的电子器件材料制造方法包括：将至少包含电子器件用的衬底和在该衬底上配置的绝缘膜的被处理基体暴露在通过具有多个缝隙的平面天线部件的微波辐射处理气体而生成的等离子体中，对所述绝缘膜进行改性的工序。
根据本发明，还提供一种电子器件材料的制造方法，该方法包括将至少包含电子器件用的衬底、在该衬底上配置的第一SiO2膜、在该第一SiO2膜上配置的第一多晶硅层、以及在第一多晶硅层上配置的第二SiO2膜的被处理基体暴露在通过具有多个缝隙的平面天线部件的微波辐射处理气体而生成的等离子体中，将所述第二SiO2膜改性的工序。
根据本发明，还提供一种电子器件材料的制造方法，该方法包括将至少包含电子器件用的衬底和在该衬底上配置的绝缘膜的被处理基体暴露在通过具有多个缝隙的平面天线部件的微波辐射处理气体而生成的等离子体中、并使用此等离子体将所述绝缘膜改性的工序、以及在所述绝缘膜上形成金属层的工序。
附图说明
图1是用于实施本发明的电子器件制造方法的制造装置的略图(平面示意图)。
图2是表示可用于本发明的电子器件制造方法的缝隙平面天线(SlotPlain Antenna，以下简记为“SPA”)等离子体处理单元的一个例子的垂直剖面示意图。
图3是可用于本发明的电子器件制造装置中的SPA的平面示意图。
图4是可用于本发明的电子器件制造方法中的CVD处理单元的垂直剖面示意图。
图5是表示本发明的制造方法中的各工序的一个例子的流程图。
图6是表示涉及本发明的制造方法的闪存存储器的制造当中的状态的一个例子的垂直剖面示意图。
图7是表示涉及本发明的制造方法的闪存存储器的制造当中的状态的一个例子的垂直剖面示意图。
图8是表示涉及本发明的制造方法的闪存存储器的制造当中的状态的一个例子的垂直剖面示意图。
图9是比较各种处理条件以及在这些处理条件下得到的绝缘膜的质量特性的曲线图。
图10是表示涉及本发明的第二实施例的逻辑器件的制造工序的一个例子的流程图。
图11是表示涉及本发明的第二实施例的逻辑器件的制造工序的一个例子的垂直剖面示意图。
图12是典型的闪存存储器的垂直剖面示意图。
具体实施方式
下面根据需要参考附图详细说明本发明。如下所述中表示定量比的“部分”以及“％”只要不特别讲明，就为质量基准。
(电子器件材料的制造方法)
本发明的电子器件材料的制造方法至少包括，将至少包含电子器件用材料的层和在该层上配置的绝缘膜的被处理基体暴露在通过具有多个缝隙的平面天线部件的微波辐射处理气体而生成的等离子体中，将所述绝缘膜的改性的工序。
(电子器件用的材料)
不特别限制本发明中可使用的电子器件用的材料，可以从公知的电子器件用的材料的一种或者两种以上的组合来适当选择使用。作为这样的电子器件用的材料的例子，例如可以举出半导体材料、液晶器件材料等。作为半导体材料的例子，可以举出以硅为主要成分的材料(单晶硅、多晶硅，非晶硅等)、以氮化硅膜为主要成分的材料、以硅锗为主要成分的材料等。
(绝缘膜)
不特别限制在上述电子器件用材料的层上配置的绝缘膜，可以从公知的电子器件用的材料的一种或者两种以上的组合来适当选择使用。作为这样的绝缘膜的例子，例如可以举出氧化硅膜(SiO2)、氮化硅膜(SiN)等。作为氧化硅膜，从热过程、生产率方面出发，最好是通过CVD形成的膜。
(处理气体)
本发明中不特别限制可以使用的处理气体，可以从可用于电子器件制造的公知的处理气体的一种或者两种以上的组合来适当选择使用。作为这样的处理气体的例子，可以举出稀有气体和氧(O2)，或者包含稀有气体和氮(N2)和氢(H2)的混合气体。
(稀有气体)
本发明中不特别限制可以使用的稀有气体，可以从可用于电子器件制造的公知的稀有气体的一种或者两种以上的组合来适当选择使用。作为这样的处理气体的例子，例如可以举出氪(Kr)、氙(Xe)、氦(He)、或者氩(Ar)。
在本发明的绝缘膜的改性中，从应形成的改性膜的特性方面出发，可以适当使用下面的改性条件。
O2：1～1000sccm，更好是10～500sccm，
稀有气体(例如Kr、Ar、He或者Xe)：200～3000sccm，更好是500～2000sccm，
H2：1～200sccm，更好是1～50sccm，
温度：室温(25℃)～700℃，更好是室温～500℃，
压力：20～5000mTorr，更好是20～3000mTorr，最好是50～2000mTorr，
微波：0.5～5W/cm2，更好是1～4W/cm2。
(合适条件的例子)
在本发明的制造方法中，从应形成的改性的特性方面出发，可以举出下述各条件作为合适的例子。
处理气体合适的一例：含有流量10～500sccm的O2或者N2、以及流量500～2000sccm的Kr、He、Xe或者Ar的气体。
SiO2膜的处理条件合适的一例：室温～500℃的温度。
SiO2膜的处理条件合适的一例：2.7～270Pa(20～2000mTorr)。
SiO2膜的形成条件合适的一例：等离子体以1～4W/cm2的输出形成。
(改变多晶硅层上的SiO2膜特性的实施例)
本发明的另一个实施例的制造方法至少包括，将至少包含电子器件用的衬底、在该衬底上配置的第一SiO2膜、在该第一SiO2膜上配置的第一多晶硅层、以及在第一多晶硅层上配置的第二SiO2膜的被处理基体暴露在通过具有多个缝隙的平面天线部件的微波辐射处理气体而生成的等离子体中，将所述第二SiO2膜改性的工序。在将配置这样的多晶硅层上的SiO2膜进行改性的情况下，可以获得提高动作可靠性的优点。
例如，作为闪存存储器用的控制栅级，也可以在这样改性的所述第二SiO2膜上形成第二多晶硅层。第二SiO2膜也可以是其它的绝缘膜(SiN、或SiN和SiO2的层叠结构)。在这样改性的SiO2膜上形成第二多晶硅层的情况下，可以进一步获得提高动作可靠性的优点。
在用CVD形成上述第一多晶硅层、第二SiO2膜、以及/或第二多晶硅层的情况下，可以进一步获得降低热过程等的优点。从生产率这一点出发，最好用CVD形成全部这些第一多晶硅层、第二SiO2膜、以及第二多晶硅层。
在上述实施例的电子器件材料的制造方法中，还可以包括在形成上述第一多晶硅层的工序和在上述第一多晶硅层上形成第二SiO2膜的工序之间、以及/或在形成上述第二多晶硅层后，将所述被处理基体暴露在通过具有多个缝隙的平面天线部件对处理气体辐射微波而生成等离子体中，使用此等离子体将所述第一或者第二多晶硅层改性的工序。这样，通过另外追加包含暴露在通过平面天线部件的微波辐射处理气体而生成的等离子体中，可以预期使第一和第二多晶硅层的表面变平滑，提高第二SiO2膜的可靠性。此外，因为通过本工序提高第一和第二多晶硅的耐氧化性，就可以期望对后面的工序中多晶硅的面积变化的抑制。再者，在本工序中使用通过SPA生成的处理气体等离子体氧化多晶硅的表面，就可以形成第二SiO2。这一工序可以在低温下进行处理。在通常的热氧化工序中存在由于高温而使器件特性恶化的可能，但是通过使用本工序就可以一边抑制由热工序而使器件特性恶化(掺杂物扩散等)一边形成氧化膜。
(在改性绝缘层上形成金属层的实施例)
本发明的另外一个电子器件材料的制造方法至少包括，将至少包含电子器件用材料的层和在该层上配置的绝缘膜(例如栅极绝缘膜)的被处理基体暴露在通过具有多个缝隙的平面天线部件的微波辐射处理气体而生成的等离子体中，将所述绝缘膜改性的工序，以及在上述绝缘膜上形成金属层的工序。在这样改性的绝缘膜上形成金属层的情况下，可以获得提高动作可靠性和降低泄漏的优点。
(绝缘膜的材料)
在上述电子器件的制造方法中，作为前期绝缘膜(例如栅极绝缘膜)可以从现有技术使用的低介电常数的SiO2、SiON、SiN或高介电常数的Al2O3、ZrO2、HfO2、Ta2O5、以及ZrSiO、HfSiO等的硅酸盐和ZrAlO、HfAlO等的铝酸盐组成的组中选择的一种或者两种中举出。
(平面天线部件)
在本发明的电子器件材料的制造方法中，因为通过具有多个缝隙的平面天线部件的辐射微波来形成电子能级低且高密度的等离子体，并使用此等离子体进行膜的改性，因此可以得到等离子体损失小，而且在低温下进行反应性高的处理。
本发明所涉及的实施改性的膜，因为使用通过具有多个缝隙的平面天线部件的微波辐射而获得电子能级低且密度高的等离子体来改性，因此膜中的悬挂键以理想的形式封端。其结果，可以使膜自身的绝缘特性提高、进而得到特性优良的电子器件材料(例如半导体材料)。此外，因为可以使晶片温度、处理腔温度为低温，因此可以实现节能的处理。
(适合的等离子体)
在本发明中可以使用的合适的等离子体的特性如下：
电子能级：0.5～2.0eV，
密度：1010～5×1012cm-3，
等离子体密度的均匀性：±10％以内。
根据本发明，可以形成优质的改性绝缘膜。因而，通过在此改性绝缘膜上形成其它层(例如电极层)，就容易形成特性优良的半导体器件结构。
(绝缘膜的合适的特性)
根据本发明，可以容易地形成具有下述这样合适特性的改性绝缘膜。
漏电流降低：器件消耗电力低，
            应用于闪存存储器时有长寿命的存储保持能力，
可靠性的提高：抑制伴随操作次数增大的恶化。
(半导体结构的合适的特性)
不特别限制本发明的方法应适用的范围，但由本发明可形成的优质改性绝缘膜可特别适合用作闪存存储器结构的绝缘膜。
根据本发明可以容易地制造具有下述合适特性的闪存存储器结构。还有，在评价根据本发明改性的绝缘膜的特性时，例如，可以形成文献(IEEE TRANSACTIONS ON ELECTRON DEVICES，Vol46，No.9，SEPTEMBER 1999 PP1866-1871)中所记载的标准闪存存储器，通过评价其闪存存储器的特性来代替评价上述绝缘膜自身的特性。这是因为在这样的标准的闪存存储器结构中，构成该结构的绝缘膜的特性强烈影响闪存存储器特性。
特性：高反复动作稳定性。
(电子器件材料制造的实施例)
以下说明本发明的一个实施例。
首先，说明可以用于涉及本发明的闪存存储器的制造方法的电子器件材料的制造装置。
图1是表示为实施本发明的电子器件材料的制造方法的电子器件(半导体器件)制造装置30的整体结构的一个例子的概略图(平面示意图)。
如图1所示，在此半导体制造装置30的几乎中央处，设置用于运送晶片W(图2)的运送室31，在围绕此运送室31的周围，设置用于对晶片进行各种处理的等离子体处理单元32、CVD处理单元33、用于进行各处理室之间的连通/隔断操作的两台装载锁定单元34及35、用于进行各种加热操作的加热单元36、以及用于对晶片进行各种加热处理的加热反应炉47。还有，加热反应炉47也可以和上述半导体制造装置30分开独立设置。
在装载锁定单元34、35的旁边分别配置用于进行各种预热或者冷却操作的预热单元45、冷却单元46。
在运送室31的内部，设置搬运臂37以及38，可以在上述各单元32～36之间搬运晶片W(图2)。
装载锁定单元34和35的图中靠前一侧设置装料臂41和42。这些装料臂41和42可在更靠前一侧设置的晶片盒载物台43上的4台晶片盒44之间装入运出晶片W。
而且，这些等离子体处理单元32以及CVD处理单元33具有互换性，也可以互换等离子体处理单元32以及CVD处理单元33，和/或在等离子体处理单元32和CVD处理单元33的位置安装一台或者两台单室型CVD处理单元和等离子体处理单元。
(等离子体处理实施例)
图2是表示在本发明的处理中可以使用的等离子体处理单元32的垂直剖面示意图。
参考图2，参考标号50是例如用铝制成的真空容器。在此真空容器50的上面，形成比衬底(例如晶片W)大的开口部分51，设置有例如由石英或氧化铝等电介质构成的扁平的圆筒形状的顶板54，以便塞住此开口部分51。位于此顶板54的下面的真空容器50的上侧的侧壁上设置有在例如沿其周方向均匀配置的16个位置处的气体供给管72，从此气体供给管72把从包含O2或稀有气体、N2以及H2等中选择的一种以上的处理气体均匀地供给真空容器50的等离子体区域P附近。
在顶板54的外侧，设置和通过具有多个缝隙的平面天线部件、例如用铜板形成的缝隙平面天线(Slot Plane Antenna，SPA)60形成的高频电源部分、例如发生2.45GHz微波的微波电源部分61连接的波导路径63。此波导路径63由下缘连接SPA 60的扁平圆形波导管63A、一端和此圆形波导管63A上面连接的圆筒形波导管63B、连接此圆筒形波导管63B上面的同轴波导变换器63C、以及一侧垂直连接此同轴波导变换器63C的侧面的、另一侧连接微波电源部分61的矩形波导管63D组合构成。
这里，在本发明中包含UHF和微波，称为高频区域。即由高频电源部分供给的高频电包含300MHz以上的UHF和1GHz以上的微波，作为300MHz以上2500MHz以下，由这些高频电发生的等离子体称为高频等离子体。
在所述圆筒形波导管63B的内部，由导电材料制成的轴部62的一端与SPA 60的上表面的几近中央处连接、另一端同轴设置以使其与圆筒形波导管63B的上表面连接，由此该波导管63B就作为同轴波导管而构成。
此外，在真空容器50内，设置和顶板54相对的晶片W的安置台52。在此安置台52内装设图中未示出的温度调节部分，由此该安置台52作为加热板而发生作用。还有，真空容器50的底部连接排气管53的一端，此排气管53的另一端连接真空泵55。
(SPA的一个实施例)
图3是表示可用于本发明的电子器件材料制造装置的SPA 60的一个例子的平面示意图。
如图3所示，该SPA 60上，在表面形成多个同心圆状的缝隙60a、60a、…各缝隙60a是近似矩形贯通的槽，使相邻接的缝隙相互正交设置，形成近似字母“T”的文字。缝隙60a的长度或排列间隔对应微波电源部分61发生的微波的波长来决定。
(CVD处理单元的一个实施例)
图4是表示可用于本发明的电子器件材料的制造装置中使用的CVD处理单元33的一个例子的垂直剖面示意图。
如图4所示，CVD处理单元33的处理室82，例如用铝等形成可以密封的结构。处理室82内装备加热机构和冷却机构，但是在图4中省略。
如图4所示，处理室82中在上部中央处连接导入气体的气体导入管83，处理室82内和气体导入管83内连通。此外，气体导入管83连接气体供给源84。然后，从气体供给源84供给气体导入管83气体，通过气体导入管83将气体导入处理室82内。作为这种气体，既可以使用形成栅极的原料、例如硅烷等各种气体(电极形成气体)，也可以根据需要将惰性气体作为载流气体来使用。
在处理室82的下部，连接排放处理室82内气体的气体排气管85，气体排气管85连接由真空泵等构成的排气部件(图中未示出)。通过这一排气部件，从气体排气管85排放处理室82内的气体，将处理室82内设定为预期的压力。
此外，在处理室82的下部配置安置晶片W的安置台87。
在此图4所示的实施例中，使用图中未示出的和晶片W大约同样大小直径的静电卡盘把晶片W安放到安置台87上。此安置台87内设有图中未示出的热源部件，可以将在安置台87上放置的晶片W的处理面调节到预期温度。
安置台87根据需要可以为能使安置的晶片W转动的机构。
图4中，在安置台87的右侧的处理室82的壁面上设置为使晶片W出入的开口部分82a，此开口部分82a的开闭通过使门阀98在图中的上下方向上移动来进行。图4中，在门阀98的再右侧相邻设置运送晶片W的搬运臂(图中未示出)，搬运臂通过开口部分82a进出处理室82内在安置台87上放置晶片W，把处理后的晶片W从处理室82运出。
在安置台87的上方设置作为喷淋部件的喷头88。此喷头88例如用铝等制成，它将安置台87和气体导入管83之间的空间分开。
喷头88的形成，使气体导入管83的气体出口83a位于其上部中央处，通过在喷头88下部设置的气体供给孔89把气体导入处理室82内。
(电子器件材料的制造的实施例)
下面说明涉及本发明的电子器件材料的制造方法的一个实施例。
图4是关于本实施例的电子器件材料的制造方法的流程图，图6～图8是表示关于本实施例的闪存存储器单元的各制造工序的垂直剖面示意图。
在此实施例中，首先，如图5和图6B所示，由对作为被处理衬底的p型Si构成的晶片W有选择地离子注入和退火工序，形成作为n+层的埋入型数据线(杂质埋入层)22(步骤1)。
接着，如图6C所示，为形成第一绝缘层而加热晶片W或者CVD处理进行表面处理，在晶片W全部面上形成SiO2膜(第一SiO2膜)23(步骤2)。还有，可以在通过加热氧化形成SiO2膜23的情况下使用加热单元36和加热反应炉47(图1)，在通过CVD法形成SiO2膜23的情况下使用CVD处理单元33(图1)。
接着，如图6D所示，把在表面上形成第一SiO2膜23的晶片W装入CVD处理单元33的腔内，在处理气体例如硅烷气体存在下加热，在所述第一SiO2膜23的表面上形成多晶硅层(第一多晶硅层)24(步骤3)。
接着，对此第一多晶硅层通过例如光刻和干蚀刻的方法有选择地蚀刻形成图案(步骤4)，如图7A所示在上述SiO2膜23上形成浮动栅极(Floating Gate)25。
接着，再次把晶片W装入CVD处理单元33内(图1)，在晶片W的表面上实施CVD处理，如图7B所示，在露出来的所述浮动栅极25上形成第二SiO2层26作为第二绝缘层(步骤5)。
接着，把此晶片W装入等离子体处理单元32内(图1)，在这里对第二SiO2层26实施等离子体处理，将第二SiO2层26改性(步骤6)。
也就是，使搬运臂37、38进入CVD处理单元33内把在表面上形成SiO2层的晶片W取出，接着打开在等离子体处理单元32内的真空容器50的侧壁上设置的门阀(图中未示出)，由搬运臂37、38把上述晶片W放置在安置台52上。
接着在关闭门阀密封内部后，由真空泵55通过排气管53排出内部大气，抽真空到规定的真空度，维持规定的压力。一方面，由微波电源部分61发生例如1.80GHz(2200W)的微波，通过波导路径引导此微波，经过SPA 60和顶板54导入到真空容器50内，由此在真空容器50内的上侧的等离子体区域P中发生高频等离子体。
这里，微波以矩形波模传送到矩形波导管63D内，在同轴波导变换器63C内从矩形波模变换成圆形波模，以圆形波模在圆筒形同轴波导管63B传输，进而在径向方向上在平板形波导路径63A内传输，由SPA 60的缝隙60a辐射并透过顶板54导入到真空容器50内。此时因为使用微波而发生高密度、低电子能级的等离子体，此外因为从SPA 60的多个缝隙60a辐射微波，所以等离子体呈高均匀分布。
然后，调节安置台52的温度，加热晶片W例如到400℃，同时通过气体供给管72把作为形成氧化膜用的处理气体的氪或氩等稀有气体和O2气体以规定的流量导入，实施改性处理。
例如，可以在下面的条件下合适地进行此等离子体处理。即，作为处理气体，使用流量为5～50sccm的O2、以及流量为500～2000sccm的氪的混合气体、在300～700℃、2.7～135Pa(20～1000mTorr)的压力下、可以在等离子体源的输出为1～3W/cm2的条件下进行。
在此工序中，通过导入的处理气体在等离子体处理单元32内发生的等离子体流使之活性化(原子团化)，通过此等离子体将覆盖在晶片W最上面的SiO2膜26的进行改性。这样，进行上述改性处理例如40秒，使上述处理气体在等离子体在晶片W最上面的SiO2膜26的表面上发生作用来进行改性。此时发生的处理气体的等离子体电子能级低，随之处理气体的等离子体和SiO2膜26的偏压处于低值。因此，处理气体的等离子体接触SiO2膜26时带来的冲击小，所谓的处理气体的等离子体冲击SiO2膜26的表面时给SiO2膜26的等离子体损失小。因此SiO2膜26的表面以及膜中的悬挂键就合适地被封端，能得到SiO2膜26高质量的纹理细腻的状态。
接着，在这样用等离子体改性后，通过选择蚀刻(例如通过光刻以及干蚀刻的方法)等形成图案(步骤7)。
接着，把结束图案处理的晶片W装入CVD处理单元33内，在此CVD处理单元33内在处理气体例如硅烷气体的存在下加热晶片W，如图7D所示，在所述改性的SiO2膜26的全部表面上形成第二多晶硅层27(步骤8)。
接着，通过对此第二多晶硅层27选择性地使用蚀刻等方法形成图案(步骤9)，如图8A所示形成控制栅极28。
接着，如图8B所示，在控制栅极28上例如通过CVD形成第三绝缘层(SiO2膜)29(步骤10)。
接着，如图8C所示，对第三绝缘层进行图案形成处理，使数据线(n+层)22的一部分露出(步骤11)。
进而，如图8D所示，在绝缘层23、26、29和数据线22上蒸镀铝等金属，形成金属层31(步骤12)。进一步使此金属层形成图案(例如通过光刻以及选择性的蚀刻方法)形成电极(步骤13)。
以后，使用一般方法实施绝缘膜形成工序、钝化层形成工序、接触孔形成工序、以及配线形成工序等来完成单元制造工序(关于包括这样的绝缘膜形成工序、钝化层形成工序、接触孔形成工序、以及配线形成工序的单元制造工序，例如可以参考文献ULSI TECHNOLOGY McGRAW-HILLINTERNATIONAL EDITIONS C.Y.CHANG，S.M.SZE)。
在上述SiO2膜26的改性工序(步骤6)中，当对SiO2膜26进行改性时，在处理气体的气氛中，在以单晶硅作为主要成分的晶片W上，通过具有多个缝隙的平面天线部件(SPA)辐射微波形成包含氧(O2)以及稀有气体的等离子体，用此等离子体对所述SiO2膜26进行了改性，因此膜质量高，而且可以自始至终地进行膜质的控制。
上述改性后的氧化膜(SiO2膜26)的质量如图9的曲线所示，是很高的。
图9是表示使用涉及本实施例的电子器件材料的制造方法的改性工序(步骤6)在SiO2膜26的表面上通过SPA使等离子体作用并实施改性处理后的SiO2膜26的可靠性评价结果的曲线图。
此曲线图的纵轴取故障率的值，横轴取Qbd值(绝缘击穿电荷)。
在本测量中的器件结构使用下面1～7的方法形成。
1：衬底
衬底使用P型或者N型硅衬底，电阻率为1～30Ωcm，面取向(100)。在硅衬底表面上形成500A的牺牲氧化膜。
2：栅极氧化前的洗净
通过使用APM(氨、过氧化氢溶液、纯水的混合液)和HPM(盐酸、过氧化氢溶液、纯水的混合液)以及DHF(氟酸和纯水的混合液)组合的RCA洗净，去除牺牲氧化膜和污染因素(金属和有机物，微粒)。
3：SiO2膜的形成
通过CVD形成SiO2膜。在加热到780℃的上述衬底上分别以200sccm、400sccm流过SiH2Cl2和N2O，将压力保持60Pa进行30分钟的处理，形成60A的CVD氧化膜(高温氧化物：HTO)。
4：等离子体氧化处理
使用下述方法使形成3的SiO2膜的硅衬底改性。把形成3的SiO2膜的硅衬底在400℃加热，分别使1000sccm、20sccm的稀有气体和氧气流过晶片W，保持压力为13Pa～107Pa(100mTorr～900mTorr)。在此气氛中通过具有多个缝隙的平面天线部件(SPA)进行3W/cm2的微波辐射形成包含氧和稀有气体的等离子体，使用此等离子体对3的SiO2膜进行改性。
5：形成栅极用的多晶硅膜
在3、4中形成的SiO2膜上使用CVD方法形成作为栅电极的多晶硅的膜。将形成SiO2膜的硅衬底在630℃加热，通过在衬底上以33Pa的压力导入硅烷气体250sccm、保持30分钟，在SiO2膜上形成膜厚3000A的电极用的多晶硅的膜。
6：向多晶硅的P(磷)掺杂
将在5中制作的硅衬底加热到800℃，在常压下分别导入350sccm、200sccm、20000sccm的POCl3气体、氧和氮到衬底上，保持24分钟左右，在多晶硅中掺杂磷。
7：图案形成、栅极蚀刻
在6中制作的硅衬底上通过平板印刷进行图案形成，把硅衬底在HF∶HNO3∶H2O＝1∶60∶60的药液中浸泡3分钟，溶解未形成图案的部分的多晶硅，制作MOS电容器。
以下面所示的方法进行测定。对栅电极面积为10000μm2的电容器施加-0.1A/cm2的一定电流的应力，测量达到产生绝缘击穿的时间(BreakDown Time：Tbd)。绝缘击穿电荷(Qbd)是电流应力-0.1A/cm2和Tbd的积的绝对值。
此外，曲线①表示为参考起见根据现有技术的CVD法形成的SiO2膜(高温氧化物：HTO)的Qbd值，曲线②表示在O2和作为稀有气体的氪两者存在下使用SPA在压力100mTorr下对上述SiO2膜进行等离子体处理得到的Qbd值，曲线③表示在O2和氪存在下使用SPA在压力500mTorr下对上述SiO2膜进行等离子体处理得到的Qbd值，曲线④表示在O2和氪存在下使用SPA在压力900mTorr下同样对上述SiO2膜进行等离子体处理得到的Qbd值。
由如图9的曲线可知，比较使用现有技术的CVD方法形成的SiO2膜的Qbd值，使用本发明的制造方法而改性的SiO2膜的Qbd值高、可期望得到可靠性高且高质量的器件特性。
根据本发明的电子器件制造方法，可以改性形成具有比现有技术的CVD氧化膜高质量的、高Qbd值的氧化膜。
(高质量改性的绝缘膜的推断机理(mechanism))
这样，由上述方法改性的绝缘膜的质量高的理由，据本发明人所见，作如下推断。
即，通过使用SPA用微波辐射处理气体而形成的等离子体可以形成密度高且电子能级比较低的等离子体。因此，可以生成高密度的原子团，而且可以抑制等离子体和被处理基体表面的偏压到比较低的值，等离子体损失小。因此可以认为SiO2膜中的悬挂键被由等离子体发生的氧气反应核适度封端，弱的Si-Si结合变成牢固的Si-O-Si结合，从而被改性形成如图9所示的具有良好电气特性的SiO2膜。
实施例
下面通过实施例来更具体地说明本发明。
在以单晶硅为主要成分的被处理基体上形成10nm左右的第一SiO2膜，对所述被处理基体实施CVD处理，在所述第一SiO2膜上形成100nm～300nm左右的第一多晶硅层。其后，对所述被处理基体实施CVD及高温氧化加热处理，从而在所述第一多晶硅层上形成厚度为5～10nm左右的第二SiO2膜。
把形成的被处理基体放置在加热到400℃的安置台上，在氩1000sccm、氧气50sccm、全压力500mT的气氛中，将第二SiO2膜表面暴露在通过SPA的2W/cm2的微波辐射而生成的等离子体中2min左右。以这一工序，对进行过CVD、高温加热氧化处理后的第二SiO2膜改性，改善其特性。
还有，本发明不限定于上述实施例。例如，在上述实施例中，仅对在两个多晶硅层25和28之间的绝缘层(SiO2层)26使用通过SPA生成的处理气体等离子体进行表面处理，但是上述以外的绝缘层，例如SiO2层23、29的一个或者两个，也可以和上述同样使用通过SPA生成的处理气体等离子体进行表面处理。
此外，因为对两个多晶硅层25和28的表面使用通过SPA生成的处理气体等离子体进行表面改变特性处理，可以期望使两个多晶硅层的表面变得平滑，多晶硅层25和28之间的绝缘层26(用SiO2和SiN形成的层)的可靠性提高。此外，对于本工序的处理气体，通过使用稀有气体和氮气，可以期望提高25或者28的多晶硅的耐氧化性，抑制在后面的工序中的多晶硅的面积变动。
更有，通过对25的多晶硅表面使用由SPA生成的处理气体等离子体进行氧化，也可以形成26的SiO2。此工序可以在低温下进行处理。通常的热氧化工序中由于高温而使器件特性恶化的可能，但是使用本工序可以在抑制由于热工序使器件特性恶化(掺杂物扩散等)的同时形成氧化膜。
在这一情况下直到25～27工序，不暴露在大气中，而且可以在图1所示的半导体制造装置内自动连续处理，可以期望达到提高半导体性能的可靠性以及使制造工序简单化。
(第二实施例)
下面说明本发明的第二实施例。在此第二实施例中，在逻辑器件的制造工序中使用SPA等离子体处理对绝缘膜进行表面改性。
图10是表示本实施例的逻辑器件制造工序的流程图，图11是示意表示本实施例的逻辑器件的制造工序的垂直剖面示意图。
本实施例的逻辑器件的制造方法大体如下进行。元素分离→制作MOS晶体管→制造电容器→形成层间绝缘膜和配线。
下面举一般的例子说明作为包含SPA处理的MOS晶体管制作中的前期工序的MOS晶体管的制作。
1：衬底
衬底使用P型或者N型硅衬底，使用电阻率1～30Ωcm、面取向(100)的衬底。
在硅衬底上根据目的实施STI和LOCOS等的元素分离工序和沟道注入，在形成栅极氧化膜或栅极绝缘膜的硅衬底表面上形成牺牲氧化膜(图11A)。
2：在形成栅极氧化膜(栅极绝缘膜)前的洗净
一般通过使用APM(氨、过氧化氢溶液、纯水的混合液)和HPM(盐酸、过氧化氢溶液、纯水的混合液)以及DHF(氟酸和纯水的混合液)组合的RCA进行洗净，来去除牺牲氧化膜和污染因素(金属和有机物，微粒)。根据需要，有时也使用SPM(硫酸和过氧化氢溶液的混合液)、臭氧水、FPM(氟酸、过氧化氢溶液、纯水的混合液)、盐酸溶液(盐酸和纯水的混合液)、有机碱等。
3：形成栅极氧化膜(栅极绝缘膜)
对形成栅极绝缘膜，大致分为使用热氧化的处理和使用CVD的处理。这里主要叙述使用CVD形成栅极绝缘膜。使用CVD形成栅极绝缘膜时，把原料气体(例如SiH4和N2O)供给到从200℃到1000℃的范围内加热的所述硅衬底上，使由于热而形成的反应核(例如Si原子团和O原子团)在膜表面上反应来进行成膜(例如SiO2)。有时也用等离子体生成反应核。一般来讲，作为栅极氧化膜的膜厚，使用从1nm到10nm的膜厚(图11B)。
4：使用SPA等离子体的栅极绝缘膜改性处理
对在3中叙述由CVD形成的绝缘膜，通过在形成SPA等离子体的气体中以稀有气体和氧为主来实施氧化，进行CVD膜的改性。对于氧化得到的效果，目标是改变膜中的弱Si-Si结合为牢固的Si-O-Si结合，改善膜的特性。此外，通过在形成SPA等离子体的气体中包含稀有气体和氮的气体，也可以实施等离子体氮化处理。对于氮化得到的效果具有抑制由于高介电常数引起的薄膜化或来自栅电极的掺杂物的扩散作用。
5：形成栅电极用的多晶硅膜
由3、4形成的栅极绝缘膜(包含栅极氧化膜、栅极氮氧化膜)上通过CVD方法使作为MOS型晶体管的栅电极的多晶硅(包含非晶硅)形成膜。将形成栅极绝缘膜的硅衬底在从500℃到650℃的范围内加热，通过在衬底上在从10到100Pa的压力下导入含硅的气体(硅烷，乙硅烷)，在栅极绝缘膜上形成膜厚为50nm到500nm的电极用的多晶硅膜。有时，作为栅电极可以使用硅锗和金属(W、Ru、TiN、Ta、Mo等)代替多晶硅(图11C)。
其后，实行栅极的图案形成和选择蚀刻，形成MOS电容器(图11D)，通过离子蚀刻形成源极、漏极(图11E)。接着经过组合成为后续工序的层间绝缘膜的成膜、形成图案、选择蚀刻、形成金属膜的配线工序，得到关于本实施例的逻辑器件(图11F)。
再者，在本实施例中形成作为绝缘膜的氧化膜(SiO2膜)，但是也可以形成由这些组成以外而形成绝缘膜。作为栅极绝缘膜，可以举出从现有技术使用的低介电常数的SiO2、SiON、SiN或高介电常数的Al2O3、ZrO2、HfO2、Ta2O5、以及ZrSiO、HfSiO等的硅酸盐和ZrAlO、HfAlO等的铝酸盐组成的组中选择的1种或两种以上的物质。
在本实施例中，在封端膜表面或者膜中的使用通过SPA生成的低温高密度等离子体供给的活性原子的效果外，通过从包含稀有气体和氮的气体构成的等离子体所供给的氮气反应核植入表面层，可以期望起到作为抑制来自多晶硅的掺杂物扩散的壁垒这样的效果。
根据上述的本发明，对于在电子器件用的衬底上配置的绝缘膜，通过具有多个缝隙的平面天线部件(SPA)来辐射微波，通过使用所谓的SPA天线的方法在硅衬底上直接供给等离子体，可对绝缘膜(例如SiO2膜)进行改性处理。因此，可以使绝缘膜自身不受损伤、在绝缘膜表面或者膜中以适当形态封端悬挂键，可以得到高质量的绝缘膜，进而得到高质量的电子器件(例如半导体器件)。

Claims (22)

1.一种电子器件材料的制造方法，包括，
将至少包含电子器件用的衬底和在该衬底上配置的绝缘膜的被处理基体暴露在通过平面天线部件对处理气体辐射微波而生成的等离子体中，将所述绝缘膜改性的工序，其中在所述平面天线部件上呈同心圆状贯穿形成多个缝隙。
2.如权利要求1所述电子器件材料的制造方法，其中，
所述电子器件用的衬底是半导体材料或液晶器件材料。
3.如权利要求1或者2所述电子器件材料的制造方法，其中，
所述电子器件用的衬底是将以单晶硅、多晶硅、非晶硅为主要成分的材料、以氮化硅为主要成分的材料、或硅锗作为主要成分的衬底。
4.如权利要求1所述电子器件材料的制造方法，其中，
所述绝缘膜是使用CVD形成的绝缘膜。
5.如权利要求1所述电子器件材料的制造方法，其中，
所述绝缘膜是从SiO2、氮氧化硅膜SiON、氮化硅SiN、氧化铝Al2O3、氧化锆ZrO2、氧化铪HfO2、硅酸盐、铝酸盐组成的组中选择一种或者两种以上。
6.如权利要求5所述电子器件材料的制造方法，其中，
所述硅酸盐是具有ZrSiO或HfSiO组成的硅酸盐，以及/或所述铝酸盐是具有ZrA1O或HfA1O组成的铝酸盐。
7.如权利要求1所述电子器件材料的制造方法，其中，
所述处理气体包含稀有气体和氧气，或者包括稀有气体和氮气。
8.如权利要求1所述电子器件材料的制造方法，其中，
所述处理气体包括稀有气体、氮气和氢气，或者包括稀有气体和氧气和氢气。
9.如权利要求7或8所述电子器件材料的制造方法，其中，
所述稀有气体是氪、氙、氩或者氦。
10.如权利要求9所述电子器件材料的制造方法，其中，
所述处理气体是包含流量为1～1000sccm的O2；流量为200～3000sccm的氪、氦、氙或者氩；以及流量为1～200sccm的氢的气体。
11.如权利要求1所述电子器件材料的制造方法，其中，
所述绝缘膜的改性在室温至700℃的温度下进行。
12.如权利要求1所述电子器件材料的制造方法，其中，
所述绝缘膜的改性在20～5000mTorr的压力下进行。
13.如权利要求1所述电子器件材料的制造方法，其中，
所述等离子体以0.5～5W/cm2的输出而形成。
14.如权利要求1所述电子器件材料的制造方法，还包括在上述改性了的绝缘膜上形成金属层的工序。
15.一种电子器件材料的制造方法，包括，
将至少包含电子器件用的衬底、在该衬底上配置的第一SiO2膜、在该第一SiO2膜上配置的第一多晶硅层、以及第一多晶硅层上配置的第二SiO2膜的被处理基体暴露在通过平面天线部件对处理气体辐射微波而生成的等离子体中，将所述第二SiO2膜改性的工序，其中在所述平面天线部件上呈同心圆状贯穿形成多个缝隙。
16.如权利要求15所述电子器件材料的制造方法，其中，
在所述第二SiO2膜上形成第二多晶硅层，并形成控制栅极。
17.如权利要求15或者16所述电子器件材料的制造方法，其中，
所述第一多晶硅层以及/或第二SiO2膜是使用CVD形成的。
18.如权利要求16所述电子器件材料的制造方法，其中，
所述第二多晶硅层是使用CVD形成的。
19.如权利要求15所述电子器件材料的制造方法，其中，
所述第一多晶硅层上的第二SiO2膜是使用CVD形成的。
20.如权利要求15所述电子器件材料的制造方法，其中，
所述电子器件用的衬底是半导体材料或液晶器件材料。
21如权利要求15或20所述电子器件材料的制造方法，其中，
所述电子器件用的衬底是将以单晶硅、多晶硅、非晶硅为主要成分的材料、以氮化硅为主要成分的材料、或硅锗作为主要成分的衬底。
22.如权利要求16所述电子器件材料的制造方法，其中，
在形成所述第一多晶硅层的工序和在所述第一多晶硅层上形成第二SiO2膜的工序之间，以及/或，在形成所述第二多晶硅层之后，还包含将所述被处理基体暴露在通过所述平面天线部件对处理气体辐射微波而生成的等离子体中，并使用此等离子体将所述第一或者第二多晶硅层改性的工序。
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