CN1967780B - 用于制作场效应晶体管的栅极电介质的方法 - Google Patents

用于制作场效应晶体管的栅极电介质的方法 Download PDF

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CN1967780B
CN1967780B CN2006101528528A CN200610152852A CN1967780B CN 1967780 B CN1967780 B CN 1967780B CN 2006101528528 A CN2006101528528 A CN 2006101528528A CN 200610152852 A CN200610152852 A CN 200610152852A CN 1967780 B CN1967780 B CN 1967780B
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reactor
gate dielectric
dielectric layer
oxide
silicon substrate
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CN1967780A (zh
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蔡太程
考利·萨尼克
克里斯多佛·肖恩·奥尔森
卡勒德·Z·艾哈迈德
菲利普·艾伦·克劳兹
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Applied Materials Inc
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Abstract

这里公开了一种用于制作场效应晶体管的栅极电介质的方法。在一个实施例中，该方法包括以下步骤：去除天然氧化物层，形成氧化物层，在氧化物层上形成栅极电介质层，氧化栅极电介质层，以及对各层和下方的热氧化物/硅界面退火。可选地，可以在形成栅极电介质层之前对氧化物层进行氮化。可选地，可以在氧化栅极电介质层之前对栅极电介质层进行氮化。在一个实施例中，该方法的至少一部分是利用安排在组合工具上的处理反应器执行的。

Description

用于制作场效应晶体管的栅极电介质的方法
技术领域
本发明的实施例一般地涉及用于在半导体衬底上制作器件的方法。更具体而言，本发明涉及用于制作场效应晶体管(具体而言是场效应晶体管的栅极电介质的方法。
背景技术
集成电路可以包括多于一百万个微电子场效应晶体管(例如，互补金属氧化物半导体(CMOS)场效应晶体管)，这些场效应晶体管形成在衬底上，并且在电路内协同工作以执行各种功能。CMOS晶体管包括沉积在沟道区上的栅极结构，沟道区形成在晶体管的源极区和漏极区之间。栅极结构一般包括栅极电极和栅极电介质。栅极电极沉积在栅极电介质上，并且两者协同地用来控制栅极电介质下方的沟道区中电荷载流子的流动(即电流)。
栅极电介质一般由氮化硅(Si3N4)或氮氧化硅(SiON)形成。为了提高晶体管的速度，在先进集成电路中栅极电介质的厚度在约20-30埃或更小的范围内选择。然而，具有这种超薄栅极电介质的栅极结构的制作是一项富有挑战性的任务。一个具体问题是当前的制造技术引起了通过栅极电介质的高漏电流，并且由于大量的氮(N2)扩散到晶体管的硅/栅极电介质界面中而降低了沟道区中电荷载流子的迁移率。
因此，在本领域中需要一种用于制作场效应晶体管的栅极电介质的改进方法。
发明内容
本发明一般地涉及用于制作场效应晶体管的栅极电介质的方法。本发明可用在集成电路器件(如微处理器、专用集成电路(ASIC)、电子存储器件等)中。
在一个实施例中，该方法包括以下步骤：从硅衬底去除天然氧化物层，在衬底上形成氧化物层，在氧化物层上形成栅极电介质层(例如，氮化硅(Si3N4)、氧化铪(HfO2)、硅氧化铪(如HfXSiYO，其中x和y是整数)等)，氧化栅极电介质层，以及对所形成的各层和热氧化物层和衬底之间的界面退火。可选地，可以在形成栅极电介质层之前对氧化物层进行氮化。可选地，可以在氧化栅极电介质层之前对栅极电介质层进行氮化。在一个实施例中，该方法的至少一部分步骤可以利用集成半导体衬底处理系统(即，组合工具)的处理反应器执行。
在另一个实施例中，一种用于在衬底上制作场效应晶体管的栅极电介质的方法包括以下步骤：从衬底去除天然氧化物层，并将衬底置于氮气净化的或真空环境中；在硅衬底上形成热氧化物层；在热氧化物层上形成栅极电介质层；利用含氧等离子体氧化栅极电介质层的至少一部分；以及对具有热氧化物层和形成在其上的经氧化的栅极电介质层的衬底进行退火。
在本发明的另一个方面，公开了一种用于制作场效应晶体管的栅极电介质的集成半导体衬底处理系统。在一个实施例中，该系统包括被配置用于在硅衬底上形成热氧化物层的至少一个第一反应器；被配置用于在热氧化物层上沉积栅极电介质层的至少一个第二反应器；被配置用于氧化栅极电介质层的至少一个第三反应器；至少一个装载室；耦合到反应器中的每一个和装载室的至少一个衬底转移室；以及管理并监视处理系统的操作的控制器。
附图说明
通过结合附图考虑下面的详细描述，将清楚了解本发明的教导，在附图中：
图1示出了图示根据本发明的一个实施例的用于制作场效应晶体管的栅极电介质的方法的流程图；
图2A-2E共同示出了其中根据图1的方法制作了栅极结构的衬底的一系列示意性横截面示图；以及
图3示出了可用于实现本发明的部分步骤的一类示例性的集成半导体衬底处理系统的示意图。
在可能的情况下，相同的标号在这里用于指代所有图中相同的元件。附图中的图被简化以用于说明目的，并且不是按比例绘出的。
附图图示了本发明的示例性实施例，因此不应当被认为是限制本发明的范围，本发明的范围可包括其他等效实施例。
具体实施方式
本发明是一种用于制作具有超薄栅极电介质(例如，小于20-30埃)的场效应晶体管的栅极电介质的方法。本发明可用于集成半导体器件和电路的制作中。
图1是示出了根据本发明的一个实施例的用于制作场效应晶体管的栅极电介质的方法100的流程图。方法100包括在制作示例性CMOS场效应晶体管的栅极结构期间对衬底执行的处理步骤。在某些实施例中，这些处理步骤是按图示顺序执行的。在替换实施例中，这些步骤中的至少两个步骤可以同时执行或者按不同的顺序执行。子步骤和辅助工艺(例如，处理反应器之间的衬底转移、工艺控制步骤等)是本领域中公知的，因此，这里省略其描述。
方法100中的至少某些部分可以利用集成半导体衬底处理系统(即组合工具)的处理反应器执行。一种这样的处理系统是可以从California，Santa Clara的Applied Materials公司得到的CENTURA集成处理系统。合适的处理系统300的一般描述将在下面参考图3进行讨论。
图2A-2E共同描述了在其上利用图1的方法制作栅极结构的衬底的一系列示意性横截面示图。图2A-2E中的横截面示图涉及被执行用来制作栅极电介质的各个处理步骤。图2A-2E中的图并不是按比例绘出的，而是出于说明目的进行了简化。为了最好地理解本发明，读者应当同时参考图1和图2A-2E。
方法100在步骤102开始，并且前进到步骤104。
在步骤104，提供硅(Si)衬底200(例如，200mm晶片、300mm晶片等)，并将其暴露于一种溶液中以从衬底表面去除天然氧化物(SiO2)层204(图2A)。示例性地，方法100可用于形成晶体管的栅极结构(未示出)。栅极结构一般置于例如晶体管的沟道区226以及源极和漏极区222和224(以虚线示出)上方的区域220中。为了图示清楚，只在图2A中示出了区域220-226。
在一个实施例中，层204是利用包括氟化氢(HF)和去离子(DI)水的溶液(即，氢氟酸溶液)去除的。在一个实施例中，溶液具有约0.1重量％和10重量％之间的HF，温度在约20-30摄氏度(℃)之间。在另一个实施例中，溶液具有约0.5％的HF和约25℃的温度。步骤104可以采用将衬底200湿法浸入到溶液中，接着在去离子水中冲洗的方法，并且可以在单个晶片或批处理水浴(包括超声波增强水浴)中执行。或者，步骤104可以利用集成处理系统300的衬底湿法清洗反应器执行。在另一个实施例中，层204可以利用RCA清洗方法去除。在完成步骤102后，衬底200被置于真空装载室(load lock)或氮气(N2)净化的环境中。
在步骤106，在衬底200上生长热氧化物(SiO2)层206。一般来说，层206可以具有在约2-40埃之间的厚度，优选地在约2-10埃之间。在一个实施例中，层206具有在约6-10埃之间的厚度。步骤106可以利用例如集成处理系统300的RADIANCE
Figure 200610152852810000210003_1
快速热处(RTP)反应器、解耦等离子体氧化(DPO)反应器或等离子体增强化学气相沉积(PECVD)反应器执行。RADIANCE反应器可以从California，Santa Clara的AppliedMaterials公司得到。
在一个实施例中，步骤106可以利用RTP反应器执行以生长层206，这是通过提供约0.5-10slm的氧气(O2)，同时维持约750-850℃的衬底温度和约0.1-50Torr的反应室压强来实现的。工艺持续时间可以在约5-30秒之间。在一个实施例中，提供约2slm的O2，同时维持约800℃的温度和约2Torr的压强。
在另一个实施例中，层206可以通过以下条件在RTP反应器中生长：以约1-10slm的速率提供一氧化二氮(N2O)，以约10-500sccm的速率提供氢气(H2)(即，N2O∶H2流量比范围从约2∶1-1000∶1)，同时维持约750-850℃的衬底温度。另外，步骤106维持约0.5-20Torr的反应室压强。工艺持续时间可以在约5-60秒之间。一个特定的工艺方案在约800℃的温度下以约4.9slm的速率提供N2O，以约50sccm的速率提供H2(即，N2O∶H2流量比为约98∶1)。
在另一个实施例中，步骤106可以利用适合于产生低能等离子体的处理室(如DPO室)执行。等离子体的低能量有助于控制衬底和/或层表面处的反应。例如，等离子体可以利用准远程等离子体源、感应等离子体源和/或RLSA源以及其他等离子体源来产生。在替换实施例中，CW和/或脉冲微波功率源(如磁控管或RLSA微波源)可用于形成层206。
在一个实施例中，可以通过将衬底200暴露于包含氧气(O2)、氧化氮(NO)、一氧化二氮(N2O)等中的至少一种的等离子体，来在DOP反应器中生长层206。另外，等离子体可以可选地包含氮气(N2)和/或可选的惰性气体(例如，氩(Ar)、氦(He)等)。
在一个实施例中，可以通过提供约10-2000sccm的氧气(O2)、约20-500℃的衬底基座温度和约5-1000mTorr之间的反应室压强，利用DPO反应器来形成层206。利用最高达约3-5kW的连续波(CW)或脉冲等离子体功率源例如在13.56MHz激发射频(RF)等离子体。在脉冲化期间，峰值RF功率可以在约10-3000W的范围内，频率可以在约2-100kHz的范围内，占空比可以在约2-50％的范围内。该过程可以执行约1-180秒。在一个实施例中，提供约200sccm的O2，并且约500W的峰值RF功率以约10kHz、约5％的占空比脉冲化，施加到感应等离子体源，温度为约25℃，压强为约40-80mTorr，持续约15-60秒。
在可选的步骤107，可以对氧化物层206进行氮化。层206可以例如在等离子体处理或热处理中氮化。示例性地，步骤107在层206的上部部分中形成了氮化材料的子层207(图2C)。氮化子层207的厚度一般形成在从约0.5-5埃的范围内，优选地在约1-3埃的范围内。
在一个实施例中，层206被暴露于含氮等离子体。在一个实施例中，等离子体包含氮气(N2)，并且可以可选地包含一种或多种可选的惰性气体(例如，氩(Ar)、氦(He)等)。步骤107可以利用例如集成处理系统300的解耦等离子体氮化(DPN)等离子体反应器执行。
在一个实施例中，可以通过提供约10-2000sccm的氮气(N2)，约20-500℃的衬底基座温度和约5-1000mTorr之间的反应室压强，利用DPN反应器来形成子层207。利用最高达约3-5kW的连续波(CW)或脉冲等离子体功率源例如在13.56MHz激发射频(RF)等离子体。在脉冲化期间，峰值RF功率、频率和占空比一般分别在从约10-3000W、约2-100kHz和约2-50％的范围内选择。该过程可以执行约1-180秒。在一个实施例中，提供约200sccm的N2，并且约1000W的峰值RF功率以约10kHz、约5％的占空比脉冲化，施加到感应等离子体源，温度为约25℃，压强为约40-80mTorr，持续约15-60秒。等离子体可以利用准远程等离子体源、感应等离子体源和径向线开槽天线(RLSA)源以及其他等离子体源产生。在替换实施例中，CW和/或脉冲微波源可用于形成子层207。
在可选的步骤107，也可以通过在RTP反应器中将热氧化物层206在高温下暴露于氨气(NH3)或NH3和N2的混合物，或一种或多种惰性气体(如氦、氩等)来对热氧化物层206进行热氮化，以形成氮化材料的子层207。
在一个实施例中，可以通过提供5-1000sccm的氨气(NH3)，同时维持700℃-1000℃的衬底温度和约0.1-10Torr的反应室压强，来利用RTP反应器形成子层207。该过程的持续时间可以在约5-120秒之间。在一个实施例中，提供100sccm的NH3，同时维持约800℃的温度和0.3Torr的压强，持续15秒。可选地，批处理炉可用于形成子层207。
在步骤108，在热氧化物层206上沉积栅极电介质层208(图2D)。层208可以由氮化硅(Si3N4)形成为约2-20埃的厚度，或者可以由高k材料，如氧化铪(HfO2)、硅酸铪(如HfXSiYO，其中x和y是整数)等或其组合形成为约10-60埃的厚度。步骤108可以利用例如集成处理系统300的化学气相沉积(CVD)反应器或原子层沉积(ALD)反应器(如CVD反应器或ALD反应器)执行。一种合适的CVD反应器是可以从Applied Materials公司得到的XGen CVD反应器。
在一个实施例中，利用CVD反应器，栅极电介质层208可以包括氮化硅(Si3N4)，并且可以通过提供约100-1000sccm的氨气(NH3)、约1-100sccm的硅烷(SiH4)(即，NH3∶SiH4流量比范围从1∶1到1000∶1)和约10-1000sccm的氮气(N2)，同时维持约400-750℃的衬底基座温度和约0.1-50Torr之间的反应室压强来形成。该过程可以执行约30-180秒。在一个实施例中，提供约500sccm的NH3、约10sccm的SiH4(即，NH3∶SiH4流量比约为50∶1)和约25sccm的N2，同时维持约600℃的温度和约5Torr的室压强。其他的硅源气体或化学物质可用于替换硅烷(SiH4)，如乙硅烷(Si2H6)、二氯硅烷(DCS)、三氯硅烷(TCS)、四氯硅烷(TCS)或六氯乙硅烷(HCD)。
在另一个实施例中，栅极电介质层208可以包括氧化铪或硅酸铪，并且可以利用CVD或ALD工艺沉积。氧化铪或硅酸铪栅极电介质层208可以利用铪和硅的金属有机或无机前驱体以及包括臭氧、水或远程等离子体氧游离基中的至少一种的氧化剂来形成。
在可选的步骤109，还可以利用与用在形成子层207中类似的工艺来对栅极电介质层208进行进一步氮化。在步骤108之后对栅极电介质层208的可选处理在栅极电介质层208中引入了额外的氮原子，从而提供了通过栅极电介质层208的漏电流的更大减少。栅极电介质层208的氮化一般将氮原子引入到栅极电介质层208中范围约0.5-5埃(优选地约1-3埃)的深度。
在步骤110，通过将栅极电介质层208暴露于含氧等离子体来对其氧化。示例性地，步骤110在层208的上部部分中形成了氧化材料的子层210(图2E)。氧化子层210的厚度一般在从约0.2-10埃(优选地约0.5-5埃)的范围内选择。
在一个实施例中，等离子体包含氧气(O2)、氧化氮(NO)、一氧化二氮(N2O)等中的至少一种，也可以包含可选的氮气(N2)和/或可选的惰性气体(例如，氩(Ar)、氦(He)等)。步骤110可以利用适合于产生低能等离子体的处理室执行。等离子体的低能量有助于控制衬底和/或层表面处的反应。例如，等离子体可以利用准远程等离子体源、感应等离子体源和/或RLSA源以及其他等离子体源来产生。在替换实施例中，CW和/或脉冲微波功率源(如磁控管或RLSA微波源)可用于形成子层210。在一个实施例中，步骤110可以利用例如集成处理系统300的DPN等离子体反应器来执行。
子层210可以通过提供约10-2000sccm的氧气(O2)来形成。氧气可以可选地与N2和/或He和/或Ar混合。衬底基座温度被维持在约20-500℃，反应室中的压强可以在约5-1000mTorr之间。利用最高达约3-5kW的连续波(CW)或脉冲等离子体功率源例如在13.56MHz激发射频(RF)等离子体。在脉冲化期间，峰值RF功率、频率和占空比一般分别在从约10-3000W、约2-100kHz和约2-50％的范围内选择。该过程可以执行约1-180秒。在一个实施例中，提供约200sccm的O2，并且以约10kHz、约5％占空比脉冲化的约1000W的峰值RF功率被施加到感应等离子体源，温度为约25℃，压强为约40mTorr，持续约30秒。
在步骤112，对栅极电介质层208以及层206和衬底200之间氧化物/硅界面退火。步骤112改善了层206和210的漏电流减少，并且增加了沟道区226(图2A中所示)中的电荷载流子的迁移率，并提高了氧化物/硅界面的可靠性。步骤112可以利用合适的热退火室执行，如集成处理系统300的RTP(例如，RADIANCE
Figure 200610152852810000210003_3
或RTP XE+)反应器，或单个衬底或批处理炉。
在一个实施例中，步骤112的退火处理可以在以下条件下执行：提供约2-5000sccm的氧气(O2)和约100-5000sccm的氧化氮(NO)中的至少一种(任何一种气体可选地与氮气(N2)混合)，同时维持约800-1100℃的衬底表面温度和约0.1-50Torr的反应室压强。该过程可以执行约5-180秒。在一个实施例中，提供约500sccm的O2，同时将室维持在约1000℃的温度和约0.1Torr的压强，持续约15秒。在另一个实施例中，提供约500sccm的NO，同时将室维持在约1000℃的温度和约0.5Torr的压强，持续约15秒。
在步骤112完成后，在步骤114，方法100结束。在集成电路的制造中，方法100有利地形成了代表漏电流的高电阻路径的超薄栅极电介质，并且有利于场效应晶体管的沟道区中的电荷载流子的高迁移率。
图3示出了可用于实现图1的方法100的部分步骤的一类示例性的CENTURA
Figure 200610152852810000210003_4
集成半导体衬底处理系统(例如，组合工具)300的示意图。系统300的特定实施例只是示例性的，并且不应当用来限制本发明的范围。应当意识到，方法100可以利用其他半导体衬底处理系统和/或处理反应器实现。
集成处理系统300一般包括真空装载室322、具有机械手330(其设有衬底接收器334)的真空密闭仓328、耦合到仓328的处理模块310、312、314、316和318、输入/输出模块302、可选的测量模块326和系统控制器340。装载室322用作衬底盒的入仓站，并且保护仓328免受大气污染物的影响。机械手330在装载室和处理模块之间转移衬底。机械手330的图示实施例是示例性的，并且不应当用来限制本发明的范围。输入/输出模块302包括至少一个前端开口统一吊舱(FOUP)306(示出了两个FOUP 306)，FOUP 306有利于在工厂接口324、测量模块326和装载室322之间交换衬底盒。
系统控制器340一般包括中央处理单元(CPU)342、存储器344和支持电路346，并且耦合到集成处理系统300的各模块和装置并控制这些模块和装置，以及能够收集来自各个模块的数据和反馈以优化系统300的性能。在操作中，控制器340直接控制系统300的模块和装置，或者与这些模块和装置相关联的管理者计算机(或控制器)。
处理模块310、312、314、316和318中的至少一个可以是RTP反应器(例如RADIANCE反应器)、PECVD反应器、CVD反应器(例如XGen反应器)、ALD反应器、DPN反应器和/或适合于执行如上参考图1所述的过程的其他反应器。用于执行根据本发明的工艺的系统300的可能配置的一个示例包括两个装载室322、两个RTP模块310和312、ALD模块314、CVD模块316、DPN模块318、包括测量工具304以及机械手308和320的测量模块326、以及包括两个FOUP 306的输入/输出模块302。应当意识到，系统300的其他配置也可用于实现上述的本发明。
本发明可以利用其他过程实现，其中参数可由本领域技术人员通过利用这里公开的教导加以调节以实现可接受的特性，而不脱离本发明的范围。尽管前述讨论涉及场效应晶体管的制作，但是在集成电路中使用的其他器件和结构的制作也可以得益于本发明。
尽管前述内容针对本发明的实施例，但是在不脱离本发明基本范围的前提下可以作出本发明的其他和另外的实施例，本发明的范围由权利要求确定。

Claims (26)

1.一种用于制作场效应晶体管的栅极电介质的方法，包括：
(a)提供硅衬底；
(b)从所述硅衬底去除天然氧化物层；
(c)在所述硅衬底上形成氧化物层并对所述氧化物层进行氮化；
(d)在所述氧化物层上形成栅极电介质层；
(e)利用含氧等离子体氧化所述栅极电介质层的至少一部分；以及
(f)对所述栅极电介质层、所述氧化物层以及所述氧化物层和所述硅衬底之间的界面进行退火。
2.如权利要求1所述的方法，还包括：
从步骤(c)到步骤(e)将所述硅衬底维持在真空环境中。
3.如权利要求1所述的方法，还包括：
从步骤(c)到步骤(f)将所述硅衬底维持在真空环境中。
4.如权利要求1所述的方法，其中步骤(b)还包括：
将所述衬底暴露于包括氟化氢和去离子水的溶液中。
5.如权利要求1所述的方法，其中步骤(c)还包括：
形成所述氧化物层到2-10埃之间的厚度。
6.如权利要求1所述的方法，其中步骤(c)还包括：
在热处理中形成所述氧化物层，所述热处理包括将所述硅衬底暴露于包括氧气或一氧化二氮中的至少一种的气氛中。
7.如权利要求1所述的方法，其中步骤(c)还包括：
在等离子体处理中形成所述氧化物层，所述等离子体处理包括将所述硅衬底暴露于包括氧气或氧化氮或一氧化二氮中的至少一种的等离子体中。
8.如权利要求1所述的方法，其中所述氮化步骤还包括：
在所述氧化物层中形成厚度在0.5-5埃之间的氮化材料子层。
9.如权利要求1所述的方法，其中所述氮化步骤还包括：
将所述氧化物层暴露于含氮等离子体中。
10.如权利要求1所述的方法，其中所述氮化步骤还包括：
在包括氨气的气氛中对所述氧化物层进行热氮化。
11.如权利要求1所述的方法，其中步骤(d)还包括：
由氮化硅、氧化铪和硅酸铪中的至少一种形成所述栅极电介质层。
12.如权利要求11所述的方法，其中步骤(d)还包括：
由氧化铪或硅酸铪中的至少一种形成所述栅极电介质层至10-60埃的厚度。
13.如权利要求11所述的方法，还包括：
由氮化硅形成所述栅极电介质层至2-10埃的厚度。
14.如权利要求1所述的方法，其中步骤(c)还包括：
对所述栅极电介质层进行氮化。
15.如权利要求14所述的方法，其中所述氮化步骤还包括：
将所述栅极电介质层暴露于含氮等离子体中。
16.如权利要求14所述的方法，其中所述氮化步骤还包括：
在包括氨气的气氛中对所述栅极电介质层进行热氮化。
17.如权利要求1所述的方法，其中步骤(e)还包括：
使用含氧气体的等离子体。
18.如权利要求17所述的方法，其中所述含氧气体包括氧气、氧化氮和一氧化二氮中的至少一种。
19.如权利要求1所述的方法，其中步骤(e)还包括：
在所述栅极电介质层的上部部分中形成厚度0.2-10埃的氧化子层。
20.如权利要求1所述的方法，其中步骤(f)还包括：
在快速热处理室或炉中对所述衬底进行热退火。
21.如权利要求1所述的方法，其中：
步骤(b)还包括将所述衬底置于氮气净化的或真空环境中；
步骤(c)还包括在所述硅衬底上形成热氧化物层作为所述氧化物层；以及
步骤(f)还包括对所述衬底进行热退火。
22.如权利要求21所述的方法，还包括：
在步骤(e)之前对所述栅极电介质层进行氮化。
23.一种用于制作场效应晶体管的栅极电介质的集成半导体衬底处理系统，包括：
被配置用于在硅衬底上形成热氧化物层的至少一个第一反应器；
被配置用于在所述热氧化物层上沉积栅极电介质层的至少一个第二反应器；
被配置用于氧化所述栅极电介质层的至少一个第三反应器；
至少一个装载室；
耦合到所述反应器中的每一个和装载室的至少一个衬底转移室；以及
管理并监视所述处理系统的操作的控制器。
24.如权利要求23所述的处理系统，还包括：
被配置用于从所述硅衬底去除天然氧化物层的至少一个第四反应器。
25.如权利要求23所述的处理系统，还包括：
被配置用于对经氧化的栅极电介质层、所述热氧化物层以及所述热氧化物层和所述硅衬底之间的界面进行退火的至少一个第五反应器。
26.如权利要求25所述的处理系统，其中所述至少一个第一反应器是快速热处理反应器或等离子体增强化学气相沉积反应器，
其中所述至少一个第二反应器是化学气相沉积反应器或原子层沉积反应器，
其中所述至少一个第三反应器是射频等离子体反应器；并且还包括：
被配置用于从所述硅衬底去除天然氧化物层的至少一个单晶片湿法清洗反应器，和
被配置用于对经氧化的栅极电介质层、所述热氧化物层以及所述热氧化物层和所述硅衬底之间的界面进行退火的至少一个快速热处理反应器。
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