TWI450338B - 場效電晶體之閘極介電質的製造方法 - Google Patents

場效電晶體之閘極介電質的製造方法 Download PDF

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TWI450338B
TWI450338B TW095137757A TW95137757A TWI450338B TW I450338 B TWI450338 B TW I450338B TW 095137757 A TW095137757 A TW 095137757A TW 95137757 A TW95137757 A TW 95137757A TW I450338 B TWI450338 B TW I450338B
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substrate
oxide layer
gate dielectric
layer
reaction chamber
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TW200721323A (en
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Thai Cheng Chua
Khaled Z Ahmed
Cory Czarnik
Philip Allan Kuaus
Christopher Sean Olsen
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Applied Materials Inc
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    • H01L21/31658—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself by thermal oxidation, e.g. of SiGe
    • H01L21/31662—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself by thermal oxidation, e.g. of SiGe of silicon in uncombined form
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Description

場效電晶體之閘極介電質的製造方法
本發明實施態樣大致係關於在半導體基材上製造元件的方法。更明確的說，本發明係關於一種製造場效電晶體的方法，特別是一種製造場效電晶體之閘極介電質的方法。
積體電路可包含百萬個以上形成在其基板上且彼此可於電路內協同執行各種功能的微型電子場效電晶體(例如，互補式金氧半導體(CMOS)場效電晶體)。一CMOS電晶體包括位於一通道區域上方的閘極結構，該通道區域係形成在該電晶體的源極與汲極區域間。該閘極結構一般包括一閘極電極及一閘極介電質(a gate dielectric)。該閘極電極位在該閘極介電質上方，且當其運作時可被用來控制閘極介電質下方通道區域內電荷載子(即，電流)的流動。
該閘極介電質一般是由氮化矽(Si3 N4 )或氧氮化矽(SiON)所形成。為提高電晶體的速度，在高階積體電路中的閘極介電質厚度一般設定在約20-30Å，或更低。但是，製造具有如此薄之閘極介電質的閘極結構是一項大挑戰。製造技術上的一大問題就是來自閘極介電質的高漏電流，以及因為大量氮氣擴散進入電晶體中的矽/閘極介電質界面所導致的通道區域內電荷載子遷移力下降。
因此，亟需提供一種用以製造場效電晶體之閘極介電質的改良方法。
本發明大致係關於一種用以製造一場效電晶體之閘極介電質的方法。本發明可被用於諸如微處理器、具特定用途的積體電路(Application specific integrated circuits,ASICs)、電子記憶元件等類的積體電路元件中。
在一實施例中，本發明包括以下步驟：從一矽基材上移除一原生氧化物層，在該基材上生成一氧化物層，在該氧化物層上生成一閘極介電質(例如，氮化矽(Si3 N4 )、氧化鉿(HfO2 )、矽酸鉿(HfSix Oy ，其中x及y為整數)等類似物)，將該閘極介電層氧化，及將所生成的層以及介於該熱氧化層與基材間的界面加以退火。選擇性的，可於形成該閘極介電質層之前，先將該氧化物層加以氮化。選擇性的，可於氧化該閘極介電質層之前，先將該閘極介電質層加以氮化。在一實施例中，可以一集積式半導體基材處理系統(亦即，群集工具(a cluster tool))的處理室來實施至少一部份之本發明方法步驟。
在另一實施例中，一種用以在一基材上製造一場效電晶體之閘極介電質的方法，包括以下步驟：從該基材上移除一原生氧化物層及將該基材放置在充滿氮氣或是真空的環境內；在該矽基材上生成一熱氧化物層；在該熱氧化物層上生成一閘極介電質層；以一含氧電漿將至少一部份該閘極介電層氧化；及將具有該熱氧化物層及該氧化的閘極介電質層形成於其上之基材加以熱退火。
在本發明另一態樣中，揭示一種集積式半導體基材處理系統，用以製造一場效電晶體之閘極介電質。在一實施例中，該系統包括至少一第一反應室，其係用以在一矽基材上生成一熱氧化物層；至少一第二反應室，其係用以沉積一閘極介電層在該熱氧化物層上；至少一第三反應室，其係用以將該閘極介電層氧化；至少一負載鎖定室；至少一基材傳送室，其係耦接至每一上述反應室及該些負載鎖定室；及一控制器，用來管理及監控該處理系統的操作。
本發明是一種用來製造具有超薄閘極介電質(例如，低於約20至30Å)之場效電晶體的閘極介電質的方法。本發明可被用來製造積體半導體元件和電路。
第1圖的流程圖依據本發明一實施例來說明製造一場效電晶體之閘極介電質的方法100。該方法100包括在製造一實例的CMOS場效電晶體的閘極結構期間，於一基材上執行的各種處理步驟。在某些實施例中，這些處理步驟係依據所揭示順序實施。在其他實施例中，這些步驟中的至少兩步驟可同時實施或以不同順序來實施。一些次要步驟及輔助性步驟(例如，在反應室、反應控制步驟等之間移送基材的步驟)，因為已是此領域中習知的，故在此省略不提。
該方法100的至少某些部份可使用一種集積式半導體基材處理系統(亦即，群集工具)中的處理反應室來實施。 這類處理系統之一為美商應用材料公司出品的CENTURA®集積式處理系統。以下將參照第3圖來描述一適當的處理系統300。
第2A至2E圖一起繪示出以第1圖方法於一基材上所製作的一閘極結構的一系列橫截面示意圖。第2A-2E圖中的橫截面圖係關於所執行用以製造該閘極結構的個別處理步驟。第2A至2E圖的影像並未成比例地繪示，且為方便顯示已加以簡化。為能更清楚了解本發明，需同時參閱第1及2A至2E圖。
方法100以步驟102開始並持續進行到步驟104。
在步驟104中，提供一矽基材200(即，200毫米的晶圓、300毫米的晶圓等)，並將其暴露在一種可移除基材表面上一原生氧化物層(SiO2 )的溶液中(第2A圖)。可以方法100來形成電晶體的閘極結構(未示出)。該閘極結構一般係設置在區域220中，位於電晶體源極與汲極區域222和224(以虛線表示)和通道區域226的上方。為簡化圖示起見，第2A圖中只繪示出區域220-226。
在一實施例中，以一種包含氫氟酸(HF)及去離子水(DI water)的溶液(亦即，氫氟酸溶液)來移除層204。在一實施例中，該溶液含有約0.1%至10%(重量%)的HF，且溫度在約20至30℃間。在另一實施例中，該溶液含有約0.5%的HF，且溫度約25℃。步驟104使用一種濕浸泡方式，將基材200浸泡在該溶液中，接著以去離子水清洗，可以使用單一晶圓或是批次晶圓方式為之，包括使用超音波來提高 洗浴的效果。或者，可以該集積式半導體基材處理系統300的一單一基材濕潔淨反應室來實施步驟104。在另一實施例中，可以一種RCA清潔法來移除該層204。一旦完成步驟102後，將基材200放置在一真空負載環境或充滿氮氣的環境下。
在步驟106，於基材200上生長一層熱氧化物(SiO2 )層206(第2B圖)。一般來說，該層206的厚度在約2至40Å間。在一實施例中，該層206的厚度在約6-10Å間。可使用該集積式半導體基材處理系統300之反應室，例如，RADIANCE®快速熱處理(RTP)反應室、去耦合電漿氧化(DPO)反應室、或電漿強化化學氣相沉積室(PECVD)來執行步驟106。RADIANCE®快速熱處理(RTP)反應室可購自美商應用材料公司。
在一實施例中，於步驟106中，係以一RTP反應室來生長該層206，其係利用供應約5-10slm的氧氣，同時將基材溫度維持在750至850℃、反應室壓力維持在0.1-50Torr下。處理期間可以在約5至30秒。在一實施例中，係以約2slm的速度來供應氧氣，同時將基材溫度維持在約800℃、反應室壓力維持在約2Torr。
在另一實施例中，藉由以約1至10slm的速度供應一氧化二氮(N2 O)、以約10至500slm的速度供應氫氣(亦即，N2 O：H2 的流速比率介於約2：1至1000：1間)，同時將基材溫度維持在750至850℃間，而於一RTP反應室中生長該層206。此外，在步驟106中，反應室壓力係維持在約 0.5至20Torr間。處理期間可以在約5至60秒。一特定處理配方包括以約4.9slm的速度供應一氧化二氮(N2 O)、以約50sccm的速度供應氫氣(亦即，N2 O：H2 的流速比率介於約98：1間)，同時將基材溫度維持在約800℃間。
在另一實施例中，可使用適合製造低能量電漿的製程室，例如，DPO反應室，來執行步驟106。低能量電漿有助於控制基材表面及/或層的反應。舉例來說，可使用一準-遠端電漿源、一誘導式電漿源、及/或一RLSA源及其他電漿源等等，來產生電漿。在其他實施例中，可以連續波(CW)及/或脈衝式的微波能量之類的來源，例如磁控管或RLSA微波源，來形成該層206。
在一實施例中，可藉由在一DPO反應室內將基材200暴露在一電漿中的方式來生成該層206，其中該電漿包含至少下列一者：O2 、NO、N2 O等類似物。此外，該電漿還可選擇性地包含N2 及/或一選擇性包含的惰性氣體(例如，氬氣、氦氣等)。
在一實施例中，可於一DPO反應室中，以約10至2000sccm的速度提供O2 ，並將製程室壓力維持在約5至1000mTorr間的方式，來形成該層206。可使用高達約3至5kW的連續波(continuous wave,CW)或脈衝式電漿源，於例如13.56MHz的頻率下，來激發該無線電波(RF)電漿。脈衝期間，RF電力尖峰可以在約10至3000瓦間，頻率在約2至100kHz間，且其功率週期(duty cycle)在約2至50%間。執行此製程約1至180秒。在一實施例中，以約200sccm 的速度提供O2 ，在約10kHz、約5%功率週期下將約500瓦尖峰RF電力加以脈衝並施加至一誘導式電漿源，並將製程室溫度維持在約25℃且製程室壓維持在約40至80mTorr間，製程持續約15至60秒。
在一選擇性實施的步驟107中，將該氧化物層206加以氮化。例如，該層206可以在一電漿處理中或一熱處理中加以氮化。步驟107可在該層206的一上方部位形成一由氮化材料構成的子層207(第2C圖)。該氮化子層207的厚度一般為約0.5至5Å間，較佳是約1至3Å間。
在一實施例中，該層206是被暴露在一含氮電漿中。在一實施例中，該電漿包含氮氣，且可選擇性地包含一或多種其他選擇性添加的惰性氣體(例如，氬氣、氦氣等類似氣體)。可使用諸如該集積式處理系統300中的去耦合電漿碳化(DPN)電漿反應器，來實施該步驟107。
在一實施例中，可藉由提供流速約10至2000sccm的氮氣、約20至500℃間之基材平台溫度、及約至-1000mTorr間之反應室壓力，而在一DPN反應室中形成該子層207。使用高達約3至5kW之一連續波(CW)或脈衝式電漿電力，於13.56MHz頻率下，激發無線電波頻率(RF)電漿。在脈衝期間，一般將RF電力尖峰設在約10至3000瓦間，頻率在約2至100kHz間，且其功率週期(duty cycle)在約2至50%間，執行此製程約1至180秒。在一實施例中，以約200sccm的速度提供N2 ，在約10kHz、5%功率週期下將約1000瓦尖峰RF電力加以脈衝並施加至一誘導式電 漿源，並將溫度維持在約25℃且壓力維持在約40至80mTorr間，持續約15至60秒。可使用一準遠端電漿源(a quasi-remote plasma source)、一誘導式電漿源、及一圓極化俓向線縫隙天線(radial line slotted antenna,RLSA)源等等其他電漿源來產生電漿。在其他實施例中，可使用CW及/或脈衝式微波電力來形成該子層207。
在一選擇性實施的步驟107中，在一RTP反應室中，於高溫下藉由將該熱氧化物層206暴露在一NH3 ，或一由NH3 及N2 組成的混合氣體中，或一或多種諸如氦氣、氬氣等類似氣體下，將該熱氧化物層206進行熱氮化而形成氮化材料製成的子層207。
在一實施例中，以約5至1000sccm的速度提供NH3 ，同時將基材溫度維持在約700至1000℃間，且製程室壓力維持在約0.1至10Torr間，而於一RTP反應室內形成該子層207。製程可持續約5至120秒。
在步驟108中，一閘極介電層208被沉積在該熱氧化物層206上方(第2D圖)。該層208可由氮化矽(Si3 N4 )所形成，至約2至20Å的厚度、或是由諸如氧化鉿(HfO2 )、矽酸鉿(Hfx Siy O，其中x及y為整數)或其之組合等類的高k介電材料所形成，至約10至60Å的厚度。可使用該集積式處理系統300內，諸如一化學氣相沉積(CVD)反應室或一原子層沉積(ALD)反應室之類的CVD反應室或ALD反應室來實施步驟108。一種適當的CVD反應室為美商應用材料公司出品的XGen CVD反應室。
在一實施例中，使用一CVD反應室，該閘極介電層208包含氮化矽(Si3 N4 )且可利用提供流速在約100至1000sccm間之氨氣(NH3 )、流速在約1至100sccm間之矽甲烷(SiH4 )(亦即，NH3 ：SiH4 的流速比在1：1至1000：1間)、及流速在約10至1000sccm間之氮氣，同時維持基材平台溫度在約400至750℃，且反應室壓力在約0.1至50Torr間的方式來形成。此製程可實施約30至180秒。在一實施例中，提供約500sccm的NH3 、約10sccm的SiH4 (亦即，NH3 ：SiH4 的流速比約為50：1)、約25sccm的N2 ，同時維持該室中的溫度在約600℃且壓力在約5Torr。其他可用來取代矽甲烷(SiH4 )的矽源氣體或化學物包括矽乙烷(Si2 H6 )、二氯矽甲烷(DSC)、三氯矽甲烷(TCS)、四氯矽甲烷(TCS；tetrachlorosilane)、或六氯矽乙烷(HCD)。
在另一實施例中，該閘極介電層208可包含氧化鉿或矽酸鉿且可使用一CVD或一ALD製程來沉積之。該氧化鉿或矽酸鉿閘極介電層208可使用鉿與矽的金屬-有機前驅物或無機前驅物，與一氧化劑(包含至少下列一種：臭氧、水或遠端電漿氧自由基)來形成。
一選擇性實施的步驟109，該閘極介電層208可進一步以一用來形成子層207的類似製程來加以氮化。在步驟108之後對該閘極介電層208所實施的選擇性處理會引入額外的氮原子到該閘極介電層208中，藉以經由該閘極介電層208來更大幅度地降低漏電流。該閘極介電層208的氮化一般可將氮原子引入至約0.5至5Å的深度，較佳是約1 至3Å的深度。
在步驟110中，藉由將該閘極介電層208暴露至含氧電漿內而將該閘極介電層208加以氧化。步驟110可於該層208的一上方部份形成一氧化材料子層210。該氧化的子層210的厚度一般選擇在約0.2至10Å間，較佳是在約0.5至5Å間。
在一實施例中，電漿含有至少一種下列物質：氧氣、一氧化氮(NO)、一氧化二氮(N2 O)等類似物；且可包含選擇添加的氮氣及/或選擇添加的惰性氣體(例如，氬氣、氦氣等類似氣體)。可以一種適合產生低能量電漿的製程室來實施步驟110。該低能量的電漿可幫助控制該基材及/或該層表面處的反應。舉例來說，可使用一準遠端電漿源、一誘導式電漿源、及/或一圓極化俓向線縫隙天線(radial line slotted antenna,RLSA)源等等其他電漿源來產生電漿。在其他實施例中，可使用諸如磁控管或RLSA微波源之類的CW及/或脈衝式微波電力來形成該子層210。在一實施例中，可使用諸如該集積式處理系統300中的去耦合電漿碳化(DPN)電漿反應室，來實施該步驟110。
可利用提供流速約10至2000sccm間的氧氣，來形成該子層210。該氧氣可被選擇性地混入氮氣及/或氦氣及/或氬氣。基材平台溫度被維持在約20至500℃間，反應室內的壓力維持在約5至1000mTorr間。RF電漿係在例如13.56MHz的頻率下以高達約3至5kW的連續波(CW)或脈衝式電力將其激發。在脈衝期間，一般將RF電力尖峰 設在約10至3000瓦間，頻率在約2至100kHz間，且其功率週期(duty cycle)在約2至50%間，並執行該氧化製程約1至180秒。在一實施例中，以約200sccm的速度提供O2 ，在約10kHz、約5%功率週期下將約1000瓦尖峰RF電力加以脈衝並施加至一誘導式電漿源，並將製程室溫度維持在約25℃且壓力維持在約40mTorr，持續約30秒。
在步驟112中，將該閘極介電層208及介於該層206與基材200間的氧化物/矽界面加以退火。步驟112可改善層206及210漏電流降低的情形，以及提高通道區域226中的荷電載子的遷移力(顯示在第2A圖中)，以及改善氧化物/矽界面的可靠性。可使用一適當的熱退火室來實施步驟112，例如該集積式處理系統300中的一RTP反應室(例如，RADIANCE®或RTP XE+)，或是一單一基材或是批式烤爐(batch furnace)。
在一實施例中，可藉由提供至少一種下列物質：約2至5000sccm間的氧氣及約100至5000sccm間的NO(此兩種氣體的任一種可選擇性的與氮氣混合)，同時將基材表面溫度維持在約800至1100℃，且將反應室中的壓力維持在0.1至50torr間來執行該退火步驟112。該製程可實施約5至180秒。在一實施例中，以約500sccm的流速來提供氧氣，同時將該室溫度維持在約1000℃，且壓力維持在0.1Torr一段約15秒的期間。在另一實施例中，係以約500sccm的速度來供應NO，同時將該室溫度維持在約1000℃，且壓力維持在0.5Torr一段約15秒的期間。
待完成步驟112之後，在步驟114中，方法100即已結束。在製造積體電路時，方法100的優點是會形成可代表漏電流之高電阻路徑的超薄閘極介電層，並促進場效電晶體通道區域中之荷電載子的高遷移力。
第3圖為可用來實施第1圖中部份方法100之實例性CENTURA®集積式半導體基材處理系統300(即，群集工具)的示意圖。該系統300的特定實例乃係為了闡述本發明概念而繪示，且不應用來限制本發明範疇。可預期方法100也可使用其他半導體基材處理系統及/或反應室來實施。
此集積式半導體基材處理系統300通常包括真空加載鎖定室322，真空氣室328(其具有連接至一基材承座334的機器人330)，耦接至該氣室328的多個處理模組310、312、314、316及318，輸入/輸出模組302，選擇性安裝的度量模組326及系統控制器340。使用該加載鎖定室322作為可讓基材卡匣停靠的停靠站並可保護該氣室328不受大氣污染物的影響。機器人330可在加載鎖定室322與處理模組間傳送基材。所繪示機器人實施例僅為供闡述本發明用的例舉實例，本發明範疇並非僅限於此。該輸入/輸出模組302包含至少一個前端開口一體槽(FOUP)306(圖中繪出兩FOUP 306)，其有助於在一工廠界面324、度量模組326及加載鎖定室322三者間交換基材卡匣。
該系統控制器340一般包括中央處理單元(CPU)342、記憶體344、及支持電路346，其被耦接至該集積式基材處理系統300並可控制該系統300的多個模組及設備，以及 可收集來自個別模組的回饋資料以使系統300的效能趨於最佳狀態。操作時，控制器340可使用該系統300之一直接控制模組與設備，或者，與這些模組與設備相連的管理者電腦(或控制器)。
該些處理模組310、312、314、316及318中至少一者可為RTP反應室(例如，RADIANCE® 反應室)、PECVD反應室、CVD反應室(例如，XGen反應室)、ALD反應室、DPN反應室及/或其他適於執行第1圖所述製程的反應室。可用來執行本發明方法之一適當組合的系統300會包括兩個加載鎖定室322、兩個RTP模組310及312、一個ALD模組314、一CVD模組316、一DPN模組318、一度量模組326(其包含一測量工具304及機器人308和320)、及輸入/輸出模組302(其包含兩個FOUP 306)。也可使用其他組裝形式的系統300來執行本發明。
本發明可使用其他製程來實施，只要依據本發明說明書揭示內容恰當調整製程參數來達到欲求目的。雖然前述內容係針對一場效電晶體而言，但積體電路中其他元件及結構的製造亦可受惠於本發明。
雖然本發明已用本發明之實施例被明確地示出及說明，但熟習此技藝者將可瞭解的是上述在形式及細節上之其它形式與細節上的改變可在不偏離本發明的範圍及精神下被達成。因此，本發明並不侷限於所示及所說明的特定形式與細節，而是落在由以下的申請專利範圍所界定的範圍內。
100‧‧‧方法
102、104、106、107、108、109、110、112、114‧‧‧步驟
200‧‧‧基材
204‧‧‧原生氧化物層
206‧‧‧熱氧化物層
207、210‧‧‧子層
208‧‧‧閘極介電層
220‧‧‧區域
222‧‧‧源極區域
224‧‧‧汲極區域
226‧‧‧通道區域
300‧‧‧處理系統
302‧‧‧輸入/輸出模組
306‧‧‧前端開口一體槽(FOUP)
310、312、314、316、318‧‧‧處理模組
322‧‧‧真空加載鎖定室
324‧‧‧工廠界面
326‧‧‧度量模組
328‧‧‧氣室
330‧‧‧機器人
334‧‧‧基材承座
340‧‧‧系統控制器
342‧‧‧CPU(中央處理器)
344‧‧‧記憶體
346‧‧‧支持電路
第1圖繪示出一流程圖，其示出依據本發明一實施例來製作一場效電晶體之閘極介電質的方法；第2A-2E圖一起繪示出以第1圖方法於一基材上所製作的一閘極結構的一系列橫截面示意圖；第3圖為一例示可用來實施本發明部份方法之集積式半導體基材處理系統的示意圖。
100‧‧‧方法
102、104、106、107、108、109、110、112、114‧‧‧步驟

Claims (25)

  1. 一種用以製造一場效電晶體之一閘極介電質的方法，該方法包含：(a)提供一矽基材；(b)藉由將該矽基材曝露至一溶液，自該矽基材上移除一原生氧化物層；(c)使用一電漿處理或一熱處理至少一者，在該矽基材上形成一氧化物層；(d)在該氧化物層形成一閘極介電層，其中該閘極介電層係由氮化矽形成；(e)使用一含氧電漿將至少一部份之該閘極介電層加以氧化；及(f)將該閘極介電層、該氧化物層及位於該氧化物層與該矽基材間之界面加以退火(anneal)。
  2. 如申請專利範圍第1項所述之方法，更包含：從步驟(c)至步驟(e)，將該矽基材維持在一真空環境下。
  3. 如申請專利範圍第1項所述之方法，更包含：從步驟(c)至步驟(f)，將該矽基材維持在一真空環境下。
  4. 如申請專利範圍第1項所述之方法，其中步驟(b)更包含： 將該基材暴露在一種包含氟化氫及去離子水的溶液中。
  5. 如申請專利範圍第1項所述之方法，其中步驟(c)更包含：形成該氧化物層至厚度在約2至10Å間。
  6. 如申請專利範圍第1項所述之方法，其中步驟(c)更包含：在一熱處理中形成該氧化物層，該熱處理包括將該氧化物層暴露在包含氧氣或一氧化二氮(nitrous oxide)至少一者的一氛圍下。
  7. 如申請專利範圍第1項所述之方法，其中步驟(c)更包含：在一電漿處理中形成該氧化物層，該電漿處理包括將該氧化物層暴露在包含氧氣或一氧化氮(nitric oxide)至少一者，或一氧化二氮(nitrous oxide)的一電漿下。
  8. 如申請專利範圍第1項所述之方法，其中步驟(c)更包含：將該氧化物層氮化。
  9. 如申請專利範圍第8項所述之方法，其中該氮化步 驟更包含：在該氧化物層上創造出厚度約0.5至5Å間的一氮化材料子層。
  10. 如申請專利範圍第8項所述之方法，其中該氮化步驟更包含：將該氧化物層暴露在含氮電漿下。
  11. 如申請專利範圍第8項所述之方法，其中該氮化步驟更包含：在一包含氨的氛圍下將該氧化物層加以熱氮化。
  12. 如申請專利範圍第1項所述之方法，更包含：從氮化矽來形成厚度約2至10Å的該閘極介電層。
  13. 如申請專利範圍第1項所述之方法，其中步驟(d)更包含：將該閘極介電層氮化。
  14. 如申請專利範圍第13項所述之方法，其中該氮化步驟更包含：將該閘極介電層暴露在含氮電漿下。
  15. 如申請專利範圍第13項所述之方法，其中該氮化步驟更包含：在一包含氨的氛圍下將該閘極介電層加以熱氮化。
  16. 如申請專利範圍第1項所述之方法，其中步驟(e)更包含：使用一種由含氧氣體所形成的電漿。
  17. 如申請專利範圍第16項所述之方法，其中該含氧氣體包含至少一種下列氣體：氧氣、一氧化氮與一氧化二氮。
  18. 如申請專利範圍第1項所述之方法，其中步驟(e)更包含：在該閘極介電層的一上方部份中形成一厚度介於約0.2至10Å間的氧化子層。
  19. 如申請專利範圍第1項所述之方法，其中步驟(f)更包含：在一快速熱處理室或一爐中將該基材加以熱退火。
  20. 如申請專利範圍第1項所述之方法，其中： 步驟(b)更包含將該基材放置在一充滿氮氣或真空的環境下；步驟(c)更包含在該矽基材上形成一熱氧化物層；以及步驟(f)更包含將該基材加以熱退火。
  21. 如申請專利範圍第20項所述之方法，更包含：在實施步驟(d)之前，將該熱氧化物層氮化。
  22. 如申請專利範圍第20項所述之方法，更包含：在實施步驟(e)之前，將該閘極介電層氮化。
  23. 如申請專利範圍第1項所述之方法，其中步驟(b)更包含：將該基材暴露在一種包含氟化氫及去離子水的溶液中；且其中步驟(f)更包含：在一快速熱處理室或一爐中將該基材加以熱退火。
  24. 一種用以製造一場效電晶體之一閘極介電質的集積式半導體基材處理系統，該系統包含：至少一第一反應室，藉由使用一電漿處理或一熱處理之至少一者，將一熱氧化物層形成在一矽基材上；至少一第二反應室，用以沉積一氮化矽閘極介電層在該熱氧化物層上； 至少一第三反應室，藉由使用一含氧電漿，將該閘極介電層加以氧化；至少一第四反應室，用以自該矽基材移除一原生氧化物層；至少一第五反應室，用以退火該氧化的閘極介電層、該熱氧化物層、及位於該氧化物層與該矽基材間的一界面；至少一加載鎖定室；至少一基材傳送室，耦接至每一上述反應室及加載鎖定室；及一控制器，可管理及監控該處理系統的運作。
  25. 如申請專利範圍第24項所述之處理系統，其中該至少一第一反應室為一快速熱處理反應室或一電漿強化化學氣相沉積反應室(PECVD)，其中該至少一第二反應室為一化學氣相沉積反應室(CVD)或一原子層沉積反應室(ALD)，其中該至少一第三反應室為一無線電波頻率電漿反應室；其中該至少一第四反應室包含至少一單一晶圓濕潔淨反應室，用以自該矽基材移除一原生氧化物層；以及其中該至少一第五反應室包含至少一快速熱處理反應室，用以退火該氧化的閘極介電層、該熱氧化物層、及位於該熱氧化物層與該矽基材間的一界面。
TW095137757A 2005-10-20 2006-10-13 場效電晶體之閘極介電質的製造方法 TWI450338B (zh)

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