TWI415193B - 用以製造場效電晶體之閘極介電質的方法 - Google Patents

用以製造場效電晶體之閘極介電質的方法 Download PDF

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TWI415193B
TWI415193B TW096115996A TW96115996A TWI415193B TW I415193 B TWI415193 B TW I415193B TW 096115996 A TW096115996 A TW 096115996A TW 96115996 A TW96115996 A TW 96115996A TW I415193 B TWI415193 B TW I415193B
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Taiwan
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oxide layer
gate dielectric
layer
substrate
dielectric layer
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TW096115996A
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English (en)
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TW200743162A (en
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Thai Cheng Chua
Cory Czarnik
Andreas G Hegedus
Christopher Sean Olsen
Khaled Z Ahmed
Philip Allan Kraus
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Applied Materials Inc
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Description

用以製造場效電晶體之閘極介電質的方法
本發明實施態樣大致係關於在半導體基材上製造元件的方法。更明確的說，本發明係關於一種製造場效電晶體的方法，特別是一種製造場效電晶體之閘極介電質的方法。
積體電路可包含百萬個以上形成在其基板上且彼此可於電路內協同執行各種功能的微型電子場效電晶體(例如，互補式金氧半導體(CMOS)場效電晶體)。一CMOS電晶體包括位於一通道區域上方的閘極結構，該通道區域係形成在該電晶體的源極與汲極區域間。該閘極結構一般包括一閘極電極及一閘極介電質(a gate dielectric)。該閘極電極位在該閘極介電質上方，且當其運作時可被用來控制閘極介電質下方通道區域內電荷載子(即，電流)的流動。
該閘極介電質一般是由氮化矽(Si3 N4 )或氧氮化矽(SiON)所形成。為提高電晶體的速度，在高階積體電路中的閘極介電質厚度一般設定在約20-30Å，或更低。但是，製造具有如此薄之閘極介電質的閘極結構是一項大挑戰。製造技術上的一大問題就是來自閘極介電質的高漏電流，以及因為大量氮氣擴散進入電晶體中的矽/閘極介電質界面所導致的通道區域內電荷載子遷移力下降。此外，氮與閘極電極之多晶矽間的反應也會使VFB /Vt 偏移，其中VFB 為扁平帶電壓且Vt 為閥電壓(threshold voltage)。
因此，亟需提供一種用以製造場效電晶體之閘極介電質的改良方法。
本發明實施例大致係關於一種用以製造一場效電晶體之閘極介電質的方法。本發明可被用於諸如微處理器、具特定用途的積體電路(Application specific integrated circuits,ASICs)、電子記憶元件等類的積體電路元件中。
在一實施例中，本發明包括以下步驟：從一矽基材上移除一原生氧化物層，在該基材上生成一第一氧化物層，在該第一氧化物層上生成一閘極介電質(例如，氮化矽(Si3 N4 )、氧化鉿(HfO2 )、矽酸鉿(HfSix Oy ，其中x及y為整數)等類似物)，在該閘極介電層上生成一第二氧化物層，及將所生成的層以及該第一氧化層與基材間的界面加以退火。選擇性的，可於形成該閘極介電質層之前，先將該基材上的第一氧化物層加以氮化。選擇性的，也可於該閘極介電質層上生成該第二氧化物層之前，先將該閘極介電質層加以氮化。在一實施例中，可以一集積式半導體基材處理系統(亦即，群集工具(a cluster tool))的處理室來實施至少一部份之本發明方法步驟。在一實施例中，位於基材上的氧化物層係利用沉積該第一氧化物層來形成的，且位於該閘極介電質層上的氧化物層係利用將該閘極介電質層加以氧化而形成的。在另一實施例中，位於基材上的氧化物層係利用沉積該第一氧化物層來形成的，且位於該閘 極介電質層上的氧化物層則係利用沉積該第二氧化物層於該閘極介電質層上來形成的。
在另一實施例中，一種用以在一基材上製造一場效電晶體之閘極介電質的方法，包括以下步驟：從該基材上移除一原生氧化物層及將該基材放置在充滿氮氣或是真空的環境內；在該矽基材上生成一第一熱氧化物層；在該第一熱氧化物層上生成一閘極介電質層；在該閘極介電層層上形成一第二氧化物層；及將具有該第一熱氧化物層及該氧化的閘極介電質層形成於其上之基材加以熱退火。在一實施例中，位於基材上的氧化物層係利用沉積該第一氧化物層來形成的，且位於該閘極介電質層上的氧化物層係利用一含氧電漿將至少一部份該閘極介電質層加以氧化而形成的。在另一實施例中，位於基材上的氧化物層係利用沉積該第一氧化物層來形成的，且位於該閘極介電質層上的氧化物層則係利用形成一熱氧化物層，亦即，沉積該第二氧化物層於該閘極介電質層上，來形成的。
在本發明另一態樣中，揭示一種集積式半導體基材處理系統，用以製造一場效電晶體之閘極介電質。在一實施例中，該系統包括至少一第一反應室，其係用以在一矽基材上生成一熱氧化物層；至少一第二反應室，其係用以沉積一閘極介電層在該熱氧化物層上；至少一第三反應室，其係用以將該閘極介電層氧化；至少一裝載閘(load lock)室；至少一基材傳送室，其係耦接至每一上述反應室及該些裝載閘室；及一控制器，用來管理及監控該處理系統的 操作。
本發明另一態樣揭示一種用以製造一場效電晶體之一閘極介電質之集積式半導體基材處理系統。在一實施例中，該系統包括一反應室，其經設定用來在一矽基材上形成一熱氧化物層，該反應室被設定用來沉積一閘極介電層在該熱氧化物層上且被設定用來形成一熱氧化物層在該閘極介電層上；一去耦合電漿源；一或多裝載閘室；及一控制器，用以管理及監控該處理系統的操作。
本發明是一種用來製造具有超薄閘極介電質(例如，低於約20-30Å)之場效電晶體的閘極介電質的方法。本發明可被用來製造積體半導體元件和電路。
第1圖的流程圖示出依據本發明一實施例來製作一場效電晶體之閘極介電質的方法100。該方法100包括在製造一例示的CMOS場效電晶體的閘極結構期間，於一基材上執行的各種處理步驟。在某些實施例中，這些處理步驟係依據所揭示順序實施。在其他實施例中，這些步驟中的至少兩步驟可同時實施或以不同順序來實施。一些次要步驟及輔助性步驟(例如，在反應室、反應控制步驟等之間移送基材的步驟)，因為已是此領域中習知的，故在此略去不提。
該方法的至少某些部份可以一種集積式半導體基材處理系統(亦即，群集工具)中的處理反應室來實施。這類處 理系統之一為美商應用材料公司出品的CENTURA®集積式處理系統。以下將分別參照第3及4圖來描述一適當的處理系統300與一適當的CVD室400。
第2A-2E圖一起繪示出以第1圖方法於一基材上所製作的一閘極結構的一系列橫截面示意圖。第2A-2E圖中的橫截面圖係關於所執行用以製造該閘極結構的個別處理步驟。第2A-2E圖的影像並未成比例地繪示，且為方便顯示已加以簡化。為能更清楚了解本發明，需同時參閱第1及2A-2E圖。
方法100以步驟102開始並持續進行到步驟104。
在步驟104中，提供一矽基材200(即，200毫米的晶圓、300毫米的晶圓等)，並將其暴露在一種可移除基材表面上一原生氧化物層(SiO2 )的溶液中(第2A圖)。可以方法100來形成電晶體的閘極結構(未示出)。該閘極結構一般係設置在區域220中，位於電晶體源極與汲極區域222和224(以虛線表示)和通道區域226的上方。為簡化圖示起見，第2A圖中只繪示出區域220-226。
在一實施例中，以一種包含氫氟酸(HF)及去離子水(DI water)的溶液(亦即，氫氟酸溶液)來移除層204。在一實施例中，該溶液含有約0.1%至10%(重量%)的HF，且溫度在約20-30℃間。在另一實施例中，該溶液含有約0.5%的HF，且溫度約25℃。步驟104使用一種濕浸泡方式，將基材200浸泡在該溶液中，接著以去離子水清洗，可以使用單一晶圓或是批次晶圓方式為之，包括使用超音波來提高 洗浴的效果。或者，可以該集積式半導體基材處理系統300的一單一基材濕潔淨反應室來實施步驟104。在另一實施例中，可以一種RCA清潔法來移除該層204。一旦完成步驟102後，將基材200放置在一真空裝載閘或經氮氣淨化(nitrogen purged)的環境下。
在步驟106，於基材200上生長一層熱氧化物(SiO2 )層206(第2B圖)。一般來說，該層206的厚度在約2-40 Å間。在另一實施例中，該該層206的厚度在約6-10 Å間。可使用該集積式半導體基材處理系統300之反應室，例如，RADIANCE®快速熱處理(RTP)反應室、去耦合電漿氧化(DPO)反應室、或電漿強化化學氣相沉積室(PECVD)來執行步驟106。RADIANCE®快速熱處理(RTP)反應室可購自美商應用材料公司。
在一實施例中，於步驟106中，係以一RTP反應室來生長該層206，其係利用供應約05-10 slm的氧氣，同時將基材溫度維持在750-850℃、反應室壓力維持在0.1-50 torr下。處理期間可以在約5-30秒。在一實施例中，係以約2 slm的速度來供應氧氣，同時將基材溫度維持在約800℃、反應室壓力維持在約2 torr。
在另一實施例中，藉由以約1-10 slm的速度供應一氧化二氮(N2 O)、以約10-500 slm的速度供應氫氣(亦即，N2 O：H2 的流速介於約2：1至1000：1間)，同時將基材溫度維持在750-850℃間，而於一RTP反應室中生長該層206。此外，在步驟106中，反應室壓力係維持在0.5-20 torr間。 處理期間可以在約5-60秒。一特定處理配方包括以約4.9 slm的速度供應一氧化二氮(N2 O)、以約50 sccm的速度供應氫氣(亦即，N2 O：H2 的流速介於約98：1間)，同時將基材溫度維持在800℃間。
在另一實施例中，可使用適合製造低能量電漿的製程室，例如，DPO反應室，來執行步驟106。低能量電漿有助於控制基材表面和/或層的反應。舉例來說，可使用一準-遠端電漿源、一誘導式電漿源、和/或一RLSA源及其他電漿源等等，來產生電漿。在其他實施例中，可以連續波(CW)和/或脈衝式的微波能量之類的來源，例如磁控管或RLSA微波源，來形成該層206。
在一實施例中，可藉由在一DPO反應室內將基材200暴露在一電漿中的方式來生成該層206，其中該電漿包含至少下列一者：O2 、NO、N2 O等類似物。此外，該電漿還可選擇性地包含N2 和/或一選擇性包含的惰性氣體(例如，氬氣、氦氣等)。
在一實施例中，可於一DPO反應室中，以約10-2000 sccm的速度提供O2 ，並將製程室壓維持在約5-1000 mTorr間的方式，來形成該層206。可使用高達3-5 kW的連續波(continuous wave,CW)或脈衝式電漿源，於例如13.56 MHz的頻率下，來激發該無線電波(RF)電漿。脈衝期間，RF電力尖峰可以在約10-3000瓦間，頻率在約2-100 kHz間，且其功率週期(duty cycle)在約2-50%間，並執行製程約1-180秒。在一實施例中，以約200 sccm的速度提供O2 ， 在約10 kHz、5%功率週期下將約500瓦尖峰RF電力加以脈衝並施加至一誘導式電漿源，並將製程室溫度維持在約25℃且製程室壓維持在約40-80 mTorr間，製程持續約15-60秒。
在進一步實施例中，可使用第4圖所揭示的PE-CVD室來沉積一熱氧化矽層206。經由一上方氣體注射器435將氧氣、一氧化氮(NO)、二氧化氮(N2 O)或其之類似物注入，相反的，矽烷(SiH4 )則係經由一下方氣體注射器注入。也可使用本文其他實施例中所揭示的矽源。經由上方氣體注射器435注入的氣體可由一誘導式耦合電漿加以激發。例如，氧氣可以13.56MHz的無線電頻率(RF)電漿加以激發。電將源可於脈衝方式或CW模式下運作。若是在脈衝式RF電漿模式下，尖峰電力可在約10~3000瓦間。若是在CW電漿模式下，尖峰電力可在約10~1000瓦間。
可利用提供約10~2000 sccm的氧氣、約20℃~500℃間的平台溫度及約1~50 mTorr的製程室壓來成長該層206。
在一選擇性實施的步驟107中，將該第一氧化物層206加以氮化。該層206可以在一電漿處理中或一熱處理中加以氮化。步驟107可在該層206的一上方部位形成一由氮化材料構成的子層207(第2C圖)。該氮化子層207的厚度一般約在0.5-5Å間，較佳是約1-3 Å間。
在一實施例中，該層206是被暴露在一含氮電漿中。在一實施例中，該電漿包含氮氣，且可選擇性地包含一或多種其他選擇性添加的惰性氣體(例如，氬氣、氦氣等類似 氣體)。可使用諸如該集積式處理系統300中的去耦合電漿碳化(DPN)電漿反應器，來實施該步驟107。
在一實施例中，可藉由提供流速約10-2000 sccm的氮氣、約20-500℃間之基材平台溫度、及約5-100 mTorr間之反應室壓力，而在一DPN反應室中形成該子層207。使用高達約3-5 kW之一連續波(CW)或脈衝式電漿電力，於13.56 MHz頻率下，激發無線電波頻率(RF)電漿。在脈衝期間，一般將RF電力尖峰射在約10-3000瓦間，頻率在約2-100 kHz間，且其功率週期(duty cycle)在約2-50%間，並執行製程約1-180秒。在一實施例中，以約200 sccm的速度提供N2 ，在約10 kHz、5%功率週期下將約1000瓦尖峰RF電力加以脈衝並施加至一誘導式電漿源，並將製程室溫度維持在約25℃且製程室壓維持在約40-80 mTorr間，製程持續約15-60秒。可使用一準遠端電漿源(a quasi-remote plasma source)、一誘導式電漿源、及一圓極化俓向線縫隙天線(radial line slotted antenna,RLSA)源等等其他電漿源來產生電漿。在其他實施例中，可使用CW和/或脈衝式微波電力來形成該子層207。
在一選擇性實施的步驟107中，在一RTP反應室中，於高溫下將該熱氧化物層206暴露在一NH3 ，或一由NH3 及N2 組成的混合氣體中，或一或多種諸如氦氣、氬氣等類似氣體下，而形成氮化材料製成的子層207。
在一實施例中，以約5-1000 sccm的速度提供NH3 ，同時將基材溫度維持在約700-1000℃間，且製程室壓維持在 約0.1-10 Torr間，而於一RTP反應室內形成該子層207。製程可持續約5-120秒。
在步驟108中，一閘極介電層208被沉積在該熱氧化物層206上方(第2D圖)。該層208可由氮化矽(Si3 N4 )沉積至約2-20Å的厚度而成，或是由諸如氧化鉿(HfO2 )、矽酸鉿(Hfx Siy O，其中x及y為整數)或其之組合等類的高k介電材料，沉積至約10-60Å的厚度而成。可使用該集積式處理系統300內，諸如一化學氣相沉積(CVD)反應室或一原子層沉積(ALD)反應室之類的CVD反應室或ALD反應室來實施步驟108。一種適當的CVD反應室為美商應用材料公司出品的XGen CVD反應室。
在一實施例中，使用一CVD反應室，該閘極介電層208可包含有氮化矽(Si3 N4 )且可利用提供流速在約100-1000 sccm間之氨氣(NH3 )、流速在約1-100 sccm間之矽烷(SiH4 )(亦即，NH3 ：SiH4 的流速比在1：1至1000：1間)、及流速在約10-1000 sccm間之氮氣，同時維持基材平台溫度在約400-750℃，且反應室壓在約0.1-50 torr間的方式來形成。此製程可實施約30-180秒。在一實施例中，提供約500 sccm的NH3 、約10 sccm的SiH4 (亦即，NH3 ：SiH4 的流速比約為50：1)、約25 sccm的N2 ，同時維持溫度在約600℃且壓力在約5 torr。其他可用來取代矽烷(SiH4 )的矽源氣體或化學物包括二矽烷(Si2 H6 )、二氯矽烷(DSC)、三氯矽烷(TCS)、四氯矽烷、或六氯二矽烷(HCD)。
在另一實施例中，該閘極介電層208可包含氧化鉿或 矽酸鉿且可使用一CVD或一ALD製程來沉積。該氧化鉿或矽酸鉿閘極介電層208可使用鉿或矽的金屬-有機前驅物或無機前驅物，與一氧化劑(包含至少下列一種：臭氧、水或遠端電漿氧自由基)來形成。
在一實施例中，在第4圖所揭示的PE-CVD室中於氮化矽(Si3 N4 )層上形成該介電層。經由一上方氣體注射器將氨氣(NH3 )和/或氧氣注入，至於矽烷(SiH4 )則係經由一下方氣體注射器注入。依據一實施例，係以約100~1000 sccm的速度注入NH3 ，並以約1~100 sccm的速度注入矽烷，亦即，流速比在1：1至1000：1之間。此外，可以約10~1000 sccm的速度注入N2 。將基材平台溫溫度維持在約400℃~750℃間且製程室壓維持在約1~50 mTorr間，一般係介於約1~20 mTorr間。或者，也可使用本文其他實施例中所揭示的矽源。
NH3 和/或N2 可被誘導式耦合電漿所激發。舉例來說，該氨氣(NH3 )和/或氮氣係為13.56MHz的無線電頻率(RF)電漿加以激發。電將源可於脈衝方式或CW模式下運作。若是在脈衝式RF電漿模式下，尖峰電力可在約10~3000瓦間。若是在CW電漿模式下，尖峰電力可在約10~1000瓦間。
在步驟110中，將該閘極介電層208暴露在含氧電漿下而氧化。詳言之，步驟110會在層208的一上方部份形成一由氧化材料組成的子層210(參見第2E圖)。該氧化的子層210的厚度一般在約0.2~10Å間，較佳是在約0.5~5 Å 間。在一實施例中，電漿含有至少一種下列物質：氧氣、一氧化氮(NO)、一氧化二氮(N2 O)等類似物；且可包含額外添加的氮氣和/或額外添加的惰性氣體(例如，氬氣、氦氣等類似氣體)。可以一種適宜產生低能量電漿的製程室來實施步驟110。該低能量的電漿可幫助控制該基材和/或該層表面處的反應。舉例來說，可使用一準遠端電漿源、一誘導式電漿源、及一圓極化俓向線縫隙天線(radial line slotted antenna,RLSA)源等等其他電漿源來產生電漿。在其他實施例中，可使用諸如磁控管或RLSA微波源之類的CW和/或脈衝式微波電力來形成該子層210。在一實施例中，可使用諸如該集積式處理系統300中的去耦合電漿碳化(DPN)電漿反應室，來實施該步驟110。
可利用提供流速約10-2000 sccm間的氧氣，來形成該子層210。該氧氣可被選擇性地混入N2 和/或氦氣和/或氬氣。基材平台溫度被維持在約20-500℃間，反應室內的壓力維持在約5-1000 mTorr間。RF電漿係在13.56 MHz的頻率下以高達約3-5 kW的連續波(CW)或脈衝式電力將其激發。在脈衝期間，一般將RF電力尖峰射在約10-3000瓦間，頻率在約2-100 kHz間，且其功率週期(duty cycle)在約2-50%間，並執行製程約1-180秒。在一實施例中，以約200 sccm的速度提供O2 ，在約10 kHz、5%功率週期下將約1000瓦尖峰RF電力加以脈衝並施加至一誘導式電漿源，並將製程室溫度維持在約25℃且製程室壓維持在約40 mTorr，製程持續約30秒。
在一實施例中，額外的或選擇性地，將閘極介電層氧化，使氮化矽介電層208上成長一層氧化矽層。以第4圖所述PE-CVD室沉積一層熱氧化矽層。經由一上方氣體注射器435將氧氣、一氧化氮(NO)、二氧化氮(N2 O)或其之類似物注入並以誘導式耦合電漿加以激發，至於矽源(如，矽烷)則係經由一下方氣體注射器注入。也可使用本文其他實施例中所揭示的矽源。電漿源可於脈衝方式或CW模式下運作。氮化矽層上方的氧化矽層的沉積厚度在2~20Å間，且可利用提供約10~2000 sccm的氧氣、將基材平台溫度維持在約20~500℃間及將製程室壓維持在約1~50 mTorr間來生成該氧化矽層。氧氣可以13.56MHz的無線電頻率(RF)電漿加以激發。若是在脈衝式RF電漿模式下，尖峰電力可在約10~3000瓦間。若是在CW電漿模式下，尖峰電力可在約10~1000瓦間。
依據關於步驟106、08及110的實施例，其係在第4圖中的PE-CVD室中實施，且該堆疊的SiO2 、Si3 N4 和SiO2 可以相同方式沉積。用來沉積該堆疊層的步驟可選擇性地在有電漿輔助下執行。電漿強化處理使得製程可在較低溫下運作。
製程室的配置包括低壓排空單元、電漿源410及用於成長薄層的下方製程室主體420，使得可熱沉積由該SiO2 、Si3 N4 和SiO2 組成的堆疊層。
在步驟112中，將該閘極介電層208及介於該層206與基材200間的氧化物/矽界面加以退火。步驟112可改善 層206及210漏電流降低的情形，以及提高通道區域226中的荷電載子的遷移力(第2A圖)，以及改善氧化物/矽界面的可靠性。可使用一適當的熱硬化室來實施步驟112，例如該集積式處理系統300中的一RTP反應室(例如，RADIANCE®或RTP XE+)，或是一單一基材或是批次烤爐(batch furnace)。
在一實施例中，可藉由提供至少一種下列物質：約2-5000 sccm間的氧氣及約100-5000 sccm間的NO(此兩種氣體的任一種可選擇性的混有N2 )，同時將基材表面溫度維持在約800-1100℃，且壓力維持在0.1-50 torr間來執行該硬化步驟112。該製程可實施約5-180秒。在一實施例中，以約500 sccm的流速來提供氧氣，同時將基材表面溫度維持在約1000℃，且壓力維持在0.1 tor一段約15秒的期間。在另一實施例中，係以約500 sccm的速度來供應NO，同時將基材表面溫度維持在約1000℃，且壓力維持在0.5 tor一段約15秒的期間。
待完成步驟112之後，在步驟114中，方法100即已結束。在製造積體電路時，方法100的優點是會形成可代表漏電流之高電阻路徑的超薄閘極介電層，並促進場效電晶體通道區域中之荷電載子的高遷移力。
第3圖為一例示可用來實施第1圖中部份方法100之CENTURA®集積式半導體基材處理系統300(即，群集工具)的示意圖。該系統300的此一特定實例乃係為了闡述本發明概念而繪示，且不應用來限制本發明範疇。方法100也 可使用其他半導體基材處理系統和/或反應室來實施，並不限於所示的基材處理系統300實例。
此集積式半導體基材處理系統300包括真空裝載閘室322，真空氣室328(其具有連接至一基材承座334的機器人330)，耦接至該氣室328的多個處理模組310、312、314、316及318，輸入/輸出模組302，選擇性安裝的度量模組326及系統控制器340。該真空裝載閘室322是用作為可讓基材卡匣停靠的停靠站並可保護該氣室328不受大氣污染物的影響。機器人330可在裝載閘室322與處理模組間傳送基材。所繪示機器人例僅為供闡述本發明用的例舉實例，本發明範疇並非僅限於此。該輸入/輸出模組302包含有助於在一工廠界面324、度量模組326及裝載閘室322三者間交換基材卡匣的至少一前端開口一體槽(FOUP)306(圖中繪出兩FOUP 306)。
該系統控制器340一般包括中央處理單元(CPU)342、記憶體344、及支持電路346，其被耦接至該集積式基材處理系統300並可控制該系統300的多個模組及設備，以及可收集來自個別模組的回饋資料以使系統300的效能趨於最佳狀態。操作時，控制器340可使用該系統300之一直接控制模組與設備，或者，與這些模組與設備相連的管理者電腦(或控制器)。
該些處理模組310、312、314、316及318中至少一者可為RTP反應室(例如，RADIANCE®反應室)、PECVD反應室、CVD反應室(例如，XGen反應室)、ALD反應室、 DPN反應室和/或其他適於執行第1圖所述製程的反應室。可用來執行本發明方法之一適當組合的系統300會包括兩個裝載閘室322、兩個RTP模組310及312、一個ALD模組314、一CVD模組316、一DPN模組318、一度量模組326(其包含一測量工具304及機器人308和320)、及輸入/輸出模組302(其包含兩個FOUP 306)。也可使用其他組裝形式的系統300來執行本發明。
第4圖示出一例示的PE-CVD室400的示意圖。在下方製程室主體420的處理區402上方設有一去耦合電漿氮化(DNP)電漿源410。製程室壁圍繞該處理區402。基板401位在該平台424上。該平台424有一支撐柱450，其包郭括數個接點可連接到該平台之雙區加熱器上。有關該平台之雙區加熱器的詳細內容可參見2001年10月19日提申之美國專利第6,646,235號中，其全文併入作為參考。
多個線圈412螺旋圍繞該電漿源之圓頂上方壁的垂直軸排列。該些線圈412位在電極板418上方並符合圓頂外形，該些線圈412的一端連接到一RF源462，且其相反的另一端則係接地。依據一實施例，可在該RF源462與該些線圈412之間設置一RF匹配電路464。
可操作該RF源462以便於13.56MHz的無線電頻率(RF)下來提供RF電流到該些線圈412。可施加約0~3000瓦的電力。RF場與被注入到氣體注射器435的氮氣或氧氣耦接。氣體注射器435可注入N2 、NH3 等類似氣體。此外，當所欲生成的為氧化物層時，該氣體注射器435也可注入 O2 、NO或N2 O。RF源可於脈衝方式或CW模式下運作。
由該氣體注射器435所注入且被RF電漿加以游離的氣體，以及由沉積氣體注入器430的氣體，會在處理區402和/或加熱的晶圓表面上反應，以熱沉積出一層於基材上。
渦輪幫浦440經由閥442和排氣口443而連接到製程室主體420。在一實施例中，該閥442可以是一種節流閥。渦輪幫浦440可降低製程室中的壓力到一適合在基材401上生長層的程度。依據一實施例，可將一處理區中的壓力控制在低於約30 mTorr下，較佳是在約1~20 mTorr間。
上述實施例容許以激發的N2 、NH3 、O2 、NO或N2 O來生長矽層。氮氣和/或氨氣係用來沉積氮化矽膜。O2 、NO和/或N2 O係用來沉積氧化矽層。由上方氣體注射器引入的氣體可在與矽源混合前，先以一種脈衝式RF誘導源加以激發。因此，可在低溫下實施電漿強化的CVD製程。
可包括在製程室400中的其他製程室細節可參照2003年6月12日提申之美國專利第6,831,021號，其全文併入作為參考。
本發明可使用其他製程來實施，只要依據本發明說明書揭示內容恰當調整製程參數來達到欲求目的。雖然前述內容係針對一場效電晶體而言，但積體電路中其他元件及結構的製造亦可受惠於本發明。
雖然本發明已用本發明之實施例被明確地示出及說明，但熟習此技藝者將可瞭解的是上述在形式及細節上之其它形式與細節上的改變可在不偏離本發明的範圍及精神 下被達成。因此，本發明並不侷限於所示及所說明的特定形式與細節，而是落在由以下的中請專利範圍所界定的範圍內。
100‧‧‧方法
102、104、106、107、108、109、110、112、114‧‧‧步驟
200、401‧‧‧基材
204‧‧‧原生氧化物層
206‧‧‧熱氧化物層
207、210‧‧‧子層
208‧‧‧閘極介電層
220‧‧‧區域
222‧‧‧源極區域
224‧‧‧汲極區域
226‧‧‧通道區域
300‧‧‧處理系統
302‧‧‧輸入/輸出模組
306‧‧‧前端開口一體槽(FOUP)
310、312、314、316、318‧‧‧處理模組
322‧‧‧真空裝載閘室
324‧‧‧工廠界面
326‧‧‧度量模組
328‧‧‧氣室
330‧‧‧機器人
334‧‧‧基材承座
340‧‧‧系統控制器
342‧‧‧CPU(中央處理器)
344‧‧‧記憶體
346‧‧‧支持電路
400‧‧‧PE-CVD室
402‧‧‧處理區
410‧‧‧電漿源
412‧‧‧線圈
418‧‧‧電極板
420‧‧‧下方製程室主體
422‧‧‧室壁
424‧‧‧基材平台
430‧‧‧沉積氣體注射器
435‧‧‧上方氣體注射器
440‧‧‧渦輪幫浦
442‧‧‧閥
443‧‧‧排氣口
462‧‧‧RF源
464‧‧‧RF匹配電路
第1圖繪示出一流程圖，其示出依據本發明一實施例來製作一場效電晶體之閘極介電質的方法；第2A-2E圖一起繪示出以第1圖方法於一基材上所製作的一閘極結構的一系列橫截面示意圖；第3圖為一例示可用來實施本發明部份方法之集積式半導體基材處理系統的示意圖。
第4圖為一例示可用來實施本發明部份方法之集積式半導體基材處理室的示意圖。

Claims (19)

  1. 一種用以製造場效電晶體之閘極介電質的方法，其依序包含以下步驟：(a)提供一矽基材；(b)在該矽基材上形成一第一氧化物層；(c)在該第一氧化物層上形成一閘極介電層，該閘極介電層的厚度為約10至60 Å，其中該閘極介電層包含氧化鉿、矽酸鉿、或其組合；(d)在該閘極介電層上形成一第二氧化物層；及，之後(e)將該閘極介電層、該第一氧化物層及位於該第一氧化物層與該矽基材間之一界面加以退火(annealing)。
  2. 如申請專利範圍第1項所述之方法，更包含：從步驟(b)至步驟(d)，將該矽基材維持在一單一製程室中。
  3. 如申請專利範圍第1項所述之方法，其中步驟(b)更包含：將該第一氧化物層沉積達約2-10Å間的厚度。
  4. 如申請專利範圍第1項所述之方法，其中步驟(b)更包含：將該第一氧化物層暴露在一種由去耦合電漿源所產生 的電漿下，該電漿包含以下氣體中之至少一種：氧氣、一氧化氮(nitric oxide)或一氧化二氮(nitrous oxide)。
  5. 如申請專利範圍第1項所述之方法，其中步驟(b)更包含：將該第一氧化物層氮化。
  6. 如申請專利範圍第5項所述之方法，其中該氮化步驟更包含：在該第一氧化物層中創造出一厚度約0.5-3Å間的氮化材料子層。
  7. 如申請專利範圍第5項所述之方法，其中將該第一氧化物層氮化的步驟包含：將該第一氧化物層暴露在含氮電漿下。
  8. 如申請專利範圍第1項所述之方法，更包含：從氮化矽來形成厚度約2-10Å的該閘極介電層。
  9. 如申請專利範圍第1項所述之方法，其中步驟(c)更包含：在一電漿強化製程中來形成該閘極介電層。
  10. 如申請專利範圍第1項所述之方法，其中該第二氧化物層的厚度在約2-10Å間。
  11. 如申請專利範圍第1項所述之方法，其中步驟(d)更包含：使用一低能量電漿源來形成一電漿。
  12. 如申請專利範圍第1項所述之方法，其中步驟(e)更包含：在一快速熱處理室或一爐中將該基材加以熱退火。
  13. 如申請專利範圍第1項所述之方法，其中步驟(d)更包含：透過將該第二氧化物層沉積在該閘極介電層上，而形成該第二氧化物層。
  14. 一種在基材上製造場效電晶體之閘極介電質的方法，其包含以下步驟：(a)將該基材置於一氮氣淨化環境或真空環境下；(b)在該基材上形成一第一熱氧化物層，該第一熱氧化物層之厚度介於約2至10 Å之間；(c)在該第一熱氧化物層上形成一閘極介電層；(d)在該閘極介電層上形成一第二熱氧化物層；及 (e)將具有該第一熱氧化物層及形成於其上之該氧化的閘極介電層之該基材加以熱退火(thermal annealing)。
  15. 如申請專利範圍第14項所述之方法，更包括：在實施步驟(c)之前，將該第一熱氧化物層氮化。
  16. 如申請專利範圍第14項所述之方法，更包含：在實施步驟(d)之前，將該閘極介電層氮化。
  17. 一種用以製造場效電晶體之閘極介電質的集積式半導體基材處理系統，包含：一反應室，其經設定用以在一矽基材上形成一第一熱氧化物層，其中該第一熱氧化物層之厚度介於約2至10 Å之間，該反應室係經設定用以沉積一閘極介電層在該第一熱氧化物層上且經設定用以形成一第二熱氧化物層在該閘極介電層上；一去耦合電漿源；一或多個裝載閘室(load lock chamber)；至少一個基材傳送室，其耦接至該反應室及該裝載閘室；及一控制器，用於管理及監控該處理系統的運作。
  18. 如申請專利範圍第17項所述之集積式半導體基材 處理系統，更包含：一上方氣體注入器與一下方氣體注入器。
  19. 如申請專利範圍第18項所述之集積式半導體基材處理系統，其中該下方氣體注入器係設置在該去耦合電漿源下方，且該上方氣體注入器係設置在該去耦合電漿源上方。
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