ATE534995T1 - Mehrebenen-zellenzugangspuffer mit zweifacher funktion - Google Patents
Mehrebenen-zellenzugangspuffer mit zweifacher funktionInfo
- Publication number
- ATE534995T1 ATE534995T1 AT08748199T AT08748199T ATE534995T1 AT E534995 T1 ATE534995 T1 AT E534995T1 AT 08748199 T AT08748199 T AT 08748199T AT 08748199 T AT08748199 T AT 08748199T AT E534995 T1 ATE534995 T1 AT E534995T1
- Authority
- AT
- Austria
- Prior art keywords
- latch
- access buffer
- level cell
- dual function
- cell access
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
- G11C11/5628—Programming or writing circuits; Data input circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
- G11C2211/564—Miscellaneous aspects
- G11C2211/5642—Multilevel memory with buffers, latches, registers at input or output
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
- G11C2211/564—Miscellaneous aspects
- G11C2211/5647—Multilevel memory with bit inversion arrangement
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Read Only Memory (AREA)
- Static Random-Access Memory (AREA)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US91615107P | 2007-05-04 | 2007-05-04 | |
US11/966,152 US7577029B2 (en) | 2007-05-04 | 2007-12-28 | Multi-level cell access buffer with dual function |
PCT/CA2008/000797 WO2008134858A1 (en) | 2007-05-04 | 2008-04-28 | Multi-level cell access buffer with dual function |
Publications (1)
Publication Number | Publication Date |
---|---|
ATE534995T1 true ATE534995T1 (de) | 2011-12-15 |
Family
ID=39939398
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AT08748199T ATE534995T1 (de) | 2007-05-04 | 2008-04-28 | Mehrebenen-zellenzugangspuffer mit zweifacher funktion |
Country Status (8)
Country | Link |
---|---|
US (4) | US7577029B2 (de) |
EP (1) | EP2150958B1 (de) |
JP (2) | JP5285064B2 (de) |
KR (2) | KR101453588B1 (de) |
CN (1) | CN101720484B (de) |
AT (1) | ATE534995T1 (de) |
TW (2) | TW200912950A (de) |
WO (1) | WO2008134858A1 (de) |
Families Citing this family (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7577029B2 (en) * | 2007-05-04 | 2009-08-18 | Mosaid Technologies Incorporated | Multi-level cell access buffer with dual function |
US7920430B2 (en) * | 2008-07-01 | 2011-04-05 | Qimonda Ag | Integrated circuits and methods for operating the same using a plurality of buffer circuits in an access operation |
KR101024154B1 (ko) * | 2009-02-02 | 2011-03-22 | 주식회사 하이닉스반도체 | 페이지 버퍼 회로 |
KR101082614B1 (ko) * | 2010-07-09 | 2011-11-10 | 주식회사 하이닉스반도체 | 반도체 메모리 장치 |
KR20120045202A (ko) * | 2010-10-29 | 2012-05-09 | 에스케이하이닉스 주식회사 | 비휘발성 메모리 장치 및 프로그램 방법 |
US8630118B2 (en) | 2011-11-09 | 2014-01-14 | Sandisk Technologies Inc. | Defective word line detection |
US8842476B2 (en) * | 2011-11-09 | 2014-09-23 | Sandisk Technologies Inc. | Erratic program detection for non-volatile storage |
KR102163872B1 (ko) | 2013-08-09 | 2020-10-13 | 삼성전자 주식회사 | 멀티 비트 메모리 장치, 그것의 온칩 버퍼 프로그램 방법 및 멀티 비트 메모리 시스템 |
WO2015025357A1 (ja) * | 2013-08-19 | 2015-02-26 | 株式会社 東芝 | メモリシステム |
JP5678151B1 (ja) * | 2013-09-18 | 2015-02-25 | 力晶科技股▲ふん▼有限公司 | 不揮発性半導体記憶装置とその制御方法 |
US20150199282A1 (en) * | 2014-01-16 | 2015-07-16 | Storart Technology Co., Ltd. | Scramble random seed prediction method with storage device built-in data copy back procedure |
CN106575525B (zh) * | 2014-08-28 | 2020-09-25 | 东芝存储器株式会社 | 半导体存储装置 |
KR102282196B1 (ko) | 2015-04-28 | 2021-07-27 | 삼성전자 주식회사 | 비휘발성 메모리 장치, 메모리 시스템 및 그것의 동작 방법 |
JP2017157257A (ja) * | 2016-03-01 | 2017-09-07 | 東芝メモリ株式会社 | 半導体記憶装置及びメモリシステム |
JP6439026B1 (ja) | 2017-11-17 | 2018-12-19 | ウィンボンド エレクトロニクス コーポレーション | 半導体記憶装置 |
KR102653843B1 (ko) * | 2018-04-19 | 2024-04-02 | 에스케이하이닉스 주식회사 | 데이터 저장 장치 및 이의 리드 디스터번스 방지 방법, 이를 이용한 스토리지 시스템 |
US11328752B2 (en) * | 2020-05-20 | 2022-05-10 | Silicon Storage Technology, Inc. | Self-timed sensing architecture for a non-volatile memory system |
Family Cites Families (71)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60252979A (ja) * | 1984-05-30 | 1985-12-13 | Oki Electric Ind Co Ltd | Cmos入出力回路 |
KR930000869B1 (ko) | 1989-11-30 | 1993-02-08 | 삼성전자 주식회사 | 페이지 소거 가능한 플래쉬형 이이피롬 장치 |
US6230233B1 (en) | 1991-09-13 | 2001-05-08 | Sandisk Corporation | Wear leveling techniques for flash EEPROM systems |
US5257223A (en) * | 1991-11-13 | 1993-10-26 | Hewlett-Packard Company | Flip-flop circuit with controllable copying between slave and scan latches |
KR950000273B1 (ko) | 1992-02-21 | 1995-01-12 | 삼성전자 주식회사 | 불휘발성 반도체 메모리장치 및 그 최적화 기입방법 |
KR960000616B1 (ko) | 1993-01-13 | 1996-01-10 | 삼성전자주식회사 | 불휘발성 반도체 메모리 장치 |
JP3202498B2 (ja) * | 1994-03-15 | 2001-08-27 | 株式会社東芝 | 半導体記憶装置 |
JP3177094B2 (ja) * | 1994-05-31 | 2001-06-18 | 富士通株式会社 | 半導体記憶装置 |
US5497354A (en) | 1994-06-02 | 1996-03-05 | Intel Corporation | Bit map addressing schemes for flash memory |
KR100220675B1 (ko) * | 1994-10-31 | 1999-09-15 | 전주범 | 투사형 화상표시장치 |
KR0142367B1 (ko) | 1995-02-04 | 1998-07-15 | 김광호 | 열 리던던씨를 가지는 불휘발성 반도체 메모리의 소거 검증회로 |
US5835935A (en) | 1995-09-13 | 1998-11-10 | Lexar Media, Inc. | Method of and architecture for controlling system data with automatic wear leveling in a semiconductor non-volatile mass storage memory |
JP3252678B2 (ja) * | 1995-10-20 | 2002-02-04 | 日本電気株式会社 | 同期式半導体メモリ |
KR0169418B1 (ko) | 1995-10-30 | 1999-02-01 | 김광호 | 페이지 소거시 데이터의 자기 보존회로를 가지는 불휘발성 반도체 메모리 |
US5606522A (en) * | 1995-12-20 | 1997-02-25 | Samsung Electronics Co., Ltd. | Non-volatile analog memory |
JP3592887B2 (ja) * | 1997-04-30 | 2004-11-24 | 株式会社東芝 | 不揮発性半導体記憶装置 |
US5937425A (en) | 1997-10-16 | 1999-08-10 | M-Systems Flash Disk Pioneers Ltd. | Flash file system optimized for page-mode flash technologies |
US6151257A (en) * | 1998-01-26 | 2000-11-21 | Intel Corporation | Apparatus for receiving/transmitting signals in an input/output pad buffer cell |
US6118705A (en) | 1998-03-13 | 2000-09-12 | Atmel Corporation | Page mode erase in a flash memory array |
US6359810B1 (en) | 1998-03-13 | 2002-03-19 | Atmel Corporation | Page mode erase in a flash memory array |
US5995417A (en) | 1998-10-20 | 1999-11-30 | Advanced Micro Devices, Inc. | Scheme for page erase and erase verify in a non-volatile memory array |
DE60043651D1 (de) | 1999-02-01 | 2010-02-25 | Renesas Tech Corp | Integrierte halbleiterschaltung und nichtflüchtiges speicherelement |
KR100347866B1 (ko) | 1999-03-08 | 2002-08-09 | 삼성전자 주식회사 | 낸드 플래시 메모리 장치 |
KR100295598B1 (ko) | 1999-05-03 | 2001-07-12 | 윤종용 | 반도체 메모리 장치 및 그 장치의 디코더 |
US6552580B2 (en) * | 1999-05-24 | 2003-04-22 | Level One Communications Inc. | Bias technique for operating point control in multistage circuits |
US6058059A (en) * | 1999-08-30 | 2000-05-02 | United Microelectronics Corp. | Sense/output circuit for a semiconductor memory device |
JP2001093288A (ja) * | 1999-09-20 | 2001-04-06 | Toshiba Corp | 不揮発性半導体記憶装置 |
US6111787A (en) | 1999-10-19 | 2000-08-29 | Advanced Micro Devices, Inc. | Address transistion detect timing architecture for a simultaneous operation flash memory device |
US7082056B2 (en) | 2004-03-12 | 2006-07-25 | Super Talent Electronics, Inc. | Flash memory device and architecture with multi level cells |
JP4944301B2 (ja) * | 2000-02-01 | 2012-05-30 | パナソニック株式会社 | 光電子装置およびその製造方法 |
JP3983969B2 (ja) * | 2000-03-08 | 2007-09-26 | 株式会社東芝 | 不揮発性半導体記憶装置 |
FR2816751A1 (fr) | 2000-11-15 | 2002-05-17 | St Microelectronics Sa | Memoire flash effacable par page |
US6763424B2 (en) | 2001-01-19 | 2004-07-13 | Sandisk Corporation | Partial block data programming and reading operations in a non-volatile memory |
US6538923B1 (en) * | 2001-02-26 | 2003-03-25 | Advanced Micro Devices, Inc. | Staircase program verify for multi-level cell flash memory designs |
US6888583B2 (en) * | 2001-05-21 | 2005-05-03 | Brillian Corporation | Method and apparatus for adjusted DC offset potential in a liquid crystal display (LCD) device |
US6732221B2 (en) | 2001-06-01 | 2004-05-04 | M-Systems Flash Disk Pioneers Ltd | Wear leveling of static areas in flash memory |
US6522580B2 (en) | 2001-06-27 | 2003-02-18 | Sandisk Corporation | Operating techniques for reducing effects of coupling between storage elements of a non-volatile memory operated in multiple data states |
JP3993035B2 (ja) * | 2001-07-19 | 2007-10-17 | 松下電器産業株式会社 | データ記録方法、記録媒体、および再生装置 |
US7042770B2 (en) * | 2001-07-23 | 2006-05-09 | Samsung Electronics Co., Ltd. | Memory devices with page buffer having dual registers and method of using the same |
US6671204B2 (en) | 2001-07-23 | 2003-12-30 | Samsung Electronics Co., Ltd. | Nonvolatile memory device with page buffer having dual registers and methods of using the same |
US6456528B1 (en) | 2001-09-17 | 2002-09-24 | Sandisk Corporation | Selective operation of a multi-state non-volatile memory system in a binary mode |
KR100454119B1 (ko) | 2001-10-24 | 2004-10-26 | 삼성전자주식회사 | 캐쉬 기능을 갖는 불 휘발성 반도체 메모리 장치 및 그것의 프로그램, 읽기, 그리고 페이지 카피백 방법들 |
KR100471167B1 (ko) * | 2002-05-13 | 2005-03-08 | 삼성전자주식회사 | 프로그램된 메모리 셀들을 검증하기 위한 페이지 버퍼를구비한 반도체 메모리 장치 |
JP2004087027A (ja) * | 2002-08-28 | 2004-03-18 | Sanyo Electric Co Ltd | アクセス回路 |
JP4270832B2 (ja) | 2002-09-26 | 2009-06-03 | 株式会社東芝 | 不揮発性半導体メモリ |
ITMI20022240A1 (it) | 2002-10-22 | 2004-04-23 | Atmel Corp | Architettura di memoria flash con cancellazione di modo |
US6847550B2 (en) | 2002-10-25 | 2005-01-25 | Nexflash Technologies, Inc. | Nonvolatile semiconductor memory having three-level memory cells and program and read mapping circuits therefor |
JP3920768B2 (ja) * | 2002-12-26 | 2007-05-30 | 株式会社東芝 | 不揮発性半導体メモリ |
KR100514415B1 (ko) | 2003-01-22 | 2005-09-09 | 주식회사 하이닉스반도체 | 낸드 플래시 메모리의 페이지 버퍼 |
US6788589B2 (en) * | 2003-01-22 | 2004-09-07 | Promos Technologies Inc. | Programmable latch circuit inserted into write data path of an integrated circuit memory |
KR100562134B1 (ko) | 2004-01-09 | 2006-03-21 | 주식회사 하이닉스반도체 | 플래시 메모리 소자의 페이지 버퍼 |
KR100575336B1 (ko) | 2004-04-20 | 2006-05-02 | 에스티마이크로일렉트로닉스 엔.브이. | 듀얼 레지스터를 갖는 페이지 버퍼, 이를 구비한 반도체메모리 장치 및 그의 프로그램 방법 |
KR100567912B1 (ko) | 2004-05-28 | 2006-04-05 | 주식회사 하이닉스반도체 | 플래시 메모리 장치의 페이지 버퍼 및 이를 이용한 데이터프로그램 방법 |
KR100609568B1 (ko) | 2004-07-15 | 2006-08-08 | 에스티마이크로일렉트로닉스 엔.브이. | 비휘발성 메모리 장치의 페이지 버퍼 및 이를 이용한프로그램 방법과 독출 방법 |
KR100642911B1 (ko) | 2004-11-30 | 2006-11-08 | 주식회사 하이닉스반도체 | 페이지 버퍼 및 이를 이용한 플래쉬 메모리 소자의 검증방법 |
JP2006164408A (ja) | 2004-12-08 | 2006-06-22 | Toshiba Corp | 不揮発性半導体記憶装置及びそのデータ消去方法。 |
JP4786171B2 (ja) * | 2004-12-10 | 2011-10-05 | 株式会社東芝 | 半導体記憶装置 |
JP4768256B2 (ja) * | 2004-12-16 | 2011-09-07 | 株式会社東芝 | 半導体記憶装置 |
KR100672148B1 (ko) * | 2005-02-17 | 2007-01-19 | 주식회사 하이닉스반도체 | 불휘발성 메모리 장치 및 그것의 페이지 버퍼 동작 방법 |
US7221592B2 (en) | 2005-02-25 | 2007-05-22 | Micron Technology, Inc. | Multiple level programming in a non-volatile memory device |
KR100672122B1 (ko) | 2005-03-10 | 2007-01-19 | 주식회사 하이닉스반도체 | 소비 전력이 감소된 플래시 메모리 장치의 페이지 버퍼 회로 |
JP4660243B2 (ja) * | 2005-03-28 | 2011-03-30 | 株式会社東芝 | 半導体記憶装置 |
KR100600301B1 (ko) * | 2005-05-25 | 2006-07-13 | 주식회사 하이닉스반도체 | 면적이 감소된 페이지 버퍼 회로와, 이를 포함하는 플래시메모리 장치 및 그 프로그램 동작 방법 |
KR100694967B1 (ko) * | 2005-06-29 | 2007-03-14 | 주식회사 하이닉스반도체 | 프로그램 동작시 에러 발생 비율을 감소시키는 플래시메모리 장치 및 그 프로그램 동작 제어 방법 |
KR100624300B1 (ko) * | 2005-06-29 | 2006-09-19 | 주식회사 하이닉스반도체 | 프로그램 시간을 감소시키는 플래시 메모리 장치의프로그램 동작 제어 방법 |
KR100642892B1 (ko) * | 2005-07-19 | 2006-11-03 | 주식회사 하이닉스반도체 | 면적이 감소된 페이지 버퍼 회로와 그 독출 및 프로그램동작 방법 |
KR100666185B1 (ko) * | 2005-07-29 | 2007-01-09 | 삼성전자주식회사 | 3-레벨 불휘발성 반도체 메모리 장치 및 이에 대한구동방법 |
US7532530B2 (en) * | 2005-09-29 | 2009-05-12 | Hynix Semiconductor, Inc. | Semiconductor memory device |
US20080054973A1 (en) * | 2006-09-06 | 2008-03-06 | Atmel Corporation | Leakage improvement for a high-voltage latch |
US7548103B2 (en) * | 2006-10-26 | 2009-06-16 | Freescale Semiconductor, Inc. | Storage device having low power mode and methods thereof |
US7577029B2 (en) | 2007-05-04 | 2009-08-18 | Mosaid Technologies Incorporated | Multi-level cell access buffer with dual function |
-
2007
- 2007-12-28 US US11/966,152 patent/US7577029B2/en not_active Expired - Fee Related
-
2008
- 2008-04-28 KR KR1020097025304A patent/KR101453588B1/ko active IP Right Grant
- 2008-04-28 EP EP08748199A patent/EP2150958B1/de not_active Not-in-force
- 2008-04-28 JP JP2010504404A patent/JP5285064B2/ja not_active Expired - Fee Related
- 2008-04-28 AT AT08748199T patent/ATE534995T1/de active
- 2008-04-28 KR KR1020147008184A patent/KR101453725B1/ko active IP Right Grant
- 2008-04-28 WO PCT/CA2008/000797 patent/WO2008134858A1/en active Application Filing
- 2008-04-28 CN CN2008800229437A patent/CN101720484B/zh not_active Expired - Fee Related
- 2008-05-01 TW TW097116118A patent/TW200912950A/zh unknown
- 2008-05-01 TW TW104111608A patent/TW201530556A/zh unknown
-
2009
- 2009-07-08 US US12/499,577 patent/US7965550B2/en active Active
-
2011
- 2011-05-24 US US13/114,523 patent/US8274825B2/en active Active
-
2012
- 2012-08-27 US US13/595,466 patent/US8565026B2/en active Active
-
2013
- 2013-05-23 JP JP2013108569A patent/JP2013157077A/ja not_active Ceased
Also Published As
Publication number | Publication date |
---|---|
KR20100028028A (ko) | 2010-03-11 |
US20110222350A1 (en) | 2011-09-15 |
TW201530556A (zh) | 2015-08-01 |
KR101453588B1 (ko) | 2014-10-23 |
EP2150958A1 (de) | 2010-02-10 |
US7577029B2 (en) | 2009-08-18 |
KR20140047164A (ko) | 2014-04-21 |
CN101720484A (zh) | 2010-06-02 |
US7965550B2 (en) | 2011-06-21 |
US20080273386A1 (en) | 2008-11-06 |
WO2008134858A1 (en) | 2008-11-13 |
US20090273973A1 (en) | 2009-11-05 |
EP2150958B1 (de) | 2011-11-23 |
JP5285064B2 (ja) | 2013-09-11 |
US20120320674A1 (en) | 2012-12-20 |
JP2010526393A (ja) | 2010-07-29 |
US8274825B2 (en) | 2012-09-25 |
EP2150958A4 (de) | 2010-06-23 |
US8565026B2 (en) | 2013-10-22 |
TW200912950A (en) | 2009-03-16 |
KR101453725B1 (ko) | 2014-10-22 |
CN101720484B (zh) | 2013-05-01 |
JP2013157077A (ja) | 2013-08-15 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
ATE534995T1 (de) | Mehrebenen-zellenzugangspuffer mit zweifacher funktion | |
TWI457932B (zh) | 改善多層式儲存格(mlc)nand快閃記憶體之性能的方法和系統 | |
US20150310916A1 (en) | Nonvolatile memory system | |
TWI348699B (en) | Non-volatile memory with background data latch caching during read operations and methods therefor | |
ATE458248T1 (de) | Verwendung von latch-schaltungen für daten bei cachevorgängen in nichtflüchtigen speichern | |
IL183833A0 (en) | Pipelined programming of non-volatile memories using early data | |
TW200802402A (en) | Non-volatile memory device and methods using the same | |
TW200715291A (en) | Semiconductor storage device having memory cell for storing data by using difference in threshold voltage | |
US20190188126A1 (en) | Memory system and method of operating the same | |
US9208021B2 (en) | Data writing method, memory storage device, and memory controller | |
TW200608404A (en) | Operating non-volatile memory without read disturb limitations | |
US9147489B2 (en) | High voltage switch and a nonvolatile memory device including the same | |
US20200242025A1 (en) | Method for managing flash memory module and associated flash memory controller and electronic device | |
TW201604867A (zh) | 運用於雙埠靜態記憶體的寫入擾動減輕電路 | |
ATE512441T1 (de) | Bereitstellung von energiereduktion bei der datenspeicherung in einem speicher | |
ATE545934T1 (de) | Speichersystem | |
KR20200048315A (ko) | 메모리 컨트롤러 및 그 동작 방법 | |
TW200710656A (en) | Nonvolatile memory device and method of reducing data transfer time of nonvolatile memory device | |
US20140337574A1 (en) | Memory system, semiconductor memory device and operating method thereof | |
DE602007007974D1 (de) | Lesen einer nichtflüchtigen speicherzelle unter berücksichtigung des speicherstatus einer benachbarten speicherzelle | |
TW200703359A (en) | Two-bit per I/O line write data bus for DDR1 and DDR2 operating modes in a DRAM | |
DE602004010134D1 (de) | Kompensation einer langen lesezeit einer speichervorrichtung in datenvergleichs- und schreiboperationen | |
US8351275B2 (en) | Programming method for flash memory device | |
WO2008083132A3 (en) | Complete word line look ahead with efficient data latch assignment in non-volatile memory read operations | |
US9305649B1 (en) | Page buffer circuit for NAND flash memory |