DE602004010134D1 - Kompensation einer langen lesezeit einer speichervorrichtung in datenvergleichs- und schreiboperationen - Google Patents

Kompensation einer langen lesezeit einer speichervorrichtung in datenvergleichs- und schreiboperationen

Info

Publication number
DE602004010134D1
DE602004010134D1 DE602004010134T DE602004010134T DE602004010134D1 DE 602004010134 D1 DE602004010134 D1 DE 602004010134D1 DE 602004010134 T DE602004010134 T DE 602004010134T DE 602004010134 T DE602004010134 T DE 602004010134T DE 602004010134 D1 DE602004010134 D1 DE 602004010134D1
Authority
DE
Germany
Prior art keywords
memory
data
parallel
write
memory device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE602004010134T
Other languages
English (en)
Other versions
DE602004010134T2 (de
Inventor
Eric H Persoon
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP BV
Original Assignee
NXP BV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NXP BV filed Critical NXP BV
Publication of DE602004010134D1 publication Critical patent/DE602004010134D1/de
Application granted granted Critical
Publication of DE602004010134T2 publication Critical patent/DE602004010134T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/14—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements
    • G11C11/15—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements using multiple magnetic layers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2263—Write conditionally, e.g. only if new data and old data differ

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)
  • Measurement Of Current Or Voltage (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Mram Or Spin Memory Techniques (AREA)
DE602004010134T 2003-07-22 2004-07-12 Kompensation einer langen lesezeit einer speichervorrichtung in datenvergleichs- und schreiboperationen Expired - Lifetime DE602004010134T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
EP03102247 2003-07-22
EP03102247 2003-07-22
PCT/IB2004/051197 WO2005008675A1 (en) 2003-07-22 2004-07-12 Compensating a long read time of a memory device in data comparison and write operations

Publications (2)

Publication Number Publication Date
DE602004010134D1 true DE602004010134D1 (de) 2007-12-27
DE602004010134T2 DE602004010134T2 (de) 2008-09-11

Family

ID=34072669

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602004010134T Expired - Lifetime DE602004010134T2 (de) 2003-07-22 2004-07-12 Kompensation einer langen lesezeit einer speichervorrichtung in datenvergleichs- und schreiboperationen

Country Status (7)

Country Link
US (1) US7263018B2 (de)
EP (1) EP1649468B1 (de)
JP (1) JP2006528398A (de)
CN (1) CN1826658B (de)
AT (1) ATE378683T1 (de)
DE (1) DE602004010134T2 (de)
WO (1) WO2005008675A1 (de)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4565966B2 (ja) * 2004-10-29 2010-10-20 三洋電機株式会社 メモリ素子
CN100524267C (zh) * 2007-02-15 2009-08-05 威盛电子股份有限公司 数据处理系统及数据处理方法
KR101472797B1 (ko) * 2007-07-16 2014-12-15 삼성전자주식회사 데이터를 읽거나 쓰기 위한 방법 및 장치
CN102870159A (zh) * 2010-04-26 2013-01-09 莫塞德技术公司 在相变存储器中的写入方案
JP5443420B2 (ja) * 2011-03-23 2014-03-19 株式会社東芝 半導体記憶装置
US8806263B2 (en) * 2011-08-26 2014-08-12 Micron Technology, Inc. Methods and apparatuses including a global timing generator and local control circuits
US10931602B1 (en) 2019-05-10 2021-02-23 Innovium, Inc. Egress-based compute architecture for network switches in distributed artificial intelligence and other applications
US11099902B1 (en) 2019-05-10 2021-08-24 Innovium, Inc. Parallelized ingress compute architecture for network switches in distributed artificial intelligence and other applications
US10931588B1 (en) * 2019-05-10 2021-02-23 Innovium, Inc. Network switch with integrated compute subsystem for distributed artificial intelligence and other applications
US11328222B1 (en) 2019-05-10 2022-05-10 Innovium, Inc. Network switch with integrated gradient aggregation for distributed machine learning
US11057318B1 (en) 2019-08-27 2021-07-06 Innovium, Inc. Distributed artificial intelligence extension modules for network switches
US11114149B2 (en) 2019-11-13 2021-09-07 Wuxi Petabyte Technologies Co, Ltd. Operation methods of ferroelectric memory
WO2021176243A1 (en) 2020-03-03 2021-09-10 Micron Technology, Inc. On-the-fly programming and verifying method for memory cells based on counters and ecc feedback
TWI755154B (zh) * 2020-03-03 2022-02-11 美商美光科技公司 基於計數器及錯誤校正碼反饋用於記憶體單元之即時程式化及驗證方法
CN113642419B (zh) * 2021-07-23 2024-03-01 上海亘存科技有限责任公司 一种用于目标识别的卷积神经网络及其识别方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3146075B2 (ja) * 1992-10-14 2001-03-12 三菱電機株式会社 多重化メモリ装置
US6052302A (en) * 1999-09-27 2000-04-18 Motorola, Inc. Bit-wise conditional write method and system for an MRAM
JP3701886B2 (ja) * 2001-04-27 2005-10-05 インターナショナル・ビジネス・マシーンズ・コーポレーション 記憶回路ブロック及びアクセス方法
US6545906B1 (en) * 2001-10-16 2003-04-08 Motorola, Inc. Method of writing to scalable magnetoresistance random access memory element
JP2003151262A (ja) * 2001-11-15 2003-05-23 Toshiba Corp 磁気ランダムアクセスメモリ
US7382664B2 (en) * 2003-03-20 2008-06-03 Nxp B.V. Simultaneous reading from and writing to different memory cells

Also Published As

Publication number Publication date
CN1826658B (zh) 2011-06-15
WO2005008675A1 (en) 2005-01-27
US20060248258A1 (en) 2006-11-02
US7263018B2 (en) 2007-08-28
ATE378683T1 (de) 2007-11-15
CN1826658A (zh) 2006-08-30
EP1649468B1 (de) 2007-11-14
DE602004010134T2 (de) 2008-09-11
JP2006528398A (ja) 2006-12-14
EP1649468A1 (de) 2006-04-26

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Legal Events

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