AU2001287197A1 - Memory device having posted write per command - Google Patents
Memory device having posted write per commandInfo
- Publication number
- AU2001287197A1 AU2001287197A1 AU2001287197A AU8719701A AU2001287197A1 AU 2001287197 A1 AU2001287197 A1 AU 2001287197A1 AU 2001287197 A AU2001287197 A AU 2001287197A AU 8719701 A AU8719701 A AU 8719701A AU 2001287197 A1 AU2001287197 A1 AU 2001287197A1
- Authority
- AU
- Australia
- Prior art keywords
- data
- command
- array
- posted
- write command
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4076—Timing circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Dram (AREA)
- Medicines That Contain Protein Lipid Enzymes And Other Medicines (AREA)
- Electrotherapy Devices (AREA)
- Measuring Or Testing Involving Enzymes Or Micro-Organisms (AREA)
Abstract
A system and method for decreasing the memory access time by determining if data will be written directly to the array or be posted through a data buffer on a per command basis is disclosed. A memory controller determines if data to be written to a memory array, such as a DRAM array, is either written directly to the array or posted through a data buffer on a per command basis. If the controller determines that a write command is going to be followed by another write command, the data associated with the first write command will be written directly into the memory array without posting the data in the buffer.; If the controller determines that a write command will be followed by a read command, the data associated with the write command will be posted in the data buffer, allowing the read command to occur with minimal delay, and the posted data will then be written into the array when the internal I/O lines are no longer being used to execute the read command.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/641,518 US6647470B1 (en) | 2000-08-21 | 2000-08-21 | Memory device having posted write per command |
US09641518 | 2000-08-21 | ||
PCT/US2001/041798 WO2002017327A2 (en) | 2000-08-21 | 2001-08-21 | Memory device having posted write per command |
Publications (1)
Publication Number | Publication Date |
---|---|
AU2001287197A1 true AU2001287197A1 (en) | 2002-03-04 |
Family
ID=24572716
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AU2001287197A Abandoned AU2001287197A1 (en) | 2000-08-21 | 2001-08-21 | Memory device having posted write per command |
Country Status (7)
Country | Link |
---|---|
US (2) | US6647470B1 (en) |
EP (2) | EP2280399B1 (en) |
JP (1) | JP4846182B2 (en) |
KR (1) | KR100613941B1 (en) |
AT (1) | ATE526666T1 (en) |
AU (1) | AU2001287197A1 (en) |
WO (1) | WO2002017327A2 (en) |
Families Citing this family (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6647470B1 (en) * | 2000-08-21 | 2003-11-11 | Micron Technology, Inc. | Memory device having posted write per command |
US7133972B2 (en) | 2002-06-07 | 2006-11-07 | Micron Technology, Inc. | Memory hub with internal cache and/or memory access prediction |
US7117316B2 (en) | 2002-08-05 | 2006-10-03 | Micron Technology, Inc. | Memory hub and access method having internal row caching |
US7149874B2 (en) * | 2002-08-16 | 2006-12-12 | Micron Technology, Inc. | Memory hub bypass circuit and method |
US7836252B2 (en) | 2002-08-29 | 2010-11-16 | Micron Technology, Inc. | System and method for optimizing interconnections of memory devices in a multichip module |
US7054971B2 (en) * | 2002-08-29 | 2006-05-30 | Seiko Epson Corporation | Interface between a host and a slave device having a latency greater than the latency of the host |
US6820181B2 (en) | 2002-08-29 | 2004-11-16 | Micron Technology, Inc. | Method and system for controlling memory accesses to memory modules having a memory hub architecture |
US20050278503A1 (en) * | 2003-03-31 | 2005-12-15 | Mcdonnell Niall D | Coprocessor bus architecture |
US7245145B2 (en) | 2003-06-11 | 2007-07-17 | Micron Technology, Inc. | Memory module and method having improved signal routing topology |
US7120727B2 (en) | 2003-06-19 | 2006-10-10 | Micron Technology, Inc. | Reconfigurable memory module and method |
US7107415B2 (en) * | 2003-06-20 | 2006-09-12 | Micron Technology, Inc. | Posted write buffers and methods of posting write requests in memory modules |
US7260685B2 (en) | 2003-06-20 | 2007-08-21 | Micron Technology, Inc. | Memory hub and access method having internal prefetch buffers |
US7389364B2 (en) | 2003-07-22 | 2008-06-17 | Micron Technology, Inc. | Apparatus and method for direct memory access in a hub-based memory system |
US20050050237A1 (en) * | 2003-08-28 | 2005-03-03 | Jeddeloh Joseph M. | Memory module and method having on-board data search capabilities and processor-based system using such memory modules |
US7136958B2 (en) | 2003-08-28 | 2006-11-14 | Micron Technology, Inc. | Multiple processor system and method including multiple memory hub modules |
US7120743B2 (en) | 2003-10-20 | 2006-10-10 | Micron Technology, Inc. | Arbitration system and method for memory responses in a hub-based memory system |
US7330992B2 (en) | 2003-12-29 | 2008-02-12 | Micron Technology, Inc. | System and method for read synchronization of memory modules |
US7188219B2 (en) | 2004-01-30 | 2007-03-06 | Micron Technology, Inc. | Buffer control system and method for a memory system having outstanding read and write request buffers |
US7519788B2 (en) | 2004-06-04 | 2009-04-14 | Micron Technology, Inc. | System and method for an asynchronous data buffer having buffer write and read pointers |
US7519877B2 (en) | 2004-08-10 | 2009-04-14 | Micron Technology, Inc. | Memory with test mode output |
US20070050128A1 (en) * | 2005-08-31 | 2007-03-01 | Garmin Ltd., A Cayman Islands Corporation | Method and system for off-board navigation with a portable device |
US8250328B2 (en) | 2009-03-24 | 2012-08-21 | Micron Technology, Inc. | Apparatus and method for buffered write commands in a memory |
KR20210054187A (en) | 2019-11-05 | 2021-05-13 | 에스케이하이닉스 주식회사 | Memory system, memory device, and operating method of memory system |
KR20220156969A (en) | 2020-05-04 | 2022-11-28 | 자콥스 비히클 시스템즈, 인코포레이티드. | Valve actuation system with components that transmit lost motion and high lift in the main motion load path |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4965717A (en) * | 1988-12-09 | 1990-10-23 | Tandem Computers Incorporated | Multiple processor system having shared memory with private-write capability |
US5471598A (en) * | 1993-10-18 | 1995-11-28 | Cyrix Corporation | Data dependency detection and handling in a microprocessor with write buffer |
US5588125A (en) | 1993-10-20 | 1996-12-24 | Ast Research, Inc. | Method and apparatus for increasing bus bandwidth on a system bus by inhibiting interrupts while posted I/O write operations are pending |
US5587961A (en) | 1996-02-16 | 1996-12-24 | Micron Technology, Inc. | Synchronous memory allowing early read command in write to read transitions |
US5838631A (en) | 1996-04-19 | 1998-11-17 | Integrated Device Technology, Inc. | Fully synchronous pipelined ram |
US6026460A (en) | 1996-05-10 | 2000-02-15 | Intel Corporation | Method and apparatus for sequencing system bus grants and disabling a posting buffer in a bus bridge to improve bus efficiency |
US5881253A (en) | 1996-12-31 | 1999-03-09 | Compaq Computer Corporation | Computer system using posted memory write buffers in a bridge to implement system management mode |
US5881248A (en) | 1997-03-06 | 1999-03-09 | Advanced Micro Devices, Inc. | System and method for optimizing system bus bandwidth in an embedded communication system |
US6021459A (en) * | 1997-04-23 | 2000-02-01 | Micron Technology, Inc. | Memory system having flexible bus structure and method |
KR100270959B1 (en) | 1998-07-07 | 2000-11-01 | 윤종용 | Semiconductor memory device |
US6018484A (en) | 1998-10-30 | 2000-01-25 | Stmicroelectronics, Inc. | Method and apparatus for testing random access memory devices |
US6301627B1 (en) * | 1998-12-18 | 2001-10-09 | International Business Machines Corporation | Method/system for identifying delayed predetermined information transfer request as bypassable by subsequently-generated information transfer request using bypass enable bit in bridge translation control entry |
US6434665B1 (en) * | 1999-10-01 | 2002-08-13 | Stmicroelectronics, Inc. | Cache memory store buffer |
US6427189B1 (en) * | 2000-02-21 | 2002-07-30 | Hewlett-Packard Company | Multiple issue algorithm with over subscription avoidance feature to get high bandwidth through cache pipeline |
US6647470B1 (en) * | 2000-08-21 | 2003-11-11 | Micron Technology, Inc. | Memory device having posted write per command |
-
2000
- 2000-08-21 US US09/641,518 patent/US6647470B1/en not_active Expired - Lifetime
-
2001
- 2001-08-21 WO PCT/US2001/041798 patent/WO2002017327A2/en active Application Filing
- 2001-08-21 EP EP10009778.1A patent/EP2280399B1/en not_active Expired - Lifetime
- 2001-08-21 AT AT01966708T patent/ATE526666T1/en not_active IP Right Cessation
- 2001-08-21 AU AU2001287197A patent/AU2001287197A1/en not_active Abandoned
- 2001-08-21 KR KR1020037002589A patent/KR100613941B1/en active IP Right Grant
- 2001-08-21 EP EP01966708A patent/EP1312093B1/en not_active Expired - Lifetime
- 2001-08-21 JP JP2002521305A patent/JP4846182B2/en not_active Expired - Lifetime
-
2003
- 2003-09-15 US US10/661,496 patent/US6845433B2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
WO2002017327A3 (en) | 2002-06-13 |
KR20030026348A (en) | 2003-03-31 |
ATE526666T1 (en) | 2011-10-15 |
EP1312093A2 (en) | 2003-05-21 |
US20040080996A1 (en) | 2004-04-29 |
EP1312093B1 (en) | 2011-09-28 |
US6647470B1 (en) | 2003-11-11 |
US6845433B2 (en) | 2005-01-18 |
JP4846182B2 (en) | 2011-12-28 |
KR100613941B1 (en) | 2006-08-18 |
EP2280399B1 (en) | 2013-10-23 |
WO2002017327A2 (en) | 2002-02-28 |
EP2280399A1 (en) | 2011-02-02 |
JP2004507005A (en) | 2004-03-04 |
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