WO2021214866A1 - ヘテロ接合バイポーラトランジスタおよびその製造方法 - Google Patents

ヘテロ接合バイポーラトランジスタおよびその製造方法 Download PDF

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WO2021214866A1
WO2021214866A1 PCT/JP2020/017177 JP2020017177W WO2021214866A1 WO 2021214866 A1 WO2021214866 A1 WO 2021214866A1 JP 2020017177 W JP2020017177 W JP 2020017177W WO 2021214866 A1 WO2021214866 A1 WO 2021214866A1
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layer
emitter
electrode
forming
base
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French (fr)
Japanese (ja)
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悠太 白鳥
拓也 星
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NTT Inc
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Nippon Telegraph and Telephone Corp
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Priority to PCT/JP2020/017177 priority Critical patent/WO2021214866A1/ja
Priority to US17/915,018 priority patent/US20230163193A1/en
Priority to JP2022516512A priority patent/JPWO2021214866A1/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D10/00—Bipolar junction transistors [BJT]
    • H10D10/80—Heterojunction BJTs
    • H10D10/821—Vertical heterojunction BJTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D10/00—Bipolar junction transistors [BJT]
    • H10D10/01—Manufacture or treatment
    • H10D10/021—Manufacture or treatment of heterojunction BJTs [HBT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D10/00—Bipolar junction transistors [BJT]
    • H10D10/80—Heterojunction BJTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/133—Emitter regions of BJTs
    • H10D62/136—Emitter regions of BJTs of heterojunction BJTs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/82—Heterojunctions
    • H10D62/824—Heterojunctions comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/177—Base regions of bipolar transistors, e.g. BJTs or IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs

Definitions

  • the present invention relates to a heterojunction bipolar transistor and a method for manufacturing the same.
  • Heterojunction bipolar transistors (HBTs) using indium phosphide (InP) materials are excellent in high speed and high output, and are particularly applied to front-end ICs for large-capacity optical communications that require ultra-high frequency operation. As an application requirement, it is required to further increase the speed of HBT.
  • the base resistance is the sum of the intrinsic base resistance generated in the base layer immediately below the emitter layer, the base access resistance generated in the base layer from the emitter end to the base electrode end, and the base electrode resistance generated in the base electrode.
  • the intrinsic base resistance it is important to reduce the emitter width.
  • the base access resistance it is important to reduce the emitter-base electrode spacing.
  • the resistance of the base electrode it is important to make the base electrode thicker.
  • FIG. 3 shows an example of an InP-based HBT.
  • a sub-collector layer 302 made of InGaAs / InP and n-type impurities doped with a high concentration of n-type impurities are doped on a substrate 301 made of InP which has been made high resistance by doping Fe.
  • a collector layer 303 made of InP, a base layer 304 made of InGaAsSb doped with p-type impurities at a high concentration, and an emitter layer 305 made of InP doped with n-type impurities are provided.
  • an emitter cap layer 306 made of InGaAs in which n-type impurities are heavily doped is formed on the emitter layer 305.
  • a collector electrode 311 is formed on the sub-collector layer 302 around the collector layer 303, and a base electrode 312 is formed on the base layer 304 around the emitter layer 305.
  • the base electrode 312 is formed so as to surround the outer peripheral portion of the emitter layer 305 in order to reduce the base resistance.
  • a first emitter electrode 313 is formed on the emitter cap layer 306, and a second emitter electrode 314 is formed on the first emitter electrode 313.
  • a protective film 307 made of an insulating material is formed so as to cover the side surface of the emitter cap layer 306.
  • the base electrode forms a resist pattern in which the range from one end side to the other end side of the base layer is opened across the emitter in a plan view, and this state. It is formed by depositing the base electrode metal in and removing unnecessary metal on the resist pattern. In this manufacturing process, in addition to the base electrode forming region, the metal to be the base electrode is collectively deposited including the emitter electrode forming region.
  • the emitter electrode acts as an eaves, and an electrical short circuit between the emitter and the base electrode is caused. It is possible to form the base electrode as close to the emitter as possible while avoiding it.
  • the distance between the emitter layer and the base electrode can be reduced to a distance corresponding to the amount of undercut in the emitter cap layer, and a value of about 0.05 ⁇ m has been reported as this distance (non-patented). Document 1).
  • the InGaAs emitter cap layer thicker, it is possible to form the base electrode thicker without short-circuiting the emitter electrode and the base electrode. Resistance can also be reduced.
  • the emitter cap layer In the process of forming the emitter cap layer, it is necessary to achieve both dimensional controllability and selectivity not to etch the underlying emitter layer. Therefore, typically, after etching a certain thickness by a highly vertical dry etching method, the remaining emitter cap layer is completely removed by wet etching in order to obtain a selectivity with the emitter layer. Is used. In this method, in principle, a crystal plane peculiar to the material in which wet etching does not easily proceed is formed. For example, when InGaAs is etched using a citric acid-based etchant, the cross section perpendicular to the ⁇ 011> direction (FIG. 3) narrows from the side where the width of the emitter cap layer comes into contact with the emitter electrode toward the side of the base layer. , So-called reverse taper structure.
  • the emitter cap layer is formed thicker in order to increase the thickness of the base electrode, the distance between the emitter layer and the base electrode will also increase.
  • the base electrode is also made thinner.
  • the emitter cap layer can be completely removed by dry etching, a vertical cross-sectional structure can be formed, and the amount of undercut can be controlled and minimized.
  • the dry etching process is performed, the plasma density and the bias potential are locally uneven in the periphery of the emitter, and the etching rate is distributed in the plane.
  • the formation of a damaged layer due to plasma on the surface of the emitter layer may cause an influence such as deterioration of current gain.
  • dry etching it is difficult to obtain a sufficient etching selectivity with the underlying emitter layer, so it is very difficult to selectively and vertically remove only the emitter cap layer by dry etching. Is. Needless to say, it is extremely difficult to develop an InGaAs etchant that can obtain a high selectivity with InP, is less likely to cause side etching, and has good verticality.
  • the conventional technique has a problem that it is not easy to reduce the base resistance of the HBT and improve the high frequency characteristics.
  • the present invention has been made to solve the above problems, and an object of the present invention is to reduce the base resistance of a heterojunction bipolar transistor and improve high frequency characteristics.
  • the heterojunction bipolar transistor according to the present invention is formed on a collector layer made of a compound semiconductor formed on a substrate, a base layer made of a compound semiconductor formed on the collector layer, and an In.
  • a third emitter electrode made of the same type of metal as the base electrode is provided.
  • the method for manufacturing a heterojunction bipolar transistor according to the present invention includes a first step of forming a collector forming layer made of a compound semiconductor on a substrate and a second step of forming a base forming layer made of a compound semiconductor on the collector forming layer.
  • a twelfth step of patterning the forming layer to form a collector layer and a thirteenth step of forming a collector electrode are provided, and the seventh step forms a second emitter electrode having a larger area than the first emitter electrode in a plan view.
  • the emitter cap forming layer is patterned to form the emitter cap layer by forming the oxide layer by oxidation from the surface side and removing the oxide layer.
  • a first emitter electrode having an area equal to or larger than the area of the emitter cap layer in plan view is formed on the emitter cap layer, and the first emitter electrode in plan view is formed on the first emitter electrode. Since the second emitter electrode having a larger area is formed, the base resistance of the heterojunction bipolar transistor can be reduced and the high frequency characteristics can be improved.
  • FIG. 1 is a cross-sectional view showing the configuration of a heterojunction bipolar transistor according to the present invention.
  • FIG. 2A is a cross-sectional view showing a state of an element in an intermediate process for explaining a method for manufacturing a heterojunction bipolar transistor according to an embodiment of the present invention.
  • FIG. 2B is a cross-sectional view showing a state of an element in an intermediate process for explaining a method for manufacturing a heterojunction bipolar transistor according to an embodiment of the present invention.
  • FIG. 2C is a cross-sectional view showing a state of an element in an intermediate process for explaining a method for manufacturing a heterojunction bipolar transistor according to an embodiment of the present invention.
  • FIG. 2A is a cross-sectional view showing a state of an element in an intermediate process for explaining a method for manufacturing a heterojunction bipolar transistor according to an embodiment of the present invention.
  • FIG. 2B is a cross-sectional view showing a state of an element in an intermediate process for explaining a
  • FIG. 2D is a cross-sectional view showing a state of an element in an intermediate process for explaining a method for manufacturing a heterojunction bipolar transistor according to an embodiment of the present invention.
  • FIG. 2E is a cross-sectional view showing a state of an element in an intermediate process for explaining a method for manufacturing a heterojunction bipolar transistor according to an embodiment of the present invention.
  • FIG. 2F is a cross-sectional view showing a state of an element in an intermediate process for explaining a method for manufacturing a heterojunction bipolar transistor according to an embodiment of the present invention.
  • FIG. 2G is a cross-sectional view showing a state of an element in an intermediate process for explaining a method for manufacturing a heterojunction bipolar transistor according to an embodiment of the present invention.
  • FIG. 2H is a cross-sectional view showing a state of an element in an intermediate process for explaining a method for manufacturing a heterojunction bipolar transistor according to an embodiment of the present invention.
  • FIG. 3 is a cross-sectional view showing the configuration of a heterojunction bipolar transistor.
  • the heterojunction bipolar transistor is first formed on a collector layer 103 made of a compound semiconductor formed on a substrate 101, a base layer 104 made of a compound semiconductor formed on the collector layer 103, and a base layer 104. It includes an emitter layer 105 that is formed, contains In and P, and is made of a compound semiconductor different from the base layer 104.
  • this heterojunction bipolar transistor includes an emitter cap layer 106 made of a compound semiconductor containing In and As formed on the emitter layer 105.
  • the collector layer 103 is formed on the sub-collector layer 102 formed on the substrate 101.
  • the laminated structure of the collector layer 103 and the base layer 104 forms the first mesa having a rectangular shape in a plan view
  • the laminated structure of the emitter layer 105 and the emitter cap layer 106 forms a second mesa having a rectangular shape in a plan view.
  • the area of the second mesa is smaller than that of the first mesa in a plan view.
  • the substrate 101 is composed of, for example, InP having a high resistance by doping with Fe.
  • the sub-collector layer 102 is composed of, for example, InGaAs in which n-type impurities are heavily doped. Further, the sub-collector layer 102 may have a two-layer structure consisting of a layer made of InP on the side of the substrate 101 and a layer made of InGaAs formed on the layer.
  • the collector layer 103 is composed of, for example, InP doped with n-type impurities.
  • the base layer 104 is composed of InGaAsSb which is heavily doped with p-type impurities.
  • the emitter layer 105 is composed of InGaP doped with n-type impurities at a low concentration.
  • InGaP is a compound semiconductor containing In and P and different from the base forming layer 204.
  • the emitter cap layer 106 is made of InGaAs in which n-type impurities are heavily doped.
  • InGaAs is a compound semiconductor containing In and As.
  • the heterojunction bipolar transistor is formed on the collector electrode 111 electrically connected to the collector layer 103, the base electrode 112 formed on the base layer 104 around the emitter layer 105, and the emitter cap layer 106.
  • the formed first emitter electrode 113, second emitter electrode 114, and third emitter electrode 115 are provided.
  • the collector electrode 111 is formed on the sub-collector layer 102 around the collector layer 103, and is electrically connected to the collector layer 103 via the sub-collector layer 102.
  • the base electrode 112 is formed on the base layer 104 so as to surround the outer peripheral portion of the emitter layer 105 in order to reduce the base resistance.
  • the first emitter electrode 113 has an area equal to or larger than the area of the emitter cap layer 106 in a plan view, and is made of a tungsten alloy (for example, TiW).
  • the first emitter electrode 113 is formed in contact with the emitter cap layer 106.
  • the second emitter electrode 114 is formed in contact with the first emitter electrode 113, is composed of a metal (for example, W) containing tungsten (W) and different from that of the first emitter electrode 113, and is the first emitter in a plan view.
  • the area is larger than that of the electrode 113.
  • the third emitter electrode 115 is formed in contact with the second emitter electrode 114, and is made of the same metal as the base electrode 112.
  • the first emitter electrode 113 formed in an area smaller than the second emitter electrode 114 in a plan view is arranged inside the formation region of the second emitter electrode 114.
  • the outside of the region of the first emitter electrode 113 around the lower surface of the second emitter electrode 114 is in an eaves state.
  • the side surface (side portion) of the first emitter electrode 113 is in a so-called undercut state.
  • the first emitter electrode 113 has an area substantially the same as that of the emitter cap layer 106, or a slightly larger area.
  • the heterojunction bipolar transistor according to the embodiment includes a protective film 107 made of an insulating material formed by covering the side surfaces of the first emitter electrode 113 and the second emitter electrode 114.
  • the protective film 107 can be made of, for example, SiN, SiO 2 , Al 2 O 3, or the like.
  • the thickness of the base electrode 112 that can be formed can be controlled by the thickness of the first emitter electrode 113, and the thickness of the emitter cap layer 106 can be freely designed.
  • the emitter cap layer 106 can be made thinner while making the base electrode 112 thicker by making the first emitter electrode 113 thicker.
  • the emitter cap layer 106 can control the dimensions of the shape in a plan view with extremely high accuracy, and the emitter-base electrode spacing can be precisely controlled. In this way, the base access resistance can also be reduced by precisely reducing the distance between the emitter and the base electrodes while reducing the resistance of the base electrode 112. Further, the emitter cap layer 106 can be made with extremely high processing accuracy such as dimensional accuracy of the shape in a plan view, and the emitter can be finely miniaturized.
  • a sub-collector forming layer 202, a collector forming layer 203, a base forming layer 204, an emitter forming layer 205, and an emitter cap forming layer 206 are laminated and formed on the substrate 101 in this order. (1st step, 2nd step, 3rd step, 4th step).
  • the sub-collector cambium 202 is formed by crystal growth (epitaxial growth) of InGaAs in which n-type impurities are doped at a high concentration.
  • the collector forming layer 203 is formed by crystal growth of InP doped with n-type impurities.
  • the base forming layer 204 is formed by crystal growth of InGaAsSb doped with a high concentration of p-type impurities.
  • the emitter cambium 205 is formed by crystal growth of InGaP doped with n-type impurities at a low concentration.
  • the emitter cap forming layer 206 is formed by crystal growth of InGaAs in which n-type impurities are heavily doped.
  • the thickness, doping concentration, and composition of each layer described above are set to optimum values in order to obtain desired electrical performance.
  • the thickness of the emitter cap forming layer 206 which is the emitter cap layer 106, affects the distance between the emitter and base electrodes. Specifically, it is desirable to make the emitter cap forming layer 206 as thin as possible in order to minimize the emitter-base electrode spacing. On the other hand, from the viewpoint of the emitter contact resistance, if the emitter cap forming layer 206 is too thin, there is a concern that the emitter contact resistance will increase. Considering both, the thickness of the emitter cap forming layer 206 is preferably about 10 nm to 50 nm.
  • Each of the above-mentioned layers can be formed by a well-known metalorganic vapor phase growth method, molecular beam epitaxy method, or the like.
  • a first metal layer 213 made of TiW is formed on the emitter cap forming layer 206 (fifth step), and a second metal layer 213 made of W is formed on the first metal layer 213.
  • the metal layer 214 is formed (sixth step). These can be formed using a deposition technique such as a sputtering method.
  • the material of the first metal layer 213 and the material of the second metal layer 214 are of any material as long as they can be formed smaller than the area of the second emitter electrode 114 when the first emitter electrode 113 described later is formed. Does not matter. Specifically, in addition to TiW, various W alloys such as WN, WSi, and WSiN can be used.
  • the thickness of the base electrode 112 depends on the thickness of the first metal layer 213 serving as the first emitter electrode 113 and the thickness of the emitter cap forming layer 206. Therefore, the thickness of the first metal layer 213 is formed to be thicker than the value obtained by subtracting the thickness of the emitter cap forming layer 206 from the thickness of the base electrode 112. Typically, if the thickness of the base electrode 112 is about 100 to 200 nm, a sufficiently low base electrode resistance can be obtained, so that the thickness of the first metal layer 213 can also be 100 to 200 nm.
  • the thickness of the second metal layer 214 is selected so as to function as a mask in the patterning of the emitter cap forming layer 206, which will be described later.
  • tungsten which is a refractory metal
  • the second metal layer 214 and the first metal layer 213 are patterned, and as shown in FIG. 2C, the first emitter electrode 113 and the first emitter electrode 113 formed on the emitter cap forming layer 206.
  • the second emitter electrode 114 formed above is formed (7th step).
  • a resist pattern is formed using a known lithography technique, the resist pattern is used as a mask, and the second metal layer 214 and the first metal layer 213 are etched by dry etching using a fluorine-based gas.
  • the first metal layer 213 made of TiW is more likely to be etched in the surface direction of the substrate 101 than the second metal layer 214 made of W. Therefore, due to the etching process described above, the dimension of the substrate 101 in the plane direction is smaller in the first emitter electrode 113 than in the second emitter electrode 114.
  • the area of the first emitter electrode 113 in a plan view can be made slightly smaller than the area of the second emitter electrode 114 in a plan view, and an undercut structure can be formed.
  • a protective film 107 made of an insulating material that covers the side surfaces of the first emitter electrode 113 and the second emitter electrode 114 is formed (step 14).
  • insulating materials such as SiN, SiO 2 , and Al 2 O 3 are deposited to form an insulating film, and then dry etching is performed with a fluorine-based gas.
  • the protective film 107 can be formed by etching back using the material.
  • the protective film 107 By forming the protective film 107 in this way, it is possible to prevent the first emitter electrode 113 and the second emitter electrode 114 from being etched and changing in dimensions in the step of forming the emitter cap layer 106. Further, the dimensions of the emitter cap layer 106 in the plan view shape can be adjusted. It is desirable that the thickness of the protective film 107 is thin enough to function as an etching mask while minimizing the distance between the emitter and base electrodes, and a thickness of about 5 to 50 nm is sufficient. The above effect can be obtained.
  • the emitter cap layer 106 is formed on the emitter cap forming layer 205 as shown in FIG. 2E (8th step).
  • the emitter cap forming layer 206 is patterned by forming an oxide layer by oxidation from the surface side and removing the oxide layer.
  • the first emitter electrode 113 is used as a mask, the emitter cap forming layer 206 is selectively oxidized from the surface side, and the oxide layer formed by this oxidation is selectively removed by wet etching.
  • the above-mentioned formation of the oxide layer and removal of the oxide layer can be carried out by alternately immersing the hydrogen peroxide-based solution (oxidation process) and the phosphoric acid-based etchant (etching process).
  • oxidation process a very thin oxide layer with a thickness of sub-nanometer is formed on the exposed surface of the emitter cap forming layer 206, and in the etching process, the very thin oxide layer is removed and immersed (treated). It is possible to precisely control the etching amount by the number of repetitions of the two processes, not by the time.
  • the first emitter electrode 113 and the second emitter electrode 114 are not etched (without damaging the shape of the emitter electrode). It is possible to etch the emitter cap forming layer 206 to form the emitter cap layer 106 with an accuracy of sub-nanometer order.
  • the shape of the InGaAs layer in a plan view is ⁇ 0-1-1>, ⁇ 0-10>, respectively, regardless of the shape of the etching mask.
  • An octagonal shape composed of sides perpendicular to the ⁇ 0-11>, ⁇ 001>, ⁇ 011>, ⁇ 010>, ⁇ 01-1>, and ⁇ 00-1> directions, or ⁇ 0-10>, ⁇ It has a hexagonal shape composed of sides perpendicular to the 0-11>, ⁇ 001>, ⁇ 010>, ⁇ 01-1>, and ⁇ 00-1> directions, and the shape in a plan view is a part of the shape of the etching mask. It will be different.
  • the distance between the emitter and base electrodes depends on the difference between the dimensions of the emitter electrode in the plan view and the dimensions of the emitter cap layer in the plan view. For this reason, it has been difficult to make the emitter-base electrode spacing uniform over the entire outer peripheral portion of the emitter by the conventional etching method using citric acid. On the other hand, according to the manufacturing method in the above-described embodiment, the emitter-base electrode spacing can be controlled uniformly and precisely.
  • the etching rate of the As-based compound is sufficiently faster than that of the P-based compound constituting the emitter-forming layer 205.
  • the emitter cap layer 206 can be selectively removed to form the emitter cap layer 106 with almost no etching.
  • the emitter layer 105 is formed on the base cambium 204 under the emitter cap layer 106 as shown in FIG. 2F (9th). Process).
  • the emitter layer 105 can be formed by etching the emitter cambium 205 with the emitter cap layer 106 as a mask by wet etching using a known hydrochloric acid-based etchant.
  • the emitter layer 205 can be patterned to form the emitter layer 105 by a patterning method in which the oxidation process and the etching process are alternately performed.
  • the third emitter electrode 115 is formed on the second emitter electrode 114, and the base electrode 112 is formed on the base forming layer 204 around the emitter layer 105 (step 10). ).
  • the electrode material is deposited by vacuum vapor deposition. After that, by removing (lifting off) the resist pattern, the layer of the electrode material formed other than the electrode forming portion is removed together with the resist pattern. As a result, a layer of the electrode material remains at the electrode forming portion, and the third emitter electrode 115 and the base electrode 112 can be formed.
  • the third emitter electrode 115 and the base electrode 112 are made of the same material (metal).
  • the thickness of the base electrode 112 may be designed to be thinner than the total thickness of the first emitter electrode 113 and the emitter cap layer 106.
  • the second emitter electrode 114 becomes a shelter, the third emitter electrode 115 and the base electrode 112 are separated, and the emitter and the base electrode 112 are not short-circuited.
  • the base electrode 112 can be formed by being placed close to the emitter.
  • the base forming layer 204 is patterned by a known lithography technique and etching technique to form the base layer 104 on the collector forming layer 203 as shown in FIG. 2H (11th step). Further, the collector forming layer 203 is patterned to form the collector layer 103 (12th step). Further, the collector electrode 111 is formed on the sub-collector forming layer 202 (13th step). As a result, the heterojunction bipolar transistor shown in FIG. 1 is obtained.
  • the npn-type InGaP / InGaAsSb-based HBTs on the InP substrate which are promising for realizing ultra-high-speed integrated circuits, have been described in detail, but similar effects can be obtained with other HBTs, specifically InP / InGaAs HBTs. It is also effective for InP-based HBTs formed on the SiC heat dissipation substrate.
  • a first emitter electrode having an area equal to or larger than the area of the emitter cap layer in a plan view is formed on the emitter cap layer, and the first emitter in a plan view is formed on the first emitter electrode. Since the second emitter electrode having an area larger than that of the electrode is formed, the emitter cap layer can be thinned while making the base electrode thicker. As a result, according to the present invention, the base resistance of the heterojunction bipolar transistor can be reduced and the high frequency characteristics can be improved.

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PCT/JP2020/017177 2020-04-21 2020-04-21 ヘテロ接合バイポーラトランジスタおよびその製造方法 Ceased WO2021214866A1 (ja)

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US17/915,018 US20230163193A1 (en) 2020-04-21 2020-04-21 Heterojunction Bipolar Transistor and Method of Manufacturing the Same
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