WO2015067182A1 - 一种用于ⅲ-ⅴ族氮化物生长的衬底及其制备方法 - Google Patents

一种用于ⅲ-ⅴ族氮化物生长的衬底及其制备方法 Download PDF

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WO2015067182A1
WO2015067182A1 PCT/CN2014/090414 CN2014090414W WO2015067182A1 WO 2015067182 A1 WO2015067182 A1 WO 2015067182A1 CN 2014090414 W CN2014090414 W CN 2014090414W WO 2015067182 A1 WO2015067182 A1 WO 2015067182A1
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substrate
growth
buffer layer
layer
nitride
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PCT/CN2014/090414
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English (en)
French (fr)
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郝茂盛
朱广敏
袁根如
邢志刚
李振毅
齐胜利
刘文第
奚明
马悦
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上海蓝光科技有限公司
上海芯元基半导体科技有限公司
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Priority to US15/035,314 priority Critical patent/US20160359083A1/en
Priority to CN201480009718.5A priority patent/CN105190915A/zh
Priority to KR1020167015087A priority patent/KR20160122118A/ko
Publication of WO2015067182A1 publication Critical patent/WO2015067182A1/zh

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    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of group III and group V of the periodic system
    • H01L33/32—Materials of the light emitting region containing only elements of group III and group V of the periodic system containing nitrogen
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    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
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    • H01L21/02538—Group 13/15 materials
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    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
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    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
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    • H01L33/12—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
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    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/16—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular crystal structure or orientation, e.g. polycrystalline, amorphous or porous
    • H01L33/18—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular crystal structure or orientation, e.g. polycrystalline, amorphous or porous within the light emitting region
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    • H01L33/20—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
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    • H01L2924/11—Device type
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    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H01L33/22—Roughened surfaces, e.g. at the interface between epitaxial layers

Definitions

  • the present invention relates to the field of semiconductor illumination, and more particularly to a substrate for III-V nitride growth and a method of fabricating the same.
  • LEDs As a new high-efficiency solid-state light source, semiconductor lighting has the advantages of long life, energy saving, environmental protection and safety, and its application field is rapidly expanding.
  • the core of semiconductor lighting is light-emitting diodes (LEDs).
  • LEDs are composed of III-V compounds such as GaAs (gallium arsenide), GaP (gallium phosphide), GaAsP (phosphorus arsenide), GaN (nitrogen).
  • an active region of a quantum well is generally added between the N-type layer and the P-type layer of the PN junction.
  • the wavelength of the LED depends on the material constituting the LED PN junction and the quantum well and the width of the quantum well.
  • GaN-based III-V nitrides including InGaN, AlGaN, etc. are the best materials for preparing visible light LEDs.
  • the specific structure of the LED is mostly grown on the substrate in the order of the N-type layer, the active region, and the P-type layer by means of epitaxy. Since there are no inexpensive GaN homogeneous substrates, GaN-based LEDs are generally grown on Si, SiC, and sapphire substrates, with sapphire substrates being the most widely used substrates.
  • a two-step growth method for growing a device-level GaN epitaxial layer is: first, under the growth temperature of about 500 ° C, a buffer layer of GaN or AlGaN having a thickness of about 30 nm is grown on the surface of the sapphire substrate, and then the growth temperature is increased to be larger than At 1000 ° C, a high quality GaN epitaxial layer can be grown.
  • a buffer layer of GaN or AlGaN having a thickness of about 30 nm is grown on the surface of the sapphire substrate, and then the growth temperature is increased to be larger than At 1000 ° C, a high quality GaN epitaxial layer can be grown.
  • dislocations in the device structure fabricated by such a method There are a large number of dislocations in the device structure fabricated by such a method, and the higher the dislocation density, the lower the luminous efficiency of the device.
  • the most widely used so-called sapphire pattern substrate (PSS) technology can reduce the dislocation density in the epitaxial layer, improve the internal quantum efficiency of the LED, and improve the light extraction efficiency of the LED by diffuse scattering of the PSS pattern.
  • the PSS technology uses lithography and etching to form a variety of microscopic patterns on the sapphire surface. For example, in the (0001) crystal orientation sapphire surface, a tapered protrusion which is still composed of a sapphire material having a certain periodic structure is formed, and a certain area of (0001) crystal plane is reserved between the tapered protrusions.
  • the (0001) crystal plane between the tapered protrusion surface and the tapered protrusion Since there is a certain selective growth mechanism between the (0001) crystal plane between the tapered protrusion surface and the tapered protrusion, that is, when epitaxial growth is performed, the (0001) crystal plane between the tapered protrusions is formed.
  • the probability of nucleation is greater than the probability of nucleation on the surface of the tapered protrusion.
  • the epitaxial layer above the conical protrusion is generally formed by lateral growth, so epitaxial growth on the PSS substrate has the effect of lateral growth, which can reduce epitaxy.
  • the dislocation density in the layer increases the internal quantum efficiency of the LED using the PSS substrate.
  • the microstructure of the surface of the PSS substrate has a certain diffuse scattering effect on the light emitted by the LED, which can destroy the total reflection effect, so the PSS substrate can also improve the light extraction efficiency of the LED.
  • the two-step method described above is also used.
  • the crystal orientation of the crystal nucleus formed on the surface of the protrusion is different from the crystal orientation of the crystal nucleus formed on the (0001) crystal plane between the conical protrusions, which easily leads to the generation of polycrystals; again, since the refractive index of the sapphire substrate is high , about 1.8, even if the convex structure is formed on the surface, the diffuse scattering effect on the light emitted by the LED is not the best, and the improvement of the light extraction efficiency is also very limited.
  • Epitaxial Lateral Overgrowth is a dielectric mask formed on a high-quality GaN epitaxial layer having a thickness of on the order of micrometers, and then subjected to secondary epitaxial growth to obtain GaN having a relatively low dislocation density.
  • the high-quality GaN epitaxial layer is a single crystal structure and has high production cost.
  • GaN with a thickness greater than 1 ⁇ m between the dielectric pattern and the sapphire surface affects the diffuse scattering effect, and GaN larger than 1 ⁇ m also affects device uniformity and repeatability.
  • an object of the present invention is to provide a substrate for III-V nitride growth and a method for fabricating the same, which are used to solve the problem of low growth quality and low light emission rate of LEDs in the prior art. And other issues.
  • the present invention provides a substrate for III-V nitride growth, comprising at least:
  • a buffer layer for subsequent growth of the epitaxial structure, the lower surface of the buffer layer being bonded to the surface of the growth substrate;
  • a plurality of semiconductor dielectric protrusions are spaced apart from the upper surface of the buffer layer, and a convex bottom surface is combined with the upper surface of the buffer layer, and a buffer layer is exposed between the protrusions.
  • the present invention also provides a method of fabricating a substrate for III-V nitride growth, comprising at least the following steps:
  • etching the dielectric layer by a photolithography process to form a plurality of protrusions arranged at intervals, and exposing a buffer layer between the protrusions.
  • the present invention provides a substrate for group III-V nitride growth and a method of fabricating the same. Since the novel pattern substrate uses a semiconductor dielectric layer as a mask, the effect of selective growth is remarkable, so that the quality of the epitaxial layer can be improved, the dislocation density can be reduced, the quality of the LED chip can be improved, and the internal quantum efficiency of the LED can be improved.
  • the present invention selects a convex structure in which a semiconductor dielectric layer having a relatively small refractive index is arranged in a processing cycle, and can also increase the reflection and scattering effect of light emitted by the LED, thereby improving the light-emitting efficiency of the LED.
  • the two-step growth method is not required, but the high temperature growth is directly performed, so that the growth time of the LED epitaxial structure can be reduced, and the epitaxial cost can be reduced.
  • the preparation method of the invention has simple process, is favorable for reducing manufacturing cost, and is suitable for industrial production.
  • processing the semiconductor dielectric layer is a very common and conventional technique in the semiconductor process, processing the semiconductor dielectric layer is much easier than processing the sapphire, so the method is very compatible with the existing LED chip process and is easy to mass-produce.
  • the preparation process window is wider than the process window for preparing a conventional PSS substrate, and the lithography and product yield are high. This technology can increase the productivity of the graphics substrate and reduce the cost of the graphics substrate.
  • 1 to 2 show the steps 1) of the method for fabricating a III-V nitride grown substrate of the present invention. Schematic diagram of the structure.
  • FIG. 3 is a schematic view showing the structure of the method 2) for fabricating a III-V nitride grown substrate of the present invention.
  • FIGS. 4 to 7 are views showing the structure of the step 3) of the method for fabricating a III-V nitride grown substrate of the present invention.
  • the material of the growth substrate is one of sapphire, SiC, Si, and ZnO.
  • the buffer layer has a thickness of 50 to 600 angstroms, preferably 100 to 500 angstroms, more preferably 200 to 400 angstroms.
  • An excessively thin buffer layer cannot meet the nucleation requirements required for subsequent epitaxial growth, resulting in a decrease in the growth quality of the epitaxial layer; an excessively thick buffer layer may cause insufficient recrystallization of the buffer layer during subsequent heating, affecting the quality of the epitaxial layer; An excessively thick buffer layer also affects the light extraction efficiency of LEDs fabricated on such substrates.
  • the buffer layer is any amorphous or polycrystalline material capable of forming a hexagonal symmetric crystal by annealing and recrystallization, more preferably selected.
  • Al x Ga 1-x N prepared by metal organic chemical chemical vapor deposition, 0 ⁇ X ⁇ 0.5, preferably 0 ⁇ X ⁇ 0.2, the temperature range is 450-700 ° C, preferably 500-600 ° C;
  • AlN prepared by metal organic chemical vapor deposition method has a temperature range of 700 to 1000 ° C; an AlN layer prepared by a sputtering method, the crystal orientation of the AlN layer is (0001) orientation; BN; or ZnO.
  • the preparation method of the above buffer layer is known to those skilled in the art and will not be described herein.
  • the preparation temperature of the buffer layer is low, the required thickness is small, and the production cost can be effectively reduced while ensuring nucleation growth of the subsequent light-emitting epitaxial structure (especially GaN-based light-emitting epitaxial structure).
  • the AlN layer prepared by sputtering has the advantages of high thickness controllability, high crystal orientation, and favorable luminescent epitaxial structure (especially GaN-based luminescent epitaxial structure). ) nucleation growth.
  • the semiconductor dielectric protrusion is at least one of SiO 2 , SiN, or SiON, more preferably SiO 2 .
  • the semiconductor medium protrusion has a height of 0.2 to 3 ⁇ m, preferably 0.5 to 2 ⁇ m.
  • the plurality of semiconductor dielectric bumps are periodically spaced, and the bottom of the semiconductor dielectric bump has a width of 0.3 to 4 ⁇ m and a pitch of 0.1 to 2 ⁇ m.
  • the smaller the bottom width of the semiconductor dielectric bumps the smaller the spacing.
  • the semiconductor dielectric bump is a semiconductor dielectric clad bump, a semiconductor dielectric conical bump or a semiconductor dielectric pyramid bump.
  • a flattened convex protrusion on the surface can effectively improve the growth quality of a subsequent light-emitting epitaxial structure (especially a GaN-based light-emitting epitaxial structure), and thus is preferable.
  • the protrusion has a bottom surface that is in contact with the upper surface of the buffer layer, and the bottom surface has a polygonal shape, a triangular shape, or a circular shape. a combination of one or more of them.
  • the protrusion further has a top surface parallel to the bottom surface, and the top surface is polygonal, triangular, or circular. A combination of one or more.
  • the top surface has the same shape as the bottom surface and is smaller than the bottom surface.
  • the top surface and the bottom surface have different shapes and are smaller than the bottom surface.
  • the material of the growth substrate is one of sapphire, SiC, Si, and ZnO.
  • the buffer layer has a thickness of 50 to 600 angstroms, preferably 100 to 500 angstroms, more preferably 200 to 400 angstroms. .
  • the buffer layer is any amorphous or polycrystalline material capable of forming a hexagonal symmetric crystal by annealing and recrystallization.
  • it is at least one selected from the group consisting of Al x Ga 1-x N prepared by metal organic compound chemical vapor deposition, 0 ⁇ X ⁇ 0.5, preferably 0 ⁇ X ⁇ 0.2, and a temperature range of 450 to 700 ° C is prepared.
  • AlN prepared by metal organic chemical vapor deposition method, the temperature range is 700-1000 ° C
  • AlN layer prepared by sputtering method, the crystal orientation of the AlN layer is (0001) orientation ; BN; or ZnO.
  • step 2) forming a semiconductor dielectric layer on the surface of the buffer layer by plasma enhanced chemical vapor deposition (PECVD),
  • the dielectric material is at least one of SiO 2 , SiN, or SiON, and more preferably SiO 2 .
  • a SiO 2 semiconductor dielectric layer is formed from SiH 4 and N 2 O in a plasma reaction environment at a temperature range of 250-350 ° C by PECVD.
  • the semiconductor dielectric layer of the step 2) has a thickness of 0.2 to 3 ⁇ m, preferably 0.5 to 2 ⁇ m.
  • etching a plurality of protrusions arranged in a spaced manner in the dielectric layer in step 3) is very common and conventional in a semiconductor process. Techniques are known to those skilled in the art and therefore will not be described again.
  • the plurality of semiconductor dielectric bumps are arranged at periodic intervals, and the bottom width of the semiconductor dielectric bump is 0.3 to 4 ⁇ m.
  • the pitch is 0.1 to 2 ⁇ m. In principle, the smaller the bottom width of the semiconductor dielectric bumps, the smaller the spacing.
  • the semiconductor dielectric bump of the step 3) is a semiconductor dielectric wrap bump, a semiconductor dielectric conical bump or
  • the semiconductor medium has pyramidal protrusions, preferably semiconductor dielectric cladding protrusions.
  • the protrusion has a bottom surface that is in contact with the upper surface of the buffer layer, and the bottom surface is polygonal or triangular. , a combination of one or more of the circles.
  • the semiconductor dielectric protrusion is a semiconductor dielectric package protrusion, and the step 3) includes the following steps:
  • the photoresist layer can be made into an interval by an exposure process or a nanoimprint process.
  • the plurality of photoresist blocks are arranged in a row, and the exposure process may be step exposure or contact exposure.
  • the embodiment provides a substrate for GaN growth, and the manufacturing method thereof comprises the following steps:
  • the growth substrate 101 is a commercially available flat plate type sapphire substrate having a surface crystal orientation (0001) and having an atomic level flatness.
  • a no-clean substrate was used, which was used without additional cleaning.
  • the above substrate was placed on a graphite tray having a SiC protective layer and sent to a MOCVD (Metal Organic Chemical Vapor Deposition) reaction chamber; the substrate was heated to 1100 ° C under a hydrogen atmosphere, and kept at this temperature for 10 minutes.
  • MOCVD Metal Organic Chemical Vapor Deposition
  • the substrate temperature was lowered to 550 ° C, and ammonia gas, trimethyl aluminum (TMAl) and trimethyl gallium (TMGa) were simultaneously introduced into the reaction chamber, wherein the standard flow rate of ammonia gas was 56 liters / minute, TMAl and The molar flow rates of TMGa were 3.25e-5 and 2.47e-4 mol/min, respectively, the pressure in the reaction chamber was 500 torr, and the pass time was 215 seconds.
  • a SiO 2 layer 103 is formed on the surface of the buffer layer 102 by PECVD (plasma enhanced chemical vapor deposition) to a thickness of 1 ⁇ m.
  • PECVD plasma enhanced chemical vapor deposition
  • the temperature in the PECVD reaction chamber is 350 ° C
  • the pressure is 1 torr (one standard atmospheric pressure is 760 torr)
  • the flow rates of SiH 4 and N 2 O are 10 sccm (standard cc / min) and 300 sccm, respectively
  • the RF power supply is 30 W.
  • the pattern formed is a periodically spaced SiO 2 protrusion arranged in a hexagonal close-packed manner with a period of 3 ⁇ m, a SiO 2 bump having a bottom width of 2 ⁇ m and a pitch of 1 ⁇ m.
  • step 3 includes the following steps:
  • step 3-1) is performed, a 1 ⁇ m photoresist layer 104 is coated on the surface of the SiO 2 layer 103, and the photoresist layer 104 is formed into a hexagonal density by an exposure process.
  • the photoresist cylinders 105 arranged in a stacked manner have a hexagonal close-packing period of 3 ⁇ m, a photoresist cylinder having a diameter of 2 ⁇ m and a pitch of 1 ⁇ m.
  • step 3-2) is then performed to reflow the plurality of photoresist cylinders into a hemispherical shape by a heating reflow process, wherein the reflux temperature is 130 degrees Celsius and the reflux time is 120 seconds.
  • each of the hemispherical photoresist patterns is transferred to the SiO 2 layer 103 by inductively coupled plasma etching (ICP) to form a plurality of SiO 2 packages.
  • ICP inductively coupled plasma etching
  • the protrusions are exposed, and the buffer layer 102 between the SiO 2 clad protrusions is exposed for epitaxial growth of the subsequent GaN epitaxial material.
  • the above ICP etching process conditions are as follows: the etching gas is CHF 3 (trifluoromethane), the standard flow rate is 50 ml/min; the upper electrode power of the ICP is 1000 W, and the lower electrode power is 50 W.
  • a GaN epitaxial layer having a thickness of 6 ⁇ m was epitaxially grown on a sapphire patterned substrate (PSS) and a novel pattern substrate prepared using the above-described steps disclosed in the present invention, respectively, using the same MOCVD apparatus.
  • the specific growth conditions of MOCVD are: growth temperature is 1050 ° C, annealing time from room temperature to growth temperature is 15 minutes; reaction chamber pressure is 500 torr; ammonia gas standard flow rate is 56 l / min; TMGa molar flow rate is 1.5 e-3 Molar/min, growth time is 150 minutes.
  • the mass of the epitaxial layer of the crystal is characterized by XRD (x-ray twin crystal diffraction) line.
  • XRD x-ray twin crystal diffraction
  • the test results show that the half widths of the XRD (002) and (102) diffraction peaks of the GaN epitaxial layer grown on the conventional PSS substrate are 280 and 302 arc seconds, respectively, and the GaN epitaxy on the novel pattern substrate prepared by the present invention
  • the half widths of the XRD (002) and (102) diffraction peaks of the layer were 243 and 258 arc seconds, respectively. It can be clearly seen from the above experiments that the novel pattern substrate prepared in the above step has better quality than the GaN epitaxial layer grown on the conventional PSS substrate.
  • the light-emitting efficiency of the LED device grown using the two substrates was measured.
  • the luminous efficiency of LEDs prepared using the substrates of the present invention is relatively large compared to conventional PSS substrates.
  • the luminous flux after packaging of the 3528 LED chip manufactured by the conventional PSS substrate is 18.30 lm on average; and the luminous flux of the LED chip using the substrate of the invention is 19.23 lm on average, and the luminous efficiency is improved by 5% or more.
  • the present embodiment provides a method for fabricating a substrate for GaN growth, the basic steps of which are as in Embodiment 1, except that the second step is: the semiconductor dielectric layer 103.
  • the raw materials for growing the SiN layer are NH 3 (ammonia gas) and SiH 4 (silane), the growth temperature is 400 ° C, the flow rate of SiH 4 is 20 sccm, the NH 3 is 17 sccm, and the N 2 is 980 sccm.
  • the pressure is 0.8 torr.
  • a GaN epitaxial layer having a thickness of 6 ⁇ m was epitaxially grown on a conventional PSS substrate and on a novel pattern substrate prepared using the above steps under substantially the same growth conditions, respectively.
  • the half widths of the XRD (002) and (102) diffraction peaks of the GaN epitaxial layer grown on the conventional PSS substrate in the above experiment were 280 and 302 arc seconds, respectively, and were grown on the novel pattern substrate prepared by the present invention.
  • the half widths of the XRD (002) and (102) diffraction peaks of the GaN epitaxial layer were 270 and 283 arc seconds, respectively. From the above experiments, it is apparent that the novel pattern substrate prepared by the above steps of the present invention has further advantages over the conventional PSS substrate.
  • the present embodiment provides a method for fabricating a substrate for GaN growth, the basic steps of which are as in Embodiment 1, wherein the buffer layer 102 is formed by physical vapor deposition (PVD).
  • the prepared AlN layer having a thickness of 200 angstroms was used as an Al target, the sputtering gas was N 2 , the substrate temperature was 600 ° C, and the sputtering power was 600 W.
  • the obtained AlN is a columnar polycrystal whose main crystal orientation is (0001).
  • a GaN epitaxial layer having a thickness of 6 ⁇ m was epitaxially grown on a conventional PSS substrate and on a novel pattern substrate prepared using the above steps under substantially the same growth conditions, respectively.
  • the half widths of the XRD (002) and (102) diffraction peaks of the GaN epitaxial layer grown on the conventional PSS substrate in the above experiment were 280 and 302 arc seconds, respectively, and were grown on the novel pattern substrate prepared by the present invention.
  • the half widths of the XRD (002) and (102) diffraction peaks of the GaN epitaxial layer were 237 and 253 arc seconds, respectively. From the above experiments, it is apparent that the novel pattern substrate prepared by the above steps of the present invention has further advantages over the conventional PSS substrate.

Abstract

一种用于III-Ⅴ族氮化物生长的衬底及其制造方法，所述制造方法包括以下步骤：1）提供一生长衬底，于所述生长衬底表面形成用于后续发光外延结构生长的缓冲层；2）于所述缓冲层表面形成半导体介质层；3）通过光刻工艺将所述半导体介质层刻蚀出间隔排列的多个半导体介质凸起，且露出各该半导体介质凸起之间的缓冲层。该方法既能保证生长发光外延结构的晶体质量，又能提高发光二极管的出光效率。工艺简单，有利于降低制造成本，适用于工业生产。

Description

一种用于Ⅲ-Ⅴ族氮化物生长的衬底及其制备方法 技术领域
本发明涉及半导体照明领域，特别是涉及一种用于Ⅲ-Ⅴ族氮化物生长的衬底及其制造方法。
背景技术
半导体照明作为新型高效固体光源，具有寿命长、节能、环保、安全等优点，其应用领域正在迅速扩大。半导体照明的核心是发光二极管(LED)，从结构上来讲LED就是由III-V族化合物，如GaAs(砷化镓)、GaP(磷化镓)、GaAsP(磷砷化镓)、GaN(氮化镓)等半导体形成的PN结。因此，它具有一般PN结的I-V特性，即正向导通、反向截止、击穿特性。此外，在一定条件下，它还具有发光特性。在正向电压下，电子由N区注入P区，空穴由P区注入N区。进入对方区域的少数载流子(少子)一部分与多数载流子(多子)复合而发光。
为了增加LED的发光效率一般会在PN结的N型层和P型层之间增加一个量子阱的有源区，LED的发光波长取决于组成LED PN结和量子阱的材料及量子阱的宽度，GaN基III-V氮化物包括InGaN、AlGaN等是制备可见光LED的最佳材料。LED的具体结构大都是利用外延的手段按照N型层、有源区、P型层的顺序依次生长在衬底之上。由于没有廉价的GaN同质衬底，GaN基LED一般生长在Si、SiC及蓝宝石衬底之上，其中蓝宝石衬底是使用最广泛的衬底。
在异质衬底上生长高质量的晶体材料非常困难，在蓝宝石衬底上生长器件级的GaN晶体材料更是困难，直到90年代初，日本人利用金属有机化合物气相沉积(MOCVD)开发出了生长器件级GaN外延层的两步生长法。所谓的两步生长法就是：首先在500℃左右的生长温度之下，在蓝宝石衬底表面生长厚度在30纳米左右的GaN或AlGaN的缓冲层(buffer layer)，然后再把生长温度提高到大于1000℃，才能生长出高质量的GaN外延层。用这样的方法制成的器件结构中存在大量的位错，位错密度越高器件的发光效率越低。
现在应用最广泛的所谓蓝宝石图形衬底(PSS)技术，可以减少外延层中的位错密度，提高LED的内量子效率，也可以通过PSS图形的漫散射，提高LED的出光效率。常规 的PSS技术就是利用光刻工艺和腐蚀工艺在蓝宝石表面形成各种各样的微观图形。比如在(0001)晶向的蓝宝石表面形成具有一定周期性结构的仍然由蓝宝石材料组成的锥形突起，锥形突起之间要保留一定面积的(0001)晶面。由于在锥形突起表面和锥形突起之间的(0001)晶面之间存在一定的选择性生长机理，也就是，进行外延生长时，在锥形突起之间的(0001)晶面上成核的几率要比在锥形突起表面上成核的几率大，锥形突起上面的外延层一般由侧向生长形成，所以在PSS衬底上进行外延生长具有侧向生长的效果，能降低外延层中的位错密度，提高使用PSS衬底的LED的内量子效率。另一方面PSS衬底表面的微观结构对LED所发出的光有一定的漫散射效果，能破坏全反射作用，因此PSS衬底还可以提高LED的出光效率。在常规PSS衬底上生长LED外延结构，也要用到上面介绍的两步法。
常规的PSS技术还有许多缺陷。首先，由于不管是用湿法还是用干法，蓝宝石的加工难度都非常大，这不但会影响常规PSS的产品良率，还会增加制造成本；其次，由于蓝宝石锥形突起表面和锥形突起之间的(0001)晶面之间的生长选择性不是非常明显，如果锥形突起之间的(0001)晶面的面积太小，在锥形突起的表面也会成核，而且在锥形突起表面形成的晶核的晶向和在锥形突起之间的(0001)晶面上形成的晶核的晶向不同，容易导致多晶的产生；再次，由于蓝宝石衬底的折射率较高，为1.8左右，即使于其表面形成凸起结构，对LED所发出的光的漫散射效果也不是最好，对出光效率的提升也有很大的限制。
侧向外延生长技术(Epitaxial Lateral Overgrowth，ELO)是在厚度为微米量级的高品质的GaN外延层上形成介质掩膜，然后进行二次外延生长得到位错密度比较低的GaN。所述高品质的GaN外延层为单晶结构，生产成本高。而且在介质图形和蓝宝石表面之间厚度大于1微米GaN会影响漫散射的效果，另外大于1微米GaN还会影响器件的一致性，和重复性。
有文章报道了直接在蓝宝石衬底表面形成介质层图形，进行外延生长，但是工艺窗口很小，没有量产价值。
现在也存在在常规PSS上溅射(Sputter)一层有一定晶向的氮化铝(AlN)的技术，与该技术也有明显差别，性价比也比该技术差。
因此，提供一种可以有效提高GaN基外延层及LED外延结构晶体质量、例如位错密度，并且能改善LED各项性能指标、尤其是LED发光效率的新型图形衬底及其制备方法实属必要。
发明内容
鉴于以上所述现有技术的缺点，本发明的目的在于提供一种用于Ⅲ-Ⅴ族氮化物生长的衬底及其制造方法，用于解决现有技术中发光二极管生长质量及出光率低等问题。
本发明提供一种用于Ⅲ-Ⅴ族氮化物生长的衬底，至少包括：
生长衬底；
用于后续发光外延结构生长的缓冲层，所述缓冲层下表面结合于所述生长衬底表面；以及
多个半导体介质凸起，间隔排列于所述缓冲层上表面，凸起底面与所述缓冲层上表面结合，各凸起之间露出缓冲层。
本发明还提供一种用于Ⅲ-Ⅴ族氮化物生长的衬底的制造方法，至少包括以下步骤：
1)提供一生长衬底，于所述生长衬底表面形成用于后续发光外延结构生长的缓冲层；
2)于所述缓冲层表面形成半导体介质层；
3)通过光刻工艺将所述介质层刻蚀出间隔排列的多个凸起，且露出各凸起之间的缓冲层。
如上所述，本发明提供一种用于Ⅲ-Ⅴ族氮化物生长的衬底及其制造方法。由于该新型图形衬底使用半导体介质层作为掩膜，选择性生长的效果明显，因此其可以提高外延层的质量，减少位错密度，改善LED芯片的品质，提高LED的内量子效率。此外，本发明选用折射率比较小的半导体介质层加工周期排列的凸起结构，还可以增加LED所发出的光的反射散射效果，提高LED的出光效率。
此外，使用该新型图形衬底外延生长LED外延结构时，不需要使用两步生长法，而是直接进行高温生长，所以可以减少LED外延结构的生长时间，降低外延成本。
本发明的制备方法工艺简单，有利于降低制造成本，适用于工业生产。具体地，由于半导体介质层的加工是半导体工艺中非常普遍和常规的技术，加工半导体介质层要比加工蓝宝石容易得多，因此该方法和现有LED芯片工艺兼容性非常好、很容易量产、制备工艺窗口比制备常规PSS衬底的工艺窗口宽、光刻和产品良率高。该技术可以提高图形衬底的产能、降低图形衬底的成本。
附图说明
图1～图2显示为本发明的用于Ⅲ-Ⅴ族氮化物生长的衬底的制造方法步骤1)所呈现 的结构示意图。
图3显示为本发明的用于Ⅲ-Ⅴ族氮化物生长的衬底的制造方法步骤2)所呈现的结构示意图。
图4～图7显示为本发明的用于Ⅲ-Ⅴ族氮化物生长的衬底的制造方法步骤3)所呈现的结构示意图。
元件标号说明
101                   生长衬底
102                   缓冲层
103                   半导体介质层
104                   光刻胶层
105                   光刻胶块
106                   包状的光刻胶块
107                   半导体介质凸起
具体实施方式
作为本发明的用于Ⅲ-Ⅴ族氮化物生长的衬底的一种优选方案，所述生长衬底的材料为蓝宝石、SiC、Si及ZnO的一种。
作为本发明的用于Ⅲ-Ⅴ族氮化物生长的衬底的一种优选方案，所述缓冲层的厚度为50～600埃，优选100～500埃，更优选200～400埃。过薄的缓冲层无法满足后续外延生长所需的成核要求，导致外延层生长质量下降；过厚的缓冲层会导致缓冲层在后续的升温过程中再结晶不够充分，影响外延层的质量；过厚的缓冲层还会影响在这样的衬底上制备的LED的出光效率。
作为本发明的用于Ⅲ-Ⅴ族氮化物生长的衬底的一种优选方案，所述缓冲层为任何能通过退火再结晶形成六角对称结构晶体的非晶或多晶材料，更优选地选自：采用金属有机化合物化学气相沉积法制备的AlxGa1-xN，0≤X≤0.5，优选0≤X≤0.2，制备的温度范围为450～700℃，优选500～600℃；采用金属有机化合物化学气相沉积法制备的AlN，制备的温度范围为700～1000℃；采用溅射法制备的AlN层，所述AlN层的晶向为(0001)取向；BN；或ZnO。上述缓冲层的制备方法为本领域技术人员已知，在此不再赘述。
由于所述缓冲层的制备温度较低，所需的厚度较小，在保证后续发光外延结构(尤其 是GaN基发光外延结构)成核生长的同时，可以有效地降低生产成本。相比于低温AlxGa1-xN层，溅射法制备AlN层的好处是厚度可控性强、晶向取向度较高，同时也有利于发光外延结构(尤其是GaN基发光外延结构)的成核生长。
作为本发明的用于Ⅲ-Ⅴ族氮化物生长的衬底的一种优选方案，所述半导体介质凸起为SiO2、SiN、或SiON中至少一种，更优选SiO2。
作为本发明的用于Ⅲ-Ⅴ族氮化物生长的衬底的一种优选方案，所述半导体介质凸起的高度为0.2～3μm，优选0.5～2μm。
作为本发明的用于Ⅲ-Ⅴ族氮化物生长的衬底的一种优选方案，所述多个半导体介质凸起呈周期性间隔排列，半导体介质凸起的底部宽度为0.3～4μm，间距为0.1～2μm。原则上，半导体介质凸起的底部宽度越小，其间距也越小。
作为本发明的用于Ⅲ-Ⅴ族氮化物生长的衬底的一种优选方案，所述半导体介质凸起为半导体介质包状凸起、半导体介质圆锥状凸起或半导体介质金字塔状凸起。表面较平缓的包状凸起可以有效提高后续发光外延结构(尤其是GaN基发光外延结构)的生长质量，因此是优选的。
作为本发明的用于Ⅲ-Ⅴ族氮化物生长的衬底的一种优选方案，所述凸起具有与所述缓冲层上表面相接的底面，底面形状为多边形、三角型、或圆形中的一种或多种的组合。
作为本发明的用于Ⅲ-Ⅴ族氮化物生长的衬底的一种优选方案，所述凸起还具有与所述底面平行的顶面，顶面为多边形、三角型、或圆形中的一种或多种的组合。
作为本发明的用于Ⅲ-Ⅴ族氮化物生长的衬底的一种优选方案，所述顶面与所述底面具有相同形状且小于底面。
作为本发明的用于Ⅲ-Ⅴ族氮化物生长的衬底的一种优选方案，所述顶面与所述底面具有不同形状且小于底面。
作为本发明的用于Ⅲ-Ⅴ族氮化物生长的衬底的制造方法的一种优选方案，所述生长衬底的材料为蓝宝石、SiC、Si及ZnO的一种。
作为本发明的用于Ⅲ-Ⅴ族氮化物生长的衬底的制造方法的的一种优选方案，所述缓冲层的厚度为50～600埃，优选100～500埃，更优选200～400埃。
作为本发明的用于Ⅲ-Ⅴ族氮化物生长的衬底的制造方法的一种优选方案，所述缓冲层为任何能通过退火再结晶形成六角对称结构晶体的非晶或多晶材料，其优选地选自以下的至少一种：采用金属有机化合物化学气相沉积法制备的AlxGa1-xN，0≤X≤0.5，优选 0≤X≤0.2，制备的温度范围为450～700℃，优选500～600℃；采用金属有机化合物化学气相沉积法制备的AlN，制备的温度范围为700～1000℃；采用溅射法制备的AlN层，所述AlN层的晶向为(0001)取向；BN；或ZnO。
作为本发明的用于Ⅲ-Ⅴ族氮化物生长的衬底的制造方法的一种优选方案，步骤2)采用等离子体增强化学气相沉积法(PECVD)于所述缓冲层表面形成半导体介质层，所述介质材料为SiO2，SiN、或SiON中至少一种，更优选SiO2。在一个优选实施方案中，采用PECVD由SiH4和N2O在250-350℃温度区间在等离子体反应环境下生成SiO2半导体介质层。
作为本发明的用于Ⅲ-Ⅴ族氮化物生长的衬底的制造方法的一种优选方案，步骤2)所述的半导体介质层的厚度为0.2～3μm，优选0.5～2μm。
本发明的用于Ⅲ-Ⅴ族氮化物生长的衬底的制造方法中，步骤3)中的将所述介质层刻蚀出间隔排列的多个凸起，是半导体工艺中非常普遍和常规的技术，为本领域技术人员已知，因此不再赘述。
作为本发明的用于Ⅲ-Ⅴ族氮化物生长的衬底的制造方法的一种优选方案，所述多个半导体介质凸起呈周期性间隔排列，半导体介质凸起的底部宽度为0.3～4μm，间距为0.1～2μm。原则上，半导体介质凸起的底部宽度越小，其间距也越小。
作为本发明的用于Ⅲ-Ⅴ族氮化物生长的衬底的制造方法的一种优选方案，步骤3)所述的半导体介质凸起为半导体介质包状凸起、半导体介质圆锥状凸起或半导体介质金字塔状凸起，优选半导体介质包状凸起。
作为本发明的用于Ⅲ-Ⅴ族氮化物生长的衬底的制造方法的一种优选方案，所述凸起具有与所述缓冲层上表面相接的底面，所述底面为多边形、三角型、圆形中的一种或多种的组合。
进一步地，所述半导体介质凸起为半导体介质包状凸起，步骤3)包括以下步骤：
3-1)于所述半导体介质层表面形成光刻胶层，并将所述光刻胶层制作成间隔排列的多个光刻胶块；
3-2)通过加热回流工艺使所述多个光刻胶块回流成多个包状的光刻胶块；
3-3)采用感应耦合等离子体刻蚀法将各该包状的光刻胶块的形状转移至所述半导体介质层，形成多个半导体介质包状凸起，且露出各该半导体介质包状凸起之间的缓冲层，用于后续GaN基发光外延结构的成核生长。
优选地，所述步骤3-1)中可通过曝光工艺或纳米压印工艺将所述光刻胶层制作成间 隔排列的多个光刻胶块，曝光工艺可以是步进式曝光或接触式曝光。
实施例
以下通过特定的具体实施例说明本发明的实施方式，本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用，本说明书中的各项细节也可以基于不同观点与应用，在没有背离本发明的精神下进行各种修饰或改变。
请参阅图1～图7。需要说明的是，本实施例中所提供的图示仅以示意方式说明本发明的基本构想，仅显示与本发明中有关的组件示意，而非对实际实施时的组件数目、形状、尺寸、制造方法及工艺窗口做出限定，其实际实施时各组件的型态、数量及比例可为一种随意的改变，且其组件布局型态也可能更为复杂。在实施例中所涉及的工艺条件在有效窗口内可以进行合理改变且达到本发明所揭示的效果。
实施例1
如图1～图7所示，本实施例提供一种用于GaN生长的衬底，其制造方法包括以下步骤：
1、如图1所示，在本实施例中，所述生长衬底101为市售的平片型蓝宝石衬底，其表面晶向(0001)，具有原子级的平整度。在本实施例中，使用的是免清洗的衬底，没有额外清洗，直接使用。将上述衬底放置在具有SiC保护层的石墨托盘之上送入MOCVD(金属有机物化学气相沉积法)反应室；在氢气气氛下将上述衬底加热到1100℃，并在该温度下保持10分钟；然后将衬底温度降低到550℃，向反应室同时通入氨气、三甲基铝(TMAl)和三甲基镓(TMGa)，其中氨气的标准流量为56升/分钟、TMAl和TMGa的摩尔流量分别为3.25e-5和2.47e-4摩尔/分钟，反应室的压力为500torr，通入时间为215秒。如图2所示，在上述条件下在生长衬底101上形成AlxGa1-xN缓冲层的厚度为300埃，其中x＝0.2。
2、如图3所示，完成缓冲层102的生长之后，利用PECVD(等离子体增强化学气相沉积法)于所述缓冲层102表面形成SiO2层103，厚度为1微米。PECVD反应腔中的温度为350℃，压力为1torr(一个标准大气压为760torr)，SiH4和N2O的流量分别为10sccm(标准毫升/分钟)和300sccm，射频电源功率 为30W，
3、介质层图形的形成。如图4～图7所示，形成的图形为周期性间隔排列的SiO2凸起，排列方式为六角密堆积，周期为3μm，SiO2凸起的底部宽度为2μm，间距为1μm。
具体地，步骤3)包括以下步骤：
如图4～图5所示，首先进行步骤3-1)，于所述SiO2层103表面涂布1μm光刻胶层104，通过曝光工艺将所述光刻胶层104制作成以六角密堆积方式排列的光刻胶圆柱105，六角密堆积的周期为3μm，光刻胶圆柱的直径为2μm，间距为1μm。
如图6所示，然后进行步骤3-2)，通过加热回流工艺使所述多个光刻胶圆柱回流成半球形，其中，回流温度130摄氏度和回流时间120秒。
如图7所示，最后进行步骤3-3)，采用感应耦合等离子体刻蚀法(ICP)将各该半球形的光刻胶图形转移至所述SiO2层103，形成多个SiO2包状凸起，且露出各SiO2包状凸起之间的缓冲层102，用于后续GaN外延材料的外延生长。上述ICP刻蚀的工艺条件为：刻蚀气体为CHF3(三氟甲烷)，其标准流量为50毫升/分钟；ICP的上电极功率为1000W，下电极功率为50W。
4、最后，使用丙酮，清洗掉上述SiO2表面残余的光刻胶，再用稀盐酸清洗掉上述SiO2凸起表面及暴露出的缓冲层表面上的其他污染物，即可直接用于GaN的外延生长。
使用相同的MOCVD设备，在蓝宝石图形化衬底(PSS)上和在使用本发明所揭示的上述步骤制备的新型图形衬底上分别外延生长厚度为6微米的GaN外延层。MOCVD的具体生长条件为：生长温度为1050摄氏度，从室温到生长温度升温退火时间为15分钟；反应室压力为500torr；氨气的标准流量为56升/分钟；TMGa的摩尔流量1.5e-3摩尔/分钟，生长时间为150分钟。
通过XRD(x-射线双晶衍射)谱线表征晶体外延层质量，XRD谱线的半峰宽越小表明晶体外延层中的位错密度越小，晶体质量越高。测试结果表明，生长在常规PSS衬底上的GaN外延层的XRD(002)和(102)衍射峰的半峰宽分别为280和302弧秒，本发明制备的新型图形衬底上的GaN外延层的XRD(002)和(102)衍射峰的半峰宽分别为243和258弧秒。通过上述实验可以明显地得出：上述步骤制备的新型图形衬底比常规PSS衬底上生长的GaN外延层具有更好的质量。
另外还对采用两种衬底生长出的LED器件进行了出光效率的测定。采用本发明衬底制备的LED的发光效率相对于常规PSS衬底有比较大的提高。常规PSS衬底制造的3528LED芯片封装后的光通量平均为18.30lm；而采用本发明衬底的LED芯片的光通量平均为19.23lm,发光效率提升5％以上。
实施例2
如图1～图7所示，本实施例提供一种用于GaN生长的衬底的制造方法，其基本步骤如实施例1，所不同处仅为第2步：所述的半导体介质层103为采用PECVD方法制备的SiN层，生长所述SiN层的原材料为NH3(氨气)和SiH4(硅烷)，生长温度是400℃，SiH4流量20sccm,NH3为17sccm,N2为980sccm，压力为0.8torr。
使用相同的MOCVD设备，在基本相同生长条件下，在常规PSS衬底上和在使用上述步骤制备的新型图形衬底上分别外延生长厚度为6微米的GaN外延层。在上述实验中生长在常规PSS衬底上的GaN外延层的XRD(002)和(102)衍射峰的半峰宽分别为280和302弧秒，生长在本发明制备的新型图形衬底上的GaN外延层的XRD(002)和(102)衍射峰的半峰宽分别为270和283弧秒。通过上述实验可以明显地得出：本发明的上述步骤制备的新型图形衬底比常规PSS衬底有更进一步的优势。
实施例3
如图1～图6所示，本实施例提供一种用于GaN生长的衬底的制造方法，其基本步骤如实施例1，其中，所述缓冲层102为采用物理气相沉积法(PVD)所制备的厚度为200埃的AlN层，所用靶材为Al靶，溅射气体为N2，衬底温度600摄氏度，溅射功率600W。得到的AlN为主要晶向为(0001)排列的柱状多晶。
使用相同的MOCVD设备，在基本相同生长条件下，在常规PSS衬底上和在使用上述步骤制备的新型图形衬底上分别外延生长厚度为6微米的GaN外延层。在上述实验中生长在常规PSS衬底上的GaN外延层的XRD(002)和(102)衍射峰的半峰宽分别为280和302弧秒，生长在本发明制备的新型图形衬底上的GaN外延层的XRD(002)和(102)衍射峰的半峰宽分别为237和253弧秒。通过上述实验可以明显地得出：本发明的上述步骤制备的新型图形衬底比常规PSS衬底有更进一步的优势。
上述实施例仅例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟悉此 技术的人士皆可在不违背本发明的精神及范畴下，对上述实施例进行修饰或改变。因此，举凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变，仍应由本发明的权利要求所涵盖。

Claims (22)

  1. 一种用于Ⅲ-Ⅴ族氮化物生长的衬底，其特征在于，至少包括：
    生长衬底；
    用于后续发光外延结构生长的缓冲层，所述缓冲层下表面结合于所述生长衬底表面；以及
    多个半导体介质凸起，间隔排列于所述缓冲层上表面，凸起底面与所述缓冲层上表面结合，各凸起之间露出缓冲层。
  2. 根据权利要求1所述的用于Ⅲ-Ⅴ族氮化物生长的衬底，其特征在于：所述生长衬底的材料为蓝宝石、SiC、Si及ZnO的一种。
  3. 根据权利要求1所述的用于Ⅲ-Ⅴ族氮化物生长的衬底，其特征在于：所述缓冲层的厚度为50～600埃。
  4. 根据权利要求1所述的用于Ⅲ-Ⅴ族氮化物生长的衬底，其特征在于：所述缓冲层为非晶或多晶材料，选自：采用金属有机化合物化学气相沉积法制备的AlxGa1-xN，0≤X≤0.5，制备的温度范围为450～700℃；采用金属有机化合物化学气相沉积法制备的AlN，制备的温度范围为700～1000℃；采用溅射法制备的AlN层，所述AlN层的晶向为(0001)取向；BN；或ZnO。
  5. 根据权利要求1所述的用于Ⅲ-Ⅴ族氮化物生长的衬底，其特征在于：所述凸起为SiO2、SiN、或SiON中的至少一种。
  6. 根据权利要求1所述的用于Ⅲ-Ⅴ族氮化物生长的衬底，其特征在于：所述凸起的高度为0.2～3μm。
  7. 根据权利要求1所述的用于Ⅲ-Ⅴ族氮化物生长的衬底，其特征在于：所述多个凸起呈周期性间隔排列，凸起的宽度为0.3～4μm，间距为0.1～2μm。
  8. 根据权利要求1所述的用于Ⅲ-Ⅴ族氮化物生长的衬底，其特征在于：所述半导体介质凸起为半导体介质包状凸起、半导体介质圆锥状凸起或半导体介质金字塔状凸起。
  9. 根据权利要求1所述的用于Ⅲ-Ⅴ族氮化物生长的衬底，其特征在于：所述凸起具有与所述缓冲层上表面相接的底面，底面形状为多边形、三角型、或圆形中的一种或多种的组合。
  10. 根据权利要求9所述的用于Ⅲ-Ⅴ族氮化物生长的衬底，其特征在于：所述凸起还具有与所述底面平行的顶面，顶面为多边形、三角型、或圆形中的一种或多种的组合。
  11. 根据权利要求9或10所述的用于Ⅲ-Ⅴ族氮化物生长的衬底，所述顶面与所述底面具有相同形状且小于底面。
  12. 根据权利要求9或10所述的用于Ⅲ-Ⅴ族氮化物生长的衬底，所述顶面与所述底面具有不同形状且小于底面。
  13. 一种用于Ⅲ-Ⅴ族氮化物生长的衬底的制造方法，其特征在于，至少包括以下步骤：
    1)提供一生长衬底，于所述生长衬底表面形成用于后续发光外延结构生长的缓冲层；
    2)于所述缓冲层表面形成半导体介质层；
    3)通过光刻工艺将所述介质层刻蚀出间隔排列的多个凸起，且露出各凸起之间的缓冲层。
  14. 根据权利要求13所述的用于Ⅲ-Ⅴ族氮化物生长的衬底的制造方法，其特征在于：所述生长衬底的材料为蓝宝石、SiC、Si及ZnO中的一种。
  15. 根据权利要求13所述的用于Ⅲ-Ⅴ族氮化物生长的衬底的制造方法，其特征在于：所述缓冲层的厚度为50～600埃。
  16. 根据权利要求13所述的用于Ⅲ-Ⅴ族氮化物生长的衬底的制造方法，其特征在于：所述缓冲层为选自以下的至少一种非晶或多晶材料：采用金属有机化合物化学气相沉积法制备的AlxGa1-xN层，0≤X≤0.5，制备的温度范围为450～700℃；采用金属有机化合物化学气相沉积法制备的AlN，制备的温度范围为700～1000℃；采用溅射法制备的AlN层，所述AlN层的晶向为(0001)取向；BN；或ZnO。
  17. 根据权利要求13所述的用于Ⅲ-Ⅴ族氮化物生长的衬底的制造方法，其特征在于：步骤2)采用等离子体增强化学气相沉积法于所述缓冲层表面形成介质层，所述介质材料为SiO2、SiN、或SiON中的至少一种。
  18. 根据权利要求13所述的用于Ⅲ-Ⅴ族氮化物生长的衬底的制造方法，其特征在于：步骤2)所述的介质层的厚度为0.2～3μm。
  19. 根据权利要求13所述的用于Ⅲ-Ⅴ族氮化物生长的衬底的制造方法，其特征在于：所述多个凸起呈周期性间隔排列，凸起的宽度为0.3～4μm，间距为0.1～2μm。
  20. 根据权利要求13所述的用于Ⅲ-Ⅴ族氮化物生长的衬底的制造方法，其特征在于：步骤3)所述的凸起为包状凸起、圆锥状凸起或金字塔状凸起。
  21. 根据权利要求20所述的用于Ⅲ-Ⅴ族氮化物生长的衬底的制造方法，所述凸起具有与所述缓冲层上表面相接的底面，所述底面为多边形、三角型、圆形中的一种或多 种的组合。
  22. 根据权利要求13所述的用于Ⅲ-Ⅴ族氮化物生长的衬底的制造方法，其特征在于：所述凸起为半导体介质包状凸起，步骤3)包括以下步骤：
    3-1)于所述半导体介质层表面形成光刻胶层，并通过曝光工艺或纳米压印工艺将所述光刻胶层制作成间隔排列的多个光刻胶块；
    3-2)通过加热回流工艺使所述多个光刻胶块回流成多个包状的光刻胶块；
    3-3)采用感应耦合等离子体刻蚀法将该包状的光刻胶块的形状转移至所述半导体介质层，形成多个半导体介质包状凸起，且露出各SiO2包状凸起之间的缓冲层，用于后续发光外延结构的生长。
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