JP2017504221A - Iii−v族窒化物半導体エピタキシャルウエハ、当該エピタキシャルウエハを含むデバイス及びその製造方法 - Google Patents
Iii−v族窒化物半導体エピタキシャルウエハ、当該エピタキシャルウエハを含むデバイス及びその製造方法 Download PDFInfo
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- 229910017083 AlN Inorganic materials 0.000 description 1
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 1
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Abstract
Description
a)前記半導体媒質層の表面にフォトレジスト層を形成し、露光工程又はナノインプリント工程によって、前記フォトレジスト層を間隔を置いて配列される複数のフォトレジストブロックに形成する。
b)誘導結合プラズマエッチング法により、当該フォトレジストブロックの形状を前記半導体媒質層へ転写し、複数の半導体媒質突起を形成するとともに、各突起間に前記エピタキシャルバッファ層を露出させる。
c)前記フォトレジストブロックを除去する。
102 エピタキシャルバッファ層
103 半導体媒質層
104 フォトレジスト層
105 フォトレジストブロック
106 こぶ状のフォトレジストブロック
107 半導体媒質突起
108 エピタキシャルトランジション層
109 n型エピタキシャル層
110 発光層
111 p型エピタキシャル層
112 透明電流拡散層
113 n電極
114 p電極
Claims (25)
- 1)基板(101)と、
2)上面及び前記基板と接触する下面を備えるエピタキシャルバッファ層(102)と、
3)前記エピタキシャルバッファ層の上面に間隔を置いて配列されて当該エピタキシャルバッファ層と接触する突起であって、各突起の間にエピタキシャルバッファ層を露出させる複数の半導体媒質突起(107)と、
4)前記半導体媒質突起と、これらの間に露出するエピタキシャルバッファ層を覆い、前記露出するエピタキシャルバッファ層に接触するとともに前記半導体媒質突起と接触して、半導体媒質突起を完全に覆い、半導体媒質突起間のスペースを完全に充填するエピタキシャルトランジション層(108)と、
5)前記エピタキシャルトランジション層の上面に位置し、下から上に向かって、n型エピタキシャル層(109)、発光層(110)及びp型エピタキシャル層(111)を含むエピタキシャル有効層と、を含むIII−V族窒化物半導体エピタキシャルウエハ。 - 前記基板は、Al2O3、SiC、Si、ZnO及びGaNから選択された材料からなることを特徴とする請求項1に記載のIII−V族窒化物半導体エピタキシャルウエハ。
- 前記エピタキシャルバッファ層の厚さは50〜600オングストロームであることを特徴とする請求項1に記載のIII−V族窒化物半導体エピタキシャルウエハ。
- 前記エピタキシャルバッファ層は、0≦X≦0.5であるAlXGa1-XN層、及び結晶方位(0001)のAlN層から選択されることを特徴とする請求項1に記載のIII−V族窒化物半導体エピタキシャルウエハ。
- 前記半導体媒質突起の高さは0.2〜3μmであることを特徴とする請求項1に記載のIII−V族窒化物半導体エピタキシャルウエハ。
- 前記半導体媒質突起は、SiO2、SiON及びSiNから選択された材料からなることを特徴とする請求項1に記載のIII−V族窒化物半導体エピタキシャルウエハ。
- 前記半導体媒質突起は底部の幅が0.3〜4μmであり、間隔が0.1〜2μmであることを特徴とする請求項1に記載のIII−V族窒化物半導体エピタキシャルウエハ。
- 前記半導体媒質突起は、底面及び少なくとも1つの側面を備え、前記底面と前記エピタキシャルバッファ層が接触するとともに、前記側面と前記エピタキシャルトランジション層が接触し、前記側面と前記底面が90度以下の夾角をなすことを特徴とする請求項1に記載のIII−V族窒化物半導体エピタキシャルウエハ。
- 前記半導体媒質突起が前記底面と平行な上面を備え、前記上面が、前記エピタキシャルトランジション層と接触するとともに、前記側面と90度以上の夾角をなすことを特徴とする請求項1に記載のIII−V族窒化物半導体エピタキシャルウエハ。
- 前記半導体媒質突起は、こぶ状、テーパー状及びピラミッド状から選択される形状を有することを特徴とする請求項1に記載のIII−V族窒化物半導体エピタキシャルウエハ。
- 前記エピタキシャルトランジション層の厚さは半導体媒質突起の高さよりも大きく、0.5〜10μmであることを特徴とする請求項1に記載のIII−V族窒化物半導体エピタキシャルウエハ。
- 前記エピタキシャルトランジション層は、GaN、AlGaN、AlN、InGaN、InAlGaN及びこれらのn型又はp型ドーパントから選択された材料からなることを特徴とする請求項1に記載のIII−V族窒化物半導体エピタキシャルウエハ。
- 前記エピタキシャルウエハは、n型GaN層、InGaN多量子井戸(MQW)発光層及びp型GaN層を含むことを特徴とする請求項1に記載のIII−V族窒化物半導体エピタキシャルウエハ。
- 請求項1〜13のいずれか1項に記載のエピタキシャルウエハと、前記n型エピタキシャル層、p型エピタキシャル層にそれぞれ電気接続されるn電極(113)及びp電極(114)を含むIII−V族窒化物半導体デバイス。
- 1)基板(101)を提供し、
2)前記基板上にエピタキシャルバッファ層(102)を積層し、
3)前記エピタキシャルバッファ層上に半導体媒質(103)を積層し、前記半導体媒質層をパターニングすることで、間隔を置いて配列される複数の半導体媒質突起(107)を形成し、前記突起間に前記エピタキシャルバッファ層を露出させ、
4)前記エピタキシャルバッファ層の露出部分に、エピタキシャルトランジション層(108)の厚さが前記半導体媒質突起の高さよりも大きくなるまで当該エピタキシャルトランジション層を積層し、
5)前記エピタキシャルトランジション層の上面にエピタキシャル有効層を成長させ、前記エピタキシャル有効層が、下から上に向けて、n型エピタキシャル層(109)、発光層(110)、p型エピタキシャル層(111)を含むことを特徴とするIII−V族窒化物半導体エピタキシャルウエハの製造方法。 - 前記方法は、ステップ3)と4)の間に、ステップ3)で取得した基板をアニールすることで前記エピタキシャルバッファ層の露出部分に結晶核を形成するステップ3’)を更に含むことを特徴とする請求項15に記載の方法。
- 前記基板は、Al2O3、SiC、Si、ZnO及びGaNから選択された材料からなることを特徴とする請求項15に記載の方法。
- 前記エピタキシャルバッファ層の厚さは50〜600オングストロームであることを特徴とする請求項15に記載の方法。
- 前記エピタキシャルバッファ層は、0≦X≦0.5であるAlXGa1-XN、及び結晶方位(0001)のAlN層から選択されることを特徴とする請求項15に記載の方法。
- 前記半導体媒質突起は高さ0.2〜3μmであり、SiO2、SiN及びSiONから選択された材料からなることを特徴とする請求項15に記載の方法。
- 前記エピタキシャルトランジション層は厚さ0.5〜10μmであり、GaN、AlGaN、AlN、InGaN、InAlGaN及びこれらのn型又はp型ドーパントから選択された材料からなることを特徴とする請求項15に記載の方法。
- 前記半導体媒質層をパターニングすることで間隔を置いて配列される複数の半導体媒質突起を形成するステップは、
a)前記半導体媒質層の表面にフォトレジスト層を形成し、露光工程又はナノインプリント工程によって、前記フォトレジスト層を間隔を置いて配列される複数のフォトレジストブロックに形成するステップと、
b)誘導結合プラズマエッチング法により、フォトレジストブロックの形状を前記半導体媒質層へ転写し、複数の半導体媒質突起を形成するとともに、各突起間に前記エピタキシャルバッファ層を露出させるステップと、
c)前記フォトレジストブロックを除去するステップと、を含むことを特徴とする請求項15に記載の方法。 - ステップa)とb)の間に、加熱還流工程によって前記複数のフォトレジストブロックを複数のこぶ状のフォトレジストブロックとするよう還流させるステップa’)を更に含むことを特徴とする請求項22に記載の方法。
- 前記エピタキシャルウエハは、n型GaN層、InGaN多量子井戸(MQW)発光層及びp型GaN層を含むことを特徴とする請求項15に記載の方法。
- 請求項1〜13のいずれか1項に記載のエピタキシャルウエハ上に、前記n型エピタキシャル層、p型エピタキシャル層にそれぞれ電気接続されるn電極及びp電極を形成するIII−V族窒化物半導体デバイスの製造方法。
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